JPH07235830A - Reception signal processing unit for array antenna - Google Patents

Abstract

PURPOSE:To provide an array antenna signal processing unit with simple circuit configuration which executes an arithmetic processing for forming a multi-beam at a higher speed than that of a conventional processing unit. CONSTITUTION:The reception signal processing unit executes the reception signal processing including quasi-orthogonal detection processing, low frequency filtering processing, and multi-beam synthesis processing employing Fourier transformation for plural reception signals received by an array antenna comprising plural prescribed antenna elements 1 arranged closely in a prescribed linear or 2-dimension arrangement and is provided with plural arithmetic circuits 5 whose number is matched with the number of the antenna elements 1 executing the reception signal processing, the plural arithmetic circuits 5 are interconnected by a linear data bus or plural 2-dimension lattice form data buses depending on the arrangement of the plural antenna elements 1, and the plural arithmetic circuits 5 executes plural sets of processing divided to execute the reception signal processing respectively by sending/receiving data required for the signal processing simultaneously through the data buses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a received signal processing device for an array antenna.

[0002]

2. Description of the Related Art For various communication systems, particularly mobile communication systems, active phased array antennas capable of easily controlling the main beam direction to a mobile receiving radio station have been researched and developed. With the progress of digital signal processing technology, a beamforming antenna is being researched and developed as one of array antennas having various functions (for example, Rei Ito et al., "Prototype of DBF antenna", IEICE Technical Report). , SANE88
-54, January 27, 1989 (hereinafter referred to as Reference 1). ). The beamforming antenna can be classified into two types depending on whether the signal processing is performed in analog or digital.

In a beamforming antenna using analog signal processing, a plurality of phase shifters connected to an array antenna composed of a plurality of antenna elements arranged in parallel are changed to change the analog signal output of each antenna element. By synthesizing at the high frequency circuit stage or the intermediate frequency stage, the main beam direction of the array antenna can be directed to the predetermined direction θk. For example, in the case of an array antenna including a plurality of N antenna elements arranged in a straight line at equal intervals d, the phase set value φn of each phase shifter
(N = 1, 2, ..., N) is expressed by the following equation 1.

[0004]

[Formula 1] φn = n · Δφk

## EQU2 ## Δφk = (2πd sin θk) / λ where λ is the wavelength of the received signal.

Here, the signal output of each antenna element is Sn
Then, the combined output signal SC is expressed by the following expression 3.

[Equation 3]

On the other hand, a beam forming antenna using digital signal processing (hereinafter referred to as a DBF antenna).
In the above, each antenna element is connected to a receiver including an A / D converter, and based on output signals Sn (n = 0, 1, 2, ..., N-1) from each A / D converter. Then, using Equation 3 above, beamforming is performed by performing complex number multiplication and addition on the received signal by one digital signal processor (hereinafter referred to as DSP).

Further, the beam combining method in the above DBF antenna is disclosed in the above document 1, and a method using the discrete Fourier transform and a method using the fast Fourier transform are disclosed as the beam combining method.

The beam combining method by the former method will be described below. A plurality of N antenna elements linearly x
₁ , x ₂ , ..., x _N are juxtaposed at respective positions, and the complex reception signal when the radio wave radiated from the angle θ when viewed from the array antenna is received by the i-th antenna element is S (θ,
Given i), consider that the beamforming method in the DBF antenna extracts the component from the predetermined angle θk method based on the received signal sampled on the spatial axis. The antenna beam is defined as showing the spatial distribution of received power,
If the direction of the maximum value is called the main beam direction, that is, the main beam direction is θk, the antenna beam B
k (θ) is S * (θk, i) (i = 0, 1, 2, ...,
The matched filter signal output Bk (θ) having N−1) as a reference function can be defined by the following equation 4.
Here, * represents a complex conjugate.

[0009]

[Equation 4]

At this time, the signal-to-noise power ratio (SNR) of the antenna beam Bk (θ) becomes maximum. Here, the amplitude of the incoming radio wave is A ₀ , the phase is φ ₀ , each antenna element amplitude pattern is Ai (θ, i), the phase pattern is φi (θ, i), and the gain of each receiver is A
₂ (i), the signal output S (θ, i) of the receiver is expressed by the following equation 5.

[0011]

## EQU5 ## S (θ, i) = A ₀ A ₁ (θ, i) A ₂ (i) exp [j
{φ ₀ + φ ₁ (θ, i) + φ ₂ (i) + (2π x _i sin θ)
/ Λ}]

Therefore, the antenna beam Bk (θ) is expressed by the following equation 6.

[Equation 6] · Exp [j {φi (θ , i) -φ i (θk, i) + {2πx i (si
nθ-sinθk) / λ}]

As is clear from the above formula 6, since the electric field vectors of the respective elements in the θk direction are in phase, the antenna beam Bk (θ) can maximize the output SNR in the θk direction. The side lobe characteristics are the gain A ₁ (θ, i) of each antenna element and the gain A ₂ (i) (i =
0, 1, 2, ..., N-1), and the desired characteristics are not always obtained. Therefore, in order to suppress the side lobe, the weighting factor W is added to the signal output of each receiver.
(I) Weighting is performed by multiplying (i = 0, 1, 2, ..., N-1). The weighting factor W (i) is generally
For example, a window function W (i) such as a Hamming function, a Hamming Taylor function, and a Dolph Chebyshev function, and a gain correction term of an antenna element and a receiver, Represented by 7.

[0014]

(7) W (i) = w (i) / [√ {Eθ [│S (θ, i)
│ ² ]}] ・ │S (θk, i) │]

Here, Eθ [] represents an average value regarding θ. The antenna pattern Bk (θ) at this time is represented by the following Expression 8.

[0016]

[Equation 8] ・ S * (θk, i) / {│S (θk, i) │}

Further, the following Expression 9 can be obtained from the above Expression 8.

[0018]

[Equation 9] ・ Exp [-j {φ ₀ + φ ₁ (θk, i) + φ ₂ (i) + (2πx _i
sin θk) / λ}]

As is clear from the above equation 9, generally, in order to form an antenna beam having an arbitrary angle θk as the main beam direction, the number of antenna elements N per beam is N.
The number of complex product-sum operations required to meet the above condition is required, and N ² complex product-sum operations are required to form N multi-beams.

Next, the case of the latter method of the fast Fourier transform, which is easier to calculate, will be described below. Here, a plurality of N antenna elements of the array antenna are linearly arranged in parallel at equal intervals d, and the phase pattern φi (θ, i) (i = 0, 1, 2, 3, ..., N of each antenna element). −
It is assumed that 1) is independent of the angle θ of the main beam direction of the array antenna, that is, the phase pattern φi (i) = φi (θ, i) of each antenna element. At this time, assuming that the gain is corrected using the following equation 10 prior to the beam formation, the antenna beam Bk (θ)
By combining the signal output of each receiver,
It is represented by 1.

[0021]

[Equation 10] Sf (θ, i) = S (θ, i) · w (i) /
^{_{[√ {Eθ [A 1 2}} (θ, i)]}] · exp [-j {φ 0 + φ 1
(I) + φ ₂ (i)}]

[Equation 11]

Here, when the number of multi-beams is made equal to the number of antenna elements, the main beam direction θk of each antenna element is set by the following equation 12.

[0023]

[Equation 12] θk = sin ⁻¹ (λk / Nd), k = −N / 2, −N / 2 + 1, ..., 0, ..., N / 2−1

At this time, the antenna beam Bk (θ) is
By matching the position of the antenna element,
It is represented by.

[0025]

[Equation 13] k = -N / 2, ..., 0, ..., N / 2-1

As is clear from the above equation 13, the antenna beam Bk (θ) is the corrected signal output Sf of the receiver.
It is a discrete Fourier transform of (θ, i), and a fast Fourier transform (hereinafter referred to as FFT) algorithm can be used. That is, the number of complex product sum operations required to form N multi-beams can be reduced to N log ₂ N instead of N ² . After forming the N multi-beams, for example, the signal having the maximum value can be selected and used as the reception signal.

[0027]

As a received signal processing device for the DBF antenna which performs the beam combining, the above-mentioned document 1 discloses an example using a mini computer, but one operation such as a mini computer is disclosed. When the arithmetic processing including the FFT arithmetic is executed by using the control device, the arithmetic processing is required many times even if the latter beam synthesizing method using the FFT arithmetic is used, and the signal processing is relatively slow. was there. Moreover, signal processing becomes very slow when the number of antenna elements increases.

The object of the present invention is to solve the above problems and to perform arithmetic processing for multi-beam formation at a higher speed than in the conventional example, and further, the signal processing for the array antenna having a simple circuit configuration. To provide a device.

[0029]

According to a first aspect of the present invention, there is provided a received signal processing device for an array antenna, wherein a plurality of predetermined antennas arranged in close proximity in a predetermined one-dimensional or two-dimensional arrangement shape. Array antenna reception that performs reception signal processing including quasi-orthogonal detection processing, low-frequency filtering processing, and multi-beam combining processing by Fourier transform on a plurality of reception signals received by the array antenna composed of the element (1) A signal processing device, comprising a plurality of arithmetic circuits corresponding to the number of the antenna elements (1) for executing the received signal processing, wherein the plurality of arithmetic circuits (5) are provided in the plurality of antenna elements. According to the arrangement shape of (1), one data bus of one dimension or a plurality of data buses (101-116) of two-dimensional lattice shape are connected, and the plurality of arithmetic circuits (5) are So Respectively, a plurality of processes divided so as to perform the received signal processing are simultaneously performed by transmitting and receiving data necessary for the signal processing via the data bus (101-116). And

The received signal processing device for an array antenna according to a second aspect is the received signal processing device for an array antenna according to the first aspect, wherein the plurality of arithmetic circuits (5) are provided.
Respectively, the data necessary for performing the received signal processing, the quasi-quadrature detection processing, the low frequency filtering processing,
And two multiplexers (34, 35) for selectively switching and outputting according to the multi-beam combining processing by the Fourier transform, and the two multiplexers (34, 35).
A multiplexer (36) for performing a multiplication of the two data output from (35), and said multiplexer (36)
An accumulator (36) for cumulatively adding and outputting a plurality of data as a result of multiplication executed by the accumulator, data obtained by the quasi-quadrature detection output by the accumulator (36), and data obtained by the low-frequency filtering process. A plurality of registers (51a, 51b, 52a, 5) for storing the data and the data after the multi-beam synthesis processing by the Fourier transform.
2b, 55), the data output from the accumulator (36) is input to the accumulator (36) by a predetermined process in the low-frequency filtering process and the multi-beam combining process by the Fourier transform. Cumulatively added, the data after the quasi-orthogonal detection processing, the data after the low-frequency filtering processing, and the data after the multi-beam combining processing by the Fourier transform are stored in the plurality of registers and output. It is characterized by

Further, the received signal processing device for an array antenna according to a third aspect is the received signal processing device for an array antenna according to the first or second aspect, in which the plurality of arithmetic circuits (5) are each provided with the data bus ( 101-116)
The processing executed by transmitting and receiving the data necessary for the signal processing via the above is a multi-beam combining processing by the Fourier transform.

Further, the received signal processing device for an array antenna according to claim 4 is the received signal processing device for an array antenna according to any one of claims 1 to 3, wherein each of the plurality of arithmetic circuits (5) has the register ( 52a, 52b) and the data bus (101-116), and selectively switches the data necessary for the multi-beam combining processing by the Fourier transform and outputs the data to the one multiplexer (34). 64) is further provided.

Further, the received signal processing device for an array antenna according to claim 5 is the received signal processing device for an array antenna according to any one of claims 1 to 4, wherein the low-pass filtering process is a transversal finite impulse response. System low pass filter processing, the plurality of arithmetic circuits (5)
Are further provided with FIFO memories (61a, 61b) for storing the data output from the registers (51a, 51b) for storing the data after the quasi-quadrature detection processing.

[0034]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a received signal processing device for an array antenna which is an embodiment according to the present invention. The received signal processing device for an array antenna of this embodiment is
16 array antennas arranged side by side in a two-dimensional matrix shape having two axes that are orthogonal to each other at equal intervals
Corresponding to the individual antenna elements 1-1 to 1-16 (collectively referred to as reference numeral 1), a quasi-quadrature detection circuit, a transversal FIR (finite impulse response) low frequency pass filter, and a so-called spatial domain are provided. For executing circuit operation including a multi-beam combining circuit using the two-dimensional FFT operation
P5-1 to 5-16 are provided, and the 16 DSPs
1 to 5-16 are connected in a grid shape via data buses 101 to 108 as shown in FIG.
P5-1 to 5-16 are ASICs (Applicat.) Dedicated to the digital reception signal processing of the array antenna having the circuit of FIG.
Ion Specific Integrated Circuit) It is characterized by being configured using a computing unit.

As shown in FIG. 1, the antenna element 1-1 includes a down converter 2-1, a bandpass filter 3-1, an A / D converter 4-1, and a DSP which are connected in cascade.
5-1 is connected to the antenna element 1-2, and the antenna element 1-2 is connected to the down converter 2-2, the band pass filter 3-2, the A / D converter 4-2, and the DSP 5-2 which are connected in cascade. And antenna elements 1-3 to 1-1 in the same manner.
5 is connected to the same one, and the antenna element 1-
16 is a down converter 2 connected in series with each other.
-16, band pass filter 3-16, and A / D converter 4-
61 and DSP5-16 are connected. Here, the down converters 2-1 to 2-16 (collectively referred to as reference numerals 2) are configured by similar circuits, and the band pass filters 3-1 to 3-16 (collectively referred to as reference numeral 3). Are similar to each other, and A / D converters 4-1 to 4-16 (generally referred to as reference numeral 4) are similar to each other and DSPs 5-1 to 5-. Reference numeral 16 (generally denoted by reference numeral 5) is composed of circuits similar to each other except that the operation data and the operation method are different, as will be described later in detail. Therefore, the operation of each circuit will be described on behalf of only one.

A high frequency signal, such as a microwave signal, of the radio wave received by the antenna element 1 is input to the down converter 2, and the down converter 2 converts the input high frequency signal into an intermediate frequency signal having a predetermined intermediate frequency. (Hereinafter, referred to as an IF signal), and is converted to A through a band pass filter 3 that removes unnecessary harmonic components.
Output to the / D converter 4. The A / D converter 4 performs A / D conversion of the input IF analog signal into an IF digital signal at a sampling frequency of 128 kHz, for example, and the DSP 5
Output to.

Next, the DSP 5 is constructed as will be described in detail later, and multiplies the input IF digital signal using quasi-quadrature detection, transversal FIR low frequency pass filtering, and two-dimensional FFT operation. The calculation including the beam combining and the sum of squares calculation is executed, and the digital signal of the calculation result is output to the comparator circuit 6. Where 16 DS
As shown in FIG. 3, P5-1 to P5-16 are connected via data buses 101 to 104 wired in the X-axis direction and data buses 105 to 108 wired in the Y-axis direction orthogonal to the Y-axis direction. Are connected in a grid pattern. Data bus 10
1 is connected to the DSPs 5-1 to 5-4, and the data bus 1
02 is connected to the DSPs 5-5 to 5-8, the data bus 103 is connected to the DSPs 5-9 to 5-12, and the data bus 104 is connected to the DSPs 5-13 to 5-16. On the other hand, the data bus 105 is connected to the DSPs 5-1, 5-5,
5-9, 5-13, the data bus 106 DS
P5-2, 5-6, 5-10, 5-14, and the data bus 107 is connected to the DSP 5-3, 5-7, 5-11, 5
-15, the data bus 108 is connected to the DSP 5-4,
5-8, 5-12, 5-16.

Further, the comparator circuit 6 is composed of a plurality of comparators and has the maximum signal power among the plurality of digital signals after multi-beam formation inputted from the 16 DSPs 5-1 to 5-16. After selecting the digital signal,
Output to demodulator 7. The demodulator 7 performs, for example, PSK demodulation processing on the input digital signal, and then outputs it as a reception data signal.

FIG. 2 shows each of the DSPs 5-1 to 5-16 shown in FIG.
It is a block diagram showing the function of. As shown in FIG.
The IF digital signal input from the / D converter 4 is transmitted by the sync distributor 11 to I channels (I
ch) and Q channel (Qch), the two IF digital signals synchronized with each other are distributed. On the other hand, the local oscillator 20 generates a local oscillation digital signal having a predetermined local oscillation frequency of, for example, 32 kHz,
The first local oscillation digital signal is output to the multiplier 12, and is also output to the multiplier 22 via the π / 2 phase shifter 21 that shifts the phase of the input digital signal by π / 2. Therefore, the multiplier 22 outputs π from the local oscillation digital signal.
The local oscillation digital signal phase-shifted by / 2 is input as the second local oscillation digital signal. Here, the local oscillator 20 and the π / 2 phase shifter 21 are connected to the DSPs 5-1 to 5-1.
It is not provided for every 6, but only one is provided in the device.

The IF digital signal for the I channel output from the synchronous distributor 11 is multiplied by the first local oscillation digital signal by the multiplier 12, and the digital signal of the multiplication result is equal to or higher than the Nyquist frequency of 16 kHz, for example. Transversal FI to eliminate unnecessary waves
It is input to the sum-of-squares circuit 15 via the FIR low-pass filter 13 that executes the R-system low-pass filtering process and the fast Fourier transformer 14 that executes the FFT operation for the multi-beam synthesis. On the other hand, the IF digital signal for the Q channel output from the synchronous distributor 11 is the multiplier 2
2 is multiplied by the second local oscillation digital signal, and the digital signal of the multiplication result is an FIR low frequency signal that performs low-pass filtering processing of the transversal FIR method in order to remove unnecessary waves of Nyquist frequency or higher. It is input to the sum-of-squares circuit 15 via the band-pass filter 23 and the fast Fourier transformer 24 that executes the FFT operation for the multi-beam combination. The transversal FI
The R low pass filters 13 and 23 are constituted by, for example, 50% roll-off filters. The sum-of-squares circuit 15 squares each digital signal input from the fast Fourier transformers 14 and 24, and then calculates the sum of the squared digital signals. That is, the sum-of-squares calculation is performed to represent the signal power level. And outputs to the comparator circuit 6.

Although not shown in FIG. 2, the I-channel spatial data digital signal output from the fast Fourier transformer 14 and the Q-channel spatial data digital signal output from the fast Fourier transformer 24 are , PSK demodulation for output to the demodulator 7.

FIG. 4 shows each of the DSPs 5-1 to 5-16 shown in FIG.
3 is a block diagram showing the circuit of FIG. As shown in FIG.
The IF digital signal output from the / D converter 4 is temporarily stored in the input register 31 and then input to the A input terminal of the input multiplexer 34. The I-channel FIFO (First-In First-Out) memory 61a or the Q-channel FIFO (First-In Fir), which will be described later in detail, respectively.
The digital signal after the quasi-quadrature detection read from the st-Out) memory 61b is input to the B input terminal of the input multiplexer 34 via the FIR output register 62.

The data lines B1 and B2 are connected to the data buses 101 to 1 in the X-axis direction, as shown in FIG.
On the other hand, the data lines B3 and B4 are connected to any one of the data buses 105 to 108 in the Y-axis direction as shown in FIG. 3 according to each DSP. Connected. The four data lines B1 to B4 are connected to the A input terminal, B input terminal, C input terminal, and D input terminal of the FFT multiplexer 64, respectively. The digital signal selected by the FFT multiplexer 64 is input to the C input terminal of the input multiplexer 34 via the FFT output register 65. The spatial data digital signal output from the two-way divider 56a or 56b, which will be described in detail later, is input to the D input terminal of the input multiplexer 34 and the C input terminal of the data multiplexer 35 via the spatial data output register 63.

Further, a ROM (FIG. 1) which is provided in a controller (not shown) which is constituted by an MPU and which controls the entire received signal processing apparatus, stores FIR data for FIR low-pass filtering. Not shown below
It is called FIRROM. The FIR data digital signal output from (1) is input to the A input terminal of the data multiplexer 35. Further, the FFT weight data digital signal output from the FFT weight ROM 33, which stores the FFT weighting coefficient data, is input to the B input terminal of the data multiplexer 35. Further, the weight data digital signal output from the beam forming weight ROM 32 which stores the weighting coefficient for two-dimensional multi-beam forming is input to the D input terminal of the data multiplexer 35.

The digital signal selected by the input multiplexer 34 is the multiplexer and accumulator 3
6 is input to the A input terminal of the data multiplexer 35.
The digital signal selected by is input to the B input terminal of the multiplexer and accumulator 36. The multiplexer and accumulator 36 is composed of a multiplexer and an accumulator, and multiplies the digital signal input to its A input terminal by the digital signal input to its B input terminal, and then, via the register 37, The register 51a, 51b, 52a, 52b, 53a, 53b, 5 is output to the accumulator IN terminal of the accumulator 36 and
It outputs to the input terminals of 4a, 54b, and 55. Here, the digital signals input to the accumulator-in terminals of the multiplexer and accumulator 36 are cumulatively added by the accumulator in the multiplexer and accumulator 36, and the accumulator is once for each FIR low-pass filtering process. Each FFT calculation and each calculation processing of the sum-of-squares circuit 15 is reset after data reading at the end of the calculation. As the multiplexer and accumulator 36, a circuit in which the multiplexer and the accumulator are integrated may be used, or a circuit in which the multiplexer and the accumulator are configured as separate circuits may be used.

(A) Post-detection register 51a: The digital signal after the quasi-quadrature detection of the I channel is temporarily stored and then stored in the FIFO memory 61a. (B) Post-detection register 51b: The digital signal after the quasi-orthogonal detection of the Q channel is temporarily stored and then stored in the FIFO memory 61b. (C) FIR register 52a: The digital signal after the FIR low-pass filtering of the I channel is temporarily stored and then output to the data line B1. (D) FIR register 52b: The digital signal after the FIR low-pass filtering of the Q channel is temporarily stored and then output to the data line B2. (E) FFT primary register 53a: The digital signal of the operation result of the first FFT operation of the real part, which will be described later in detail, is temporarily stored and then output to the data line B3. (F) FFT primary register 53b: The digital signal of the operation result of the first FFT operation of the imaginary part, which will be described later in detail, is temporarily stored and then output to the data line B4. (G) Spatial data register 54a: A spatial data output signal 63 and a demodulator via a distributor 56a after temporarily storing a spatial data digital signal, which is a calculation result of a second FFT calculation of a real part described later in detail. Output to 7. (H) Spatial data register 54b: After spatially storing a spatial data digital signal which is the calculation result of the second FFT calculation of the imaginary part, which will be described later in detail, the spatial data output register 63 and the demodulator via the distributor 56b. Output to 7. (I) Power data register 55: The power data digital signal output from the sum of squares circuit 15 is temporarily stored and then output to the comparator circuit 6.

The registers 51a, 51b, 52 are
A 3-state buffer amplifier is provided at the final stage of a, 52b, 53a, 53b. This is the register 51a, 5
For 1b, when reading data from the FIFO memories 61a and 61b, the three-state buffer amplifier at the final stage is opened, and the data line B from another DSP
This is because the 3-state buffer amplifier at the final stage is opened when data is output to 1 to B4.

Next, the two-dimensional fast Fourier transform method used in this embodiment will be described below. This is an extension of the one-dimensional fast Fourier transform method described in the section of the prior art. Here, as mentioned above,
A plurality of N (N = 16 in this embodiment) antenna elements 1 of the array antenna are arranged in parallel in a two-dimensional matrix shape at equal intervals d, and the input signal of each antenna element is Skm (θ) (k = 0,1, ..., N-1; m = 0,1,
, N-1), the result of the Fourier transform of the first dimension is expressed as in Expression 14. Here, k is a coordinate in the first-dimensional Fourier transform, and m is a coordinate in the second-dimensional Fourier transform. Combined beam output Bkm (k = 0,
, ..., N-1; m = 0, 1, ..., N-1) is the result of the second-dimensional Fourier transform, and is expressed as in Equation 15 using the result of the first-dimensional Fourier transform. To be done.

[0049]

[Equation 14] k = 0, 1, 2, 3, ..., N-1; m = 0, 1, 2,
3, ..., N-1

[0050]

[Equation 15] k = 0, 1, 2, 3, ..., N-1; m = 0, 1, 2,
3, ..., N-1

Here, the relationship between the direction θkm of the multi-beam and the beams obtained by the Fourier transform can be expressed by the following equation 16. In Expression 16, the multi-beam direction θkm is expressed in the form of (x, y), where x is an angle in the XZ plane with respect to the Z axis, and y is with respect to the Z axis in the YZ plane. It is the angle.

[0052]

Θkm = [sin ⁻¹ {sin (−2π · k /
N)}, sin ⁻¹ {sin (−2π · m / N)}] k = 0, 1, 2, 3, ..., N-1; m = 0, 1, 2,
3, ..., N-1

As is clear from the equations (14) and (15), the antenna beam Bkm is the signal output Skm of the receiver.
Since it is a discrete Fourier transform of, the FFT algorithm can be used. That is, the number of complex operations required to form N multi-beams can be reduced to Nlog ₂ N times instead of N ² times. After forming the N multi-beams, for example, by selecting the maximum value signal among them,
It can be the received signal. The antenna beam Bkm of the equation 15 corresponds to the signals of the spatial data registers 54a and 54b of FIG. 4 of this embodiment.

5 to 9 are first timing charts showing the operations of the DSPs 5-1 to 5-16 shown in FIG. 1. First, the operation of the DSP 5-1 will be described with reference to the timing charts. In the timing chart, “state” is a serial number given for convenience of description according to the clock, “function” is a processing function executed by the DSP, and “input MUX” is an input selected by the input multiplexer 34. "Data MUX" indicates an input terminal selected by the data multiplexer 35, and "FFTMUX" indicates an input terminal selected by the FFT multiplexer 64. Here, "X" represents indefinite. Further, "output enable" indicates a register whose output is enabled, and "input latch trigger" indicates a register which is input latched. The input multiplexer 34, the data multiplexer 35, and the switching signal of the input terminals of the FFT multiplexer 64, and
The output enable signal and the input latch trigger signal to each register shown in FIG. 3 are generated by the controller (not shown) or a timing signal generation circuit (not shown) controlled by the controller.

As shown in FIG. 5, in the state 1,
The input multiplexer 34 is switched to the A input terminal, and the data multiplexer 35 is switched to the D input terminal. At this time, the received data signal output from the A / D converter 4-1 is input to the A input terminals of the multiplexer and accumulator 36 via the A input terminals of the input register 31 and the input multiplexer 34, while the beam forming is performed. The data digital signal read from the weight wait ROM 32 is passed through the D input terminal of the data multiplexer 35 to the multiplexer and accumulator 36.
Is input to the B input terminal of. Then, the multiplexer / accumulator 36 multiplies the two input digital signals to make all the IF digital signals in phase,
That is, every time the sampling is performed, the phases φij of all IF digital signals are 0 °, 90 °, 180 °, and 270 °.
And the processing for generating the IF digital signal after the quasi-quadrature detection is executed. Then, at the end of state 1, the input latch trigger signal to the post-detection register 51a rises, the data digital signal of the multiplication result is stored in the post-detection register 51a via the register 37, and then stored in the FIFO memory 61a. The F
The IFO memory 61a stores nine I-channel data digital signals after quasi-quadrature detection up to 9 clocks before the present, for the transversal FIR low-pass filtering process which is the next process. .

Next, in states 2 to 10,
The transversal FIR low pass filtering process is executed. First, in state 2, the input multiplexer 34 is switched to the B input terminal and the data multiplexer 35 is switched to the A input terminal. At this time, the data digital signal of the I channel after quasi-quadrature detection, which is read from the FIFO memory 61a 9 clocks before the present, is transmitted from the multiplexer and accumulator 36 via the FIR output register 62 and the B input terminal of the input multiplexer 34. Input to the A input terminal. on the other hand,
The FIR data digital signal read from the FIRROM is input to the B input terminal of the multiplexer and accumulator 36 via the A input terminal of the data multiplexer 35. Then, the multiplexer and accumulator 36 multiplies the two input digital signals and outputs the result to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. As a result, the data digital signal of the multiplication result is input to the multiplexer and the accumulator in the accumulator 36, and immediately before this, the accumulator is reset, so that 0 is added to the data digital signal of the multiplication result and Store in the accumulator.

Next, in the state 3, similarly to the state 2, the input multiplexer 34 is switched to the B input terminal and the data multiplexer 35 is switched to the A input terminal.
Can be switched to the input terminal. At this time, the data digital signal of the I channel after the quasi-quadrature detection, which is read from the FIFO memory 61a 8 clocks before the present, is the FIR signal.
It is inputted to the A input terminal of the multiplexer and accumulator 36 via the output register 62 and the B input terminal of the input multiplexer 34. On the other hand, the FIR data digital signal read from the FIRROM is input to the B input terminal of the multiplexer and accumulator 36 via the A input terminal of the data multiplexer 35. Then, the multiplexer and accumulator 36 multiplies the two input digital signals and outputs the result to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. As a result, the data digital signal of the multiplication result is input to the multiplexer and the accumulator in the accumulator 36. At this time, the input data digital signal of the multiplication result is in the state 2
Is added to the data digital signal of the multiplication result and stored in the accumulator.

Similarly, in states 4 to 10, F
The processing for IR low-pass filtering is executed, and as shown in FIG.
Since the output enable signal to a rises, the data digital signal of the I channel after quasi-quadrature detection stored in the register 51a in the state 9 at this timing is FIF.
It is written in the O memory 61a. Further, as shown in FIG. 5, at the timing of the end of the state 10, the FIR
FIR which is the result of the final product-sum operation of low-pass filtering
The low-pass filtered I-channel data digital signal is input from the multiplexer and accumulator 36 to the FIR register 52a via the register 37 and is temporarily stored therein.

Further, in states 11 to 20,
Similar to the above states 1 to 10, the Q channel IF
Quasi-quadrature detection and FIR low-pass filtering are performed on the digital received signal. Then, as shown in FIG. 6, at the intermediate timing of the state 19, the register 51b
Since the output enable signal to the signal rises, the Q channel data digital signal after quasi-quadrature detection stored in the register 51b in the state 19 at this timing is FIF.
It is written in the O memory 61b. Further, as shown in FIG. 6, at the intermediate timing of the state 20, the register 5
Since the output enable signal to 2a and 52b rises, the FIs stored in the registers 52a and 52b are stored.
The I-channel and Q-channel data digital signals after the R low-pass filtering are input to the A input terminal and the B input terminal of the FFT multiplexer 64 via the data lines B1 and B2, respectively. Here, since the FFT multiplexer 64 selects the A input terminal from the intermediate timing of the state 20 to the intermediate timing of the state 21, the FIR low-pass filtering output to the data line B1 is performed. The data digital signal of the subsequent I channel is FF
It is input to the C input terminal of the input multiplexer 34 via the T multiplexer 64 and the FFT output register 65.

Then, the first FFT operation including four product-sum operations from states 21 to 24 is executed, and the second FFT operation including four product-sum operations from states 25 to 28 is executed. The methods of the first and second FFT operations are shown in Tables 1 to 4 below.

[0061]

[Table 1]

[0062]

[Table 2]

[0063]

[Table 3]

[0064]

[Table 4]

In Table 1, "original data DR" is a data digital signal after FIR low-pass filtering stored in the FIR register 52a or 52b in the arithmetic DSP in the right column, that is, for example, FIR of DSP5-1
The register 52a stores the original data I (0) of the I channel, and the FIR register 5 of the DSP 5-1.
The original data Q (0) of the Q channel is stored in 2b,
The FIR register 52a of the DSP5-2 stores the original data I (1) of the I channel, and the DSP5-
The second FIR register 52b stores the Q channel original data Q (1).
Is similar to. “Data X” is data for the first FFT operation and is the original data DR.
The data X is the register 52a or 5 of the same DSP.
2b to the A input terminal or the B input terminal of the FFT multiplexer 64 via the data line B1 or B2, or the data bus 101 to 1 from another DSP.
08 via any one of the data lines B1 or B2
The data is input to the A input terminal or the B input terminal of the FT multiplexer 64 and then input to the C input terminal of the input multiplexer 34 via the FFT output register 65. The “multiplication coefficient Wx” is a multiplication coefficient for the first FFT operation, and is data that is input to the B input terminal of the data multiplexer 35 after being read from the FFT weight ROM 33. The “result data D1” is the data of the result of the so-called product-sum operation, that is, the result data of the first FFT operation, in which the product operation of the data X and the multiplication coefficient Wx is repeated four times and the sum thereof is obtained. . For example, in the uppermost four-stage calculation example of Table 1 (hereinafter referred to as the first calculation example), I (0) × 1, I (1) × 1, and I (0) × 1
The product of (2) × 1 and I (3) × 1 is executed four times,
The sum of these four products becomes I '(0), the data D1 is stored in the FFT primary register 53a or 53b, and is used for the second FFT operation described below. The first FFT operation is similarly executed as shown in Tables 1 to 4 below.

"Data Y" is data for the second FFT operation, and is the register 53a or 53 of each DSP.
b, and if necessary, via the data line B3 or B4, the FFT multiplexer 64 of the same DSP.
Is input to the C input terminal or the D input terminal of, or is input to the C input terminal or the D input terminal of the FFT multiplexer 64 of another DSP via the data line B3 or B4,
Then, it is input to the C input terminal of the input multiplexer 34 via the FFT output register 65. “Multiplication coefficient W
y ”is a multiplication coefficient for the second FFT operation and is F
The data is read from the FT weight ROM 33 and then input to the B input terminal of the data multiplexer 35. The “result data D2” is the data Y and the multiplication coefficient Wy.
The product data of the so-called product-sum operation, that is, the second FFT
This is the result data of the calculation. For example, in the first calculation example shown in the top four rows of Table 1, I ′ (0) × 1 and I ′ (1)
The product of × 1, I ′ (2) × 1, and I ′ (3) × 1 is executed four times, and the sum of these four products becomes I ″ (0). The second FFT operation is performed in the same manner thereafter. The result data D2 is stored in the spatial data register 54a or 54b and then used in the processing corresponding to the function of the next square sum circuit 15.

The first FFT operation is an FFT operation in the horizontal direction (X axis direction) in FIG. 3, and the second FFT operation is an FFT operation in the vertical direction (Y axis direction) in FIG. In addition, F shown in Tables 1 to 4
The FT operation corresponds to the above Equations 14 and 15 and the following Equation 1
It is represented by 7 and number 18.

[0068]

[Equation 17] k = 0, 1, 2, 3

[Equation 18] m = 0, 1, 2, 3

Here, the number of antenna elements in the X-axis direction,
Since the number of antenna elements in the Y-axis direction is 4, N in Equations 14 and 15 is 4, and as is clear from Equations 17 and 18, the left half of the FFT operation shown in Tables 1 to 4 Is the FFT in the horizontal direction (X-axis direction), and the right half is the FFT in the vertical direction (Y-axis direction).

FFT1 to FFT4 in FIG.
First FFT for channel IF digital received signal
In the operation 24, the I-channel result data D1 is calculated, FFT5 to FF8 are the first FFT operations for the Q-channel IF digital received signal, and in the state 28, the Q-channel result data D1 is calculated. To be done. In addition, FFT9 to FF12 in FIG.
Is the second FFT operation for the I channel IF digital received signal, the result data D2 of the I channel is calculated in state 29, and FFT13 to FFT16 are
Second FF for Q channel IF digital received signal
This is a T operation, and the result data D2 of the Q channel is calculated in the state 36. 7 and 8 show the DSP5-
Since it is a timing chart for No. 1, the I-channel FFT processing and the Q-channel FFT processing can be classified, but cannot be classified in other DSPs as shown in Tables 1 to 4.

The operation of the DSP 5-1 will be described with reference to FIG. 7. In the state 21, the input multiplexer 34 is switched to the C input terminal, while the data multiplexer 35 is switched to the B input terminal. At this time, the data X is transferred from the FFT multiplexer 64 to F
C of the FT output register 65 and the input multiplexer 34
Multiplexer and accumulator 3 via input terminal
While being input to the A input terminal of 6, FFT weight R
The data digital signal of the multiplication coefficient Wx read from the OM 33 is input to the B input terminal of the multiplexer and accumulator 36 via the B input terminal of the data multiplexer 35. Then, the multiplexer and accumulator 36 multiplies the two input digital signals,
It outputs to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. As a result, the data digital signal of the multiplication result is input to the multiplexer and the accumulator in the accumulator 36, and immediately before this, the accumulator is reset, so that 0 is added to the data digital signal of the multiplication result and Store in the accumulator. The calculation of FFT1 in the state 21 is I (0) × 1 in the first calculation example.

Next, in the state 22, as in the case of the state 21, the input multiplexer 34 is switched to the C input terminal and the data multiplexer 35.
Is switched to the B input terminal. At this time, the data X is input from the FFT multiplexer 64 to the A input terminal of the multiplexer and accumulator 36 via the FFT output register 65 and the C input terminal of the input multiplexer 34, while being read from the FFT weight ROM 33. The data digital signal having the multiplication coefficient Wx is input to the B input terminal of the multiplexer and accumulator 36 via the B input terminal of the data multiplexer 35.
Then, the multiplexer and accumulator 36 multiplies the two input digital signals and outputs the result to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. As a result, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. At this time, the data digital signal of the input multiplication result is
It is added to the data digital signal of the multiplication result multiplied in the state 21 and stored in the accumulator.
The calculation of FFT2 in the state 21 is I (1) × 1 + I (0) in the first calculation example.

In the same manner, the processing for the first FFT operation is executed in states 23 and 24. here,
The calculation of FFT3 in state 23 is I (2) × 1 + I (1) + I (0) in the first calculation example, and the calculation of FFT3 in state 24 is I (3) in the first calculation example. × 1 + I (2) + I (1) + I
(0) = I ′ (0) is calculated, and the calculation result of the state 24 is the result data D1 in Tables 1 to 4.

Then, as shown in FIG.
Since the input latch trigger signal to the register 53a rises at the timing of the end of, the data digital signal of the result data D1 which is the result of the first FFT operation is transferred from the multiplexer and accumulator 36 to the register 37.
It is input to the FFT primary register 53a via and is temporarily stored. Further, at the intermediate timing of the state 24 before this operation, as shown in FIG.
Since the output enable signal to a and 52b rises,
The data digital signals of the I channel and the Q channel after the FIR low-pass filtering stored in the registers 52a and 52b are F through the data lines B1 and B2, respectively.
It is input to the A input terminal and the B input terminal of the FT multiplexer 64. Here, since the FFT multiplexer 64 selects the B input terminal from the intermediate timing of the state 24 to the intermediate timing of the state 21, as shown in FIG. 7, the FIR low-pass filtering output to the data line B2 is performed. The subsequent Q channel data digital signal is input to the C input terminal of the input multiplexer 34 via the FFT multiplexer 64 and the FFT output register 65.

Further, in the state 25, the input multiplexer 34 is switched to the C input terminal,
The data multiplexer 35 is switched to the B input terminal. At this time, the data X is the FFT as described above.
While being input from the multiplexer 64 to the A input terminal of the multiplexer and accumulator 36 via the FFT output register 65 and the C input terminal of the input multiplexer 34, the data digital signal of the multiplication coefficient Wx read from the FFT weight ROM 33 is the data. It is input to the B input terminal of the multiplexer and accumulator 36 via the B input terminal of the multiplexer 35. Then, the multiplexer and accumulator 36 multiplies the two input digital signals and, via the register 37, the accumulator / accumulator of the multiplexer and accumulator 36.
Output to the IN terminal. As a result, the data digital signal of the multiplication result is input to the multiplexer and the accumulator in the accumulator 36, and immediately before this, the accumulator is reset, so that 0 is added to the data digital signal of the multiplication result and Store in the accumulator. FF in state 25
The calculation of T5 is Q (0) × 1 in the first calculation example.

Next, in the state 26, as in the case of the state 25, the input multiplexer 34 is switched to the C input terminal, and the data multiplexer 35.
Is switched to the B input terminal. At this time, the data X is input from the FFT multiplexer 64 to the A input terminal of the multiplexer and accumulator 36 via the FFT output register 65 and the C input terminal of the input multiplexer 34, while being read from the FFT weight ROM 33. The data digital signal having the multiplication coefficient Wx is input to the B input terminal of the multiplexer and accumulator 36 via the B input terminal of the data multiplexer 35.
Then, the multiplexer and accumulator 36 multiplies the two input digital signals and outputs the result to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. As a result, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. At this time, the data digital signal of the input multiplication result is
It is added to the data digital signal of the multiplication result multiplied in the state 25 and stored in the accumulator.
The calculation of FFT6 in the state 26 is Q (1) × 1 + Q (0) in the first calculation example.

In the same manner, the processing for the first FFT operation is executed in states 27 and 28. here,
The calculation of FFT7 in state 27 is Q (2) × 1 + Q (1) + Q (0) in the first calculation example, and the calculation of FFT8 in state 28 is Q (3) in the first calculation example. × 1 + Q (2) + Q (1) + Q
(0) = Q '(0) is calculated, and the calculation result of the state 28 is the result data D1 in Tables 1 to 4.

Then, as shown in FIG.
Since the input touch trigger signal to the register 53b rises at the timing of the end of, the data digital signal of the result data D1 which is the result of the first FFT operation is transferred from the multiplexer and accumulator 36 to the register 37.
It is input to the FFT primary register 53a via and is temporarily stored. At the intermediate timing of the state 27 before this operation, as shown in FIG.
Since the output enable signal to a and 53b rises,
The first F stored in the registers 53a and 53b, respectively.
The two digital data signals after the FT operation are sent to the C of the FFT multiplexer 64 via the data lines B3 and B4, respectively.
It is input to the input terminal and the B input terminal. Here, since the FFT multiplexer 64 selects the C input terminal from the intermediate timing of the state 28 to the intermediate timing of the state 29, after the first FFT operation output to the data line B3, as shown in FIG. The data digital signal of
It is input to the C input terminal of the input multiplexer 34 via the FFT multiplexer 64 and the FFT output register 65 for the next second FFT operation.

Next, in state 29 of FIG.
The input multiplexer 34 is switched to the C input terminal, while the data multiplexer 35 is switched to the B input terminal. At this time, the data Y is input from the FFT multiplexer 64 to the A input terminal of the multiplexer and accumulator 36 via the FFT output register 65 and the C input terminal of the input multiplexer 34, while F
The multiplication coefficient W read from the FT weight ROM 33
The data digital signal of y is input to the B input terminal of the multiplexer and accumulator 36 via the B input terminal of the data multiplexer 35. Then, the multiplexer and accumulator 36 multiplies the two input digital signals and outputs the result to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. As a result, the data digital signal of the multiplication result is input to the multiplexer and the accumulator in the accumulator 36, and immediately before this, the accumulator is reset, so that 0 is added to the data digital signal of the multiplication result and Store in the accumulator. The calculation of FFT9 in the state 29 is I ′ (0) × 1 in the first calculation example.

Next, in the state 30, similarly to the state 29, the input multiplexer 34 is switched to the C input terminal, and the data multiplexer 35.
Is switched to the B input terminal. At this time, the data Y is input from the FFT multiplexer 64 through the FFT output register 65 and the C input terminal of the input multiplexer 34 to the A input terminal of the multiplexer and accumulator 36, while being read from the FFT weight ROM 33. The data digital signal having the multiplication coefficient Wy is input to the B input terminal of the multiplexer and accumulator 36 via the B input terminal of the data multiplexer 35.
Then, the multiplexer and accumulator 36 multiplies the two input digital signals and outputs the result to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. As a result, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. At this time, the data digital signal of the input multiplication result is
It is added to the data digital signal of the multiplication result multiplied in the state 29 and stored in the accumulator.
The calculation of the FFT 10 in the state 30 is I ′ (4) × 1 + I ′ (0) in the first calculation example.

In the same manner, the processing for the second FFT operation is executed in states 31 and 32. here,
In the first calculation example, the calculation of the FFT 11 in the state 31 is I ′ (8) × 1 + I ′ (4) + I ′ (0), and the calculation of the FFT 12 in the state 32 is
In the first calculation example, I '(12) + I' (8) + I '
(4) + I ′ (0) is calculated, and the calculation result of the state 32 is the result data D2 in Tables 1 to 4.

Then, as shown in FIG.
Since the input latch trigger signal to the register 54a rises at the timing of the end of, the data digital signal of the result data D2, which is the result of the second FFT operation, is transferred from the multiplexer and accumulator 36 to the register 37.
Is input to the space data register 54a via the and is temporarily stored. In addition, at the intermediate timing of the state 32 before this operation, as shown in FIG.
Since the output enable signal to a and 53b rises,
The first F stored in the registers 53a and 53b, respectively.
The two digital data signals after the FT operation are sent to the C of the FFT multiplexer 64 via the data lines B3 and B4, respectively.
It is input to the input terminal and the D input terminal. Here, since the FFT multiplexer 64 selects the D input terminal from the intermediate timing of the state 32 to the intermediate timing of the state 33, after the first FFT operation output to the data line B4, as shown in FIG. The data digital signal of
FFT multiplexer 64 and FFT output register 65
Is input to the C input terminal of the input multiplexer 34 via.

Further, in the state 33, the input multiplexer 34 is switched to the C input terminal,
The data multiplexer 35 is switched to the B input terminal. At this time, the data Y is, as described above, the FFT.
While being input from the multiplexer 64 to the A input terminal of the multiplexer and accumulator 36 via the FFT output register 65 and the C input terminal of the input multiplexer 34, the data digital signal of the multiplication coefficient Wy read from the FFT weight ROM 33 is the data. It is input to the B input terminal of the multiplexer and accumulator 36 via the B input terminal of the multiplexer 35. Then, the multiplexer and accumulator 36 multiplies the two input digital signals and, via the register 37, the accumulator / accumulator of the multiplexer and accumulator 36.
Output to the IN terminal. As a result, the data digital signal of the multiplication result is input to the multiplexer and the accumulator in the accumulator 36, and immediately before this, the accumulator is reset, so that 0 is added to the data digital signal of the multiplication result and Store in the accumulator. FF in the state 33
The calculation of T13 is Q ′ (0) × 1 in the first calculation example.

Next, in the state 34, as in the case of the state 33, the input multiplexer 34 is switched to the C input terminal and the data multiplexer 35.
Is switched to the B input terminal. At this time, the data Y is input from the FFT multiplexer 64 through the FFT output register 65 and the C input terminal of the input multiplexer 34 to the A input terminal of the multiplexer and accumulator 36, while being read from the FFT weight ROM 33. The data digital signal having the multiplication coefficient Wy is input to the B input terminal of the multiplexer and accumulator 36 via the B input terminal of the data multiplexer 35.
Then, the multiplexer and accumulator 36 multiplies the two input digital signals and outputs the result to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. As a result, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. At this time, the data digital signal of the input multiplication result is
It is added to the data digital signal of the multiplication result multiplied in the state 33 and stored in the accumulator.
In the first calculation example, the calculation of the FFT 14 in the state 34 is Q ′ (4) × 1 + Q ′ (0).

Similarly, the processing for the second FFT operation is executed in states 35 and 36. here,
The calculation of the FFT 15 in the state 35 is Q ′ (8) × 1 + Q ′ (4) + Q ′ (0) in the first calculation example, and the calculation of the FFT 16 in the state 36 is
In the first calculation example, Q ′ (12) × 1 + Q ′ (8) +
It is a calculation of Q ′ (4) + Q ′ (0) = Q ″ (0), and the calculation result of the state 36 is the result data D2 in Tables 1 to 4.

Then, as shown in FIG.
Since the input latch trigger signal to the register 54b rises at the timing of the end of, the data digital signal of the result data D2, which is the result of the second FFT operation, is transferred from the multiplexer and accumulator 36 to the register 37.
Is input to the spatial data register 54b via the and is temporarily stored. In addition, at the intermediate timing of the state 367 before this operation, as shown in FIG.
Since the output enable signal to a rises, the data digital signal of the spatial data after the second FFT operation stored in the register 54a is output to the distributor 56a and the spatial data output for the processing of the next square sum circuit 15. It is input to the D input terminal of the input multiplexer 34 and the C input terminal of the data multiplexer 35 via the register 63.

Then, in the state 37 of FIG. 9, the process of squaring the spatial data stored in the register 54a is executed, in the state 38, the process of squaring the spatial data stored in the register 54b is executed, and in the state 39. In, the process of calculating the power data proportional to the amount of power (hereinafter referred to as power data) by adding the two data squared above is executed.

That is, as shown in FIG. 9, state 3
7, the input multiplexer 34 is switched to the D input terminal and the data multiplexer 35 is switched to the C input terminal. At this time, the data digital signal of the spatial data is input to the input multiplexer 34 via the distributor 56a and the spatial data output register 63.
, And the C input terminal of the data multiplexer 35, and the data digital signals of the same spatial data are input to both input terminals of the multiplexer and accumulator 36, so that the multiplexer and accumulator 36 have the same input data. The data digital signals of the two spatial data of are multiplied and output to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. As a result, the data digital signal of the multiplication result is input to the multiplexer and the accumulator in the accumulator 36. At this time, since the input data digital signal of the multiplication result is reset immediately before this operation, the multiplication is performed. The resulting data digital signal is added to 0 and stored in the accumulator. The calculation of the square of the spatial data in the state 37 is the calculation of the square of I ″ (0) in the first calculation example. Since the output enable signal to the register 54b rises at an intermediate timing of the state 37, the data digital signal of the spatial data after the second FFT operation stored in the register 54b is processed by the next square sum circuit 15. Therefore, it is input to the D input terminal of the input multiplexer 34 and the C input terminal of the data multiplexer 35 via the distributor 56b and the spatial data output register 63.

Then, as shown in FIG.
, The input multiplexer 34 is switched to the D input terminal and the data multiplexer 35 is switched to the C input terminal.
Can be switched to the input terminal. At this time, the data digital signal of the spatial data is input to the D input terminal of the input multiplexer 34 and the C input terminal of the data multiplexer 35 via the distributor 56a and the spatial data output register 63, and the same space Since the data digital signal of the data is input to both input terminals of the multiplexer and accumulator 36, the multiplexer and accumulator 36 multiplies the same two input data digital signals of the spatial data, and the multiplexer 37 via the register 37. And the accumulator of the accumulator 36
Output to the IN terminal. As a result, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. At this time, the input data digital signal of the multiplication result is in the state 37.
The data digital signal of the multiplication result is added to the squared data of the spatial data calculated in the above, and is output to the power data register 55 via the register 37. The calculation of the square of the spatial data in the state 38 is the calculation of the square of Q ″ (0) in the first calculation example. Then, since the input latch trigger rises at the timing of ending the state 38, the data digital signal of the operation result of the state 38 output from the register 37 is stored in the power data register 55. It should be noted that from the intermediate timing of the state 38 before this operation to the next state 3
Since the output enable signal of the register 55 rises by the middle timing of 9, the power data stored in the register 55, that is, the data digital signal of the calculation result of the square sum circuit 15 is output to the comparator circuit 6. In addition,
State 40 is provided for buffering the next operation cycle.

State 1 to state 40 described above
Up to the calculation of DSP5-1 up to other DSP5-2
5 to 16 execute the same processing as that of the states 1 to 40 shown in Tables 1 to 4. With this, the following 16 pieces of power data can be calculated. Of these 16 power data, the maximum data is selected by the comparator circuit 6 and input to the demodulator 7,
For example, PSK demodulation is performed using the two spatial data of I channel and Q channel output from the registers 54a and 54b in the DSP, and the demodulated data digital signal is output as a reception data signal.

As described above, each DSP simultaneously executes the processing including the quasi-quadrature detection, the transversal FIR low-pass filtering, and the FFT operation to the spatial domain, so that it can be executed at extremely high speed. . In addition, since the DSP executes processing including quasi-quadrature detection, transversal FIR low-pass filtering, and FFT calculation in the spatial domain, analog multi-beam forming such as Butler matrix in a phased array antenna is used. Compared to the signal processing of the array antenna, the device of this embodiment has an advantage that it is possible to realize multibeams in close proximity with a higher signal-to-noise ratio.

As described above, in this embodiment, as a method for efficiently executing the arithmetic processing including multi-beam formation, two-dimensional two axes of the physical arrangement of the antenna elements of the array antenna, that is, X In order to efficiently transmit and receive the data calculated by each DSP in the axial direction and the Y-axis direction, the
One data bus 101 to 104 and four data buses 105 to 108 in the Y-axis direction are used. In the above FFT operation processing, it is necessary to combine the received signals received by the individual antenna elements and to convert the spatial information, so the received data calculated by each DSP is
It is necessary to send and receive between SPs and exchange them. Since the calculation result transmitted / received via the data buses 101 to 104 after being calculated by another DSP is used, the FFT operation can be efficiently executed. As a result, the DSP usage efficiency in each operation cycle can be increased. That is, by using the dedicated data buses 101 to 116 for FFT operation between the DSPs to transmit and receive the data necessary for the operation, the operation rate of each DSP can be maximized. In other words, the multi-digital signal processor is configured so that the received signal processing can be distributed to all the DSPs.

As described above, the DSPs 5-1 to 5-5
As shown in FIG. 3, the ASIC arithmetic circuits, which are −16, are connected using grid-shaped buses 101 to 116 to perform arithmetic processing such as predetermined multi-beam synthesis on each ASI.
All ASICs are executed because they are distributed and executed in the C arithmetic circuit.
It is possible to increase the time for which the arithmetic circuits simultaneously perform arithmetic operations and increase the operating rate of the ASIC arithmetic circuits. As a result, it is possible to provide a signal processing device for an array antenna that can execute arithmetic processing for multi-beam formation at a higher speed than in the conventional example and that has a simple circuit configuration.

Further, D of the received signal processing apparatus of this embodiment is
For example, a CMA adaptive algorithm capable of removing an interference wave using a plurality of beams may be added to the processing in the SP. Also, in the DSP, for example, QPS
A K demodulation circuit may be added.

Since the received signal processing device of this embodiment does not depend on the carrier frequency, the same received signal processing device can be used for both L band and S band. That is, even if the carrier frequency is changed, if the communication data rate is the same, the calculation algorithm of the digital signal processing device is not affected.

The same circuit can be used by adapting the frequency for operating the DSP to an arbitrary data rate. This is because the operating frequency of the digital reception signal processing device is determined with respect to the actual data rate, and if the digital reception signal processing device can operate even at a high frequency, the circuit is It can be dealt with by changing only the operating frequency without changing it.

In the above embodiments, the received signal processing device for processing a plurality of high frequency received signals received by an array antenna composed of a plurality of antenna elements arranged in a two-dimensional matrix shape has been described. But,
The present invention is not limited to this, and is applied to a reception signal processing device for processing a plurality of high-frequency reception signals received by an array antenna composed of a plurality of antenna elements arranged in a one-dimensional linear shape. be able to. In this case, each D
There is only one data bus connecting SP.

[0098]

As described above in detail, according to the present invention, 1
Quasi-orthogonal detection processing, low-frequency filtering for a plurality of received signals received by an array antenna composed of a plurality of predetermined antenna elements (1) juxtaposed in close proximity in a two-dimensional or two-dimensional predetermined arrangement shape A received signal processing device for an array antenna, which performs received signal processing including multi-beam combining processing by Fourier transform and Fourier transform, comprising: a plurality of antenna elements (1) that perform the received signal processing. An arithmetic circuit is provided, and the plural arithmetic circuits (5) are provided with one-dimensional one data bus or two-dimensional lattice-shaped plural data according to the arrangement shape of the plural antenna elements (1). The plurality of arithmetic circuits (5) are connected to each other via the buses (101-116), and each of the plurality of arithmetic circuits (5) simultaneously performs a plurality of processes divided so as to execute the received signal processing. -116) through the run by transmitting and receiving data necessary for the signal processing. Therefore, it is possible to provide a signal processing device for an array antenna which can execute arithmetic processing for multi-beam formation at a higher speed than in the conventional example and which has a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of a received signal processing device for an array antenna that is an embodiment according to the present invention.

FIG. 2 is a block diagram showing functions of each DSP shown in FIG.

3 is a block diagram showing connections between the 16 DSPs of FIG. 1. FIG.

4 is a block diagram showing a circuit of each DSP shown in FIG. 1. FIG.

5 is a first timing chart showing the operation of each DSP of FIG. 1. FIG.

6 is a second timing chart showing the operation of each DSP of FIG. 1. FIG.

FIG. 7 is a third timing chart showing the operation of each DSP in FIG.

8 is a fourth timing chart showing the operation of each DSP of FIG. 1. FIG.

9 is a fifth timing chart showing the operation of each DSP of FIG. 1. FIG.

[Explanation of symbols]

 1-1 to 1-16 ... Antenna element, 2-1 to 2-16 ... Down converter, 3-1 to 3-16 ... Band pass filter, 4-1 to 4-16 ... A / D converter, 5- 1 to 5-16 ... DSP, 6 ... Comparator circuit, 7 ... Demodulator, 11 ... Synchronous distributor, 12, 22 ... Multiplier, 13, 23 ... FIR low-pass filter, 14, 24 ... Fast Fourier transformer , 15 ... Sum of squares circuit 20 ... Local oscillator, 21 ... π / 2 phase shifter, 31 ... Input register, 32 ... Beam ROM for beam forming, 33 ... Weight ROM for FFT, 34 ... Input multiplexer, 35 ... Data multiplexer, 36 ... Multiplexer and accumulator, 37 ... Register, 51a, 51b ... Post-detection register, 52a, 52b ... FIR register, 53a, 53b ... FFT primary register 54a, 54b ... Spatial data register, 55 ... Power data register, 56a, 56b ... Distributor, 61a, 61b ... FIFO memory, 62 ... FIR output register, 63 ... Spatial data output register, 64 ... FFT multiplexer, 65 ... FFT output Registers, 101 to 108 ... Data buses, B1 to B4 ... Data lines.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Isamu Chiba 5 Seipaya, Seika-cho, Soraku-gun, Kyoto Prefecture, Mihiratani, ATR Optical & Radio Communications Research Institute, Inc. (72) Ryu Miura, Soraku-gun, Kyoto Prefecture 5 Seiraya-cho, Indani-ya-letter, Mihiratani, Inc. Optical Communications Research Institute, Inc. (72) Inventor, Yoshio Karasawa, 5 Seiji-cho, Seika-cho, Soraku-gun, Kyoto Pref. Radio Communications Laboratory

Claims (5)

[Claims] 1. A quasi-orthogonal detection for a plurality of received signals received by an array antenna comprising a plurality of predetermined antenna elements (1) juxtaposed in close proximity in a one-dimensional or two-dimensional predetermined arrangement shape. A received signal processing device for an array antenna, which performs received signal processing including processing, low-frequency filtering processing, and multi-beam combining processing by Fourier transform, the number of antenna elements (1) performing the received signal processing. And a plurality of arithmetic circuits (5) according to the arrangement shape of the plurality of antenna elements (1). Multiple data buses (101
-116), each of the plurality of arithmetic circuits (5) simultaneously performs a plurality of processes divided so as to execute the received signal processing, simultaneously with the data bus (1).
01-116) to perform the above-mentioned signal processing by transmitting and receiving data necessary for the signal processing. 2. The plurality of arithmetic circuits (5) convert data necessary for executing the received signal processing into multi-phase data by the quasi-quadrature detection processing, the low-frequency filtering processing, and the Fourier transform. Two multiplexers (34, 3) for selectively switching and outputting according to beam combining processing
5) and a multiplexer (3 that executes multiplication of two data output from the two multiplexers (34, 35)).
6), an accumulator (36) that cumulatively adds and outputs a plurality of data of multiplication results executed by the multiplexer (36), and the quasi-quadrature detection processed data output from the accumulator (36) , A plurality of registers (51a, 51) for storing the data after the low-frequency filtering process and the data after the multi-beam combining process by the Fourier transform.
b, 52a, 52b, 55), and the data output from the accumulator (36) by a predetermined process in the low-frequency filtering process and the multi-beam combining process by the Fourier transform is the accumulator (36). The data after the quasi-orthogonal detection processing, the data after the low frequency filtering processing, and the data after the multi-beam combining processing by the Fourier transform are stored in the plurality of registers. The received signal processing device for an array antenna according to claim 1, wherein the received signal processing device outputs the received signal. 3. The multi-beam processing based on the Fourier transform is performed by the plurality of arithmetic circuits (5) transmitting and receiving data necessary for the signal processing via the data buses (101-116), respectively. The received signal processing device for an array antenna according to claim 1 or 2, which is a synthesizing process. 4. The plurality of arithmetic circuits (5) respectively include the registers (52a, 52b) and the data bus (1).
01-116), and further includes another multiplexer (64) which selectively switches data necessary for the multi-beam synthesis processing by the Fourier transform and outputs the data to the one multiplexer (34). The received signal processing device for an array antenna according to claim 1. 5. The low-pass filtering process is a transversal type finite impulse response type low-pass filtering process, wherein each of the plurality of arithmetic circuits (5) performs the quasi-quadrature detection process. Register (51a, 5a
5. The received signal processing device for an array antenna according to claim 1, further comprising a FIFO memory (61a, 61b) for storing the data output from 1b).