JPH07221283A - Semiconductor device - Google Patents

Abstract

PURPOSE:To shorten the turn-off time of a semiconductor device in which a MOS transistor is utilized for a turn-off operation and to increase a maximum controllable current. CONSTITUTION:A p<-> channel region 3 and a p<+> gate region 4 are formed on the surface part of an n<-> semiconductor region 2 on a p<+> anode region 1, an n<+> cathode region 5 is formed on the surface part inside the p<-> channel region 3. A p<+> cathode short region 6 is formed by keeping a prescribed interval from the p<+> gate region 4. A p<+> source region 21 which is overlapped with the end part of the p<+> gate region 4 and which is shallower than the region 4 is formed in a position in which the p<+> gate region 4 on the surface part of the n<-> semiconductor region 2 faces the p<+> cathode short region 6. A p<+> drain region 22 overlapped with the end part of the p<+> cathode short region 6 and shallower than the region 6 is formed. A silicon oxide film 7 is formed at the upper part, and in its neighborhood, of the n<-> semiconductor region 2 between the p<+> gate region 4 and the p<+> cathode short region 6, and a gate electrode 23 is formed on the surface of the film 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is applicable to turn-off operation.
The present invention relates to a semiconductor device using an S transistor.

[0002]

2. Description of the Related Art A semiconductor device is required to have various characteristics depending on its application. For example, for transistors and thyristors used as switching elements, the switching speed such as turn-on time and turn-off time is important, and for power elements such as thyristors that control large currents, control is possible along with on-resistance. Current becomes important.

FIG. 6 is a sectional view showing the structure of a MOS control thyristor provided with a MOS transistor used for a turn-off operation in order to shorten the turn-off time.
In the figure, an n ⁻ semiconductor region 2 is formed on the upper surface of the p ⁺ anode region 1. A p ⁻ channel region 3 is selectively formed on the surface of the n ⁻ semiconductor region 2, and ap ⁺ gate region 4 is formed so as to surround the p ⁻ channel region 3. In addition, on the surface of the p ⁻ channel region 3,
An n ⁺ cathode region 5 is selectively formed. Further, ap ⁺ cathode short region 6 is formed on the surface of the n ⁻ semiconductor region 2 at a position spaced apart from the p ⁺ gate region 4 by a predetermined distance.

On the surface of the n ^- semiconductor region 2 in which the above region is formed, the silicon oxide film 7 is uniformly formed except for a part of each surface of the n ⁺ cathode region 5 and the p ⁺ cathode short region 6. Has been formed. A cathode electrode 8 is formed so as to be connected to the surface of the n ⁺ cathode region 5, and a cathode shorting electrode 9 is formed so as to be connected to the surface of the p ⁺ cathode short region 6. These two
The two electrodes 8 and 9 are electrically connected. Also,
On the surface of the silicon oxide film 7, the n ⁻ semiconductor region 2 between the p ⁺ gate region 4 and the p ⁺ cathode short region 6 is formed.
Of the gate electrode 10 is formed on the upper part and in the vicinity thereof. The gate electrode 10 extends to a position on the surface of the silicon oxide film 7 so as to overlap the upper portions of the p ⁺ gate region 4 and the p ⁺ cathode short region 6. Further, the anode electrode 11 is uniformly formed on the lower surface of the p ⁺ anode region 1.

Next, the operation of the MOS control thyristor having the above structure will be described. At the time of turn-on, when a positive voltage is applied to the gate electrode 10, the carriers in the p ⁺ gate region 4 and the p ⁻ channel region 3 become a displacement current and reach the vicinity of the n ⁺ cathode region 5. As a result, electrons are injected from the n ⁺ cathode region 5 into the p ⁻ channel region 3, and the electrons reach the vicinity of the p ⁺ anode region 1. Then, p ⁺ electrons that reach near the anode region 1 and the p ⁺ anode region 1 n ^- as it reduces the energy barrier between the semiconductor region 2, a p ⁺ anode region 1 n ^- holes to the semiconductor region 2 As a result, the holes reach the n ⁺ cathode region 5 and the thyristor enters the latch-up state.

At the time of turn-off, the p ⁺ gate region 4 and the p ⁺ cathode short region 6 are used as the source region and the drain region, respectively, and the surface of the n ⁻ semiconductor region 2 between the p ⁺ gate region 4 and the p ⁺ cathode short region 6 is turned on. A p-channel MOS transistor (hereinafter referred to as pMOS) in which the vicinity is the channel region and the gate electrode 10 is the gate electrode is used. That is, by applying a negative voltage to the gate electrode 10, the pMOS is turned on, and p ⁻
Excess carriers in the channel region 3 and the p ⁺ gate region 4 or the n ⁻ semiconductor region 2 are caused to flow to the cathode terminal via the pMOS to turn off the thyristor.
In this way, the turn-off time is shortened by extracting excess carriers using the pMOS.

[0007]

By the way, the turn-off time of the MOS control thyristor having the above-mentioned structure is determined by the above pMO.
The larger the current, the shorter the turn-off time, depending on the magnitude of the current drawn through S. Also, the larger the current, the larger the maximum controllable current. Here, the maximum controllable current is a turn-off characteristic that represents the ability to turn off the thyristor in the ON state, and indicates how large a latch-up current can be cut off. Therefore, if the resistance value of the pMOS is reduced, the extraction current is increased, and the turn-off time is shortened.
The maximum controllable current also increases. However, in the conventional MOS control thyristor shown in FIG. 6, the resistance value of the pMOS cannot be made sufficiently small for the reasons described below.

FIG. 7 is a diagram showing the structure of the pMOS of the MOS control thyristor shown in FIG. 6 and the main parts in the vicinity thereof, and explaining the surface impurity concentration of those regions. In FIG. 7, the resistance value of the pMOS channel region is the distance d between the p ⁺ gate region 4 and the p ⁺ cathode short-circuit region 6.
(PMOS channel length). However, p ⁺
The gate region 4 and the p ⁺ cathode short region 6 are n
^- so formed deep by diffusing the p-type impurity from the surface of the semiconductor region 2, the distance d is variation occurs with respect to the design value. The reason for this is that, when a semiconductor region is formed by diffusing impurities, the spread of the region follows a Gaussian distribution, and therefore the spread of the p ⁺ gate region 4 and the p ⁺ cathode short region 6 necessarily has variations. is there. Further, in such a region formation by impurity diffusion, the spread in the vertical direction (depth) and the spread in the horizontal direction have a constant ratio, so that the p ⁺ gate region 4 and the p ⁺ cathode short region 6 are formed. If a deep region is formed, the variation due to the Gaussian distribution also increases in the lateral direction, and the variation in the distance d also increases. If p ⁺ gate region 4 is formed shallower than a predetermined depth, it becomes difficult to secure the breakdown voltage.

Therefore, in order to prevent the p ⁺ gate region 4 and the p ⁺ cathode short-circuit region 6 from coming into contact with each other, the distance d between them must be designed to be large with a margin. As a result, the resistance value of the channel region of the pMOS becomes large, and the turn-off time of the thyristor cannot be shortened sufficiently.

Another reason why the resistance value of the pMOS cannot be made sufficiently small is the problem of the surface impurity concentration of the p ⁺ gate region 4 and the p ⁺ cathode short region 6. The current drawn at turn-off is p, as shown in FIG.
^The cathode short-circuiting electrode 9 is reached by passing through the end portion near the surface of the ⁺ gate region 4, the channel region of the pMOS, and the vicinity of the surface of the p ⁺ cathode short-circuit region 6. However, the surface impurity concentration is low at the end (4a) of the p ⁺ gate region 4 and the end (6a) of the p ⁺ cathode short region 6. The reason for this is that as the distance from the diffusion window position where the p-type impurity is introduced to form these regions increases, the concentration decreases according to the Gaussian distribution. Therefore, the resistance values of the regions 4a and 6a are large and pM
The resistance value of the entire OS also increases.

As a result, the turn-off time of the thyristor could not be shortened sufficiently and the maximum controllable current could not be increased sufficiently. The present invention solves the above problem, and an object of the present invention is to speed up the turn-off operation of a semiconductor device using a MOS transistor for the turn-off operation and increase the maximum controllable current.

[0012]

The semiconductor device of the present invention comprises:
A second conductivity type second semiconductor region is formed on the surface of the first conductivity type first semiconductor region, and a first conductivity type third semiconductor region is formed on the surface of the second semiconductor region. A second conductive type fourth semiconductor region is formed on the surface of the first semiconductor region at a predetermined distance from the second semiconductor region, and the third semiconductor region and the fourth semiconductor region are formed. It is assumed that the semiconductor region is electrically connected.

When this semiconductor device is applied to a thyristor, for example, a second conductivity type anode region is provided on the lower surface of the first semiconductor region. Further, the second semiconductor region corresponds to the gate region (or base region), and the third semiconductor region corresponds to the cathode region.

According to a first aspect of the present invention, there is provided the semiconductor device according to the first aspect.
At a position where the second semiconductor region and the fourth semiconductor region are opposed to each other on the surface portion of the semiconductor region, the second conductivity type is connected to the second semiconductor region and is shallower than the second semiconductor region. A fifth semiconductor region is formed, and is connected to the fourth semiconductor region to form a sixth semiconductor region of the second conductivity type that is shallower than the fourth semiconductor region. An insulating film is formed on the surface of the semiconductor region and the first semiconductor region between the semiconductor regions, and an electrode is further formed on the insulating film.

A semiconductor device according to a second aspect is the semiconductor device according to the first aspect.
On the premise that the fifth and sixth semiconductor regions are the source region and the drain region, respectively, and the surface portion of the first semiconductor region between the fifth and sixth semiconductor regions is the channel region, and the respective regions are formed. The distance between the fifth semiconductor region and the sixth semiconductor region is minimized within the range of satisfying the condition of enhancing the MOS transistor constituted by the insulating film and the electrode on the insulating film. To do.

A semiconductor device according to a third aspect is the semiconductor device according to the first aspect.
Based on the above, the fifth and sixth semiconductor regions are formed with a high impurity concentration. A semiconductor device according to a fourth aspect is based on the first aspect, and the fifth semiconductor region is formed in the second region.
At the surface portion in the semiconductor region, the diffusion window position at the time of forming the second semiconductor region or the vicinity thereof is formed.

A semiconductor device according to a fifth aspect is the semiconductor device according to the first aspect.
Based on the above, the sixth semiconductor region is formed in the surface portion of the fourth semiconductor region up to or near the diffusion window position when the fourth semiconductor region is formed.

A semiconductor device according to a sixth aspect is the semiconductor device according to the first aspect.
Based on the above, the sixth semiconductor region is formed up to a position overlapping with an electrode connected to the fourth semiconductor region on the surface portion in the fourth semiconductor region.

[0019]

In the semiconductor device of the present invention, since the fifth and sixth semiconductor regions are formed shallowly, variations in the spread of these regions are reduced. Therefore, the distance between the fifth semiconductor region and the sixth semiconductor region can be formed almost according to the designed value, and the distance can be set to a sufficiently small desired value. Therefore, the channel of the MOS transistor having the second and fifth semiconductor regions as source regions, the fourth and sixth semiconductor regions as drain regions, and the surface portion of the first semiconductor region between these regions as a channel region. The length can be shortened, and the current drawn through this MOS transistor becomes large. As a result, the turn-off time is shortened and the maximum controllable current is increased (claims 1 and 2).

A fifth semiconductor region having a high impurity concentration is formed into a second semiconductor region.
When the semiconductor window is formed up to or near the diffusion window position when forming the semiconductor region, the resistance of the source region of the MOS transistor becomes small (claims 3 and 4). Further, if the sixth semiconductor region having a high impurity concentration is formed up to or near the position of the diffusion window when forming the fourth semiconductor region, or at a position overlapping the electrode connected to the fourth semiconductor region, The resistance of the drain region of the MOS transistor is reduced (claims 3, 5, and 6). Therefore, since the current drawn at the time of turn-off becomes large, the turn-off time becomes short and the maximum controllable current becomes large.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an embodiment of the present invention and is a cross-sectional view of a thyristor using a MOS transistor for a turn-off operation. In FIG. 1, the same reference numerals as those given in FIG. 6 showing the structure of the conventional thyristor indicate the same region or portion.

An n ⁻ semiconductor region 2 (corresponding to the first semiconductor region in the claims) is formed on the upper surface of the p ⁺ anode region 1, and the p ⁻ channel region is formed on the surface of the n ⁻ semiconductor region 2. 3 and ap ⁺ gate region 4 (regions 3 and 4 correspond to the second semiconductor region in the claims) are formed. An n ⁺ cathode region 5 (corresponding to the third semiconductor region in the claims) is formed on the surface of the p ⁻ channel region 3, and the p ⁻ of the surface of the n ⁻ semiconductor region 2 is formed.
^A p ⁺ cathode short region 6 (corresponding to the fourth semiconductor region in the claims) is formed at a position spaced apart from the ⁺ gate region 4 by a predetermined distance.

The p ⁺ gate region 4 and the p ⁺ cathode short region 6 are formed relatively deep at the same time, for example, 4
It is formed to a depth of about μm. Further, the regions 4 and 6 are formed so that a p-type impurity such as boron is contained at a high concentration, and the surface impurity concentration thereof is, for example, about 5 × 10 ¹⁸ . Further, the distance between the p ⁺ gate regions 4 and 4 and the impurity concentration of the p ⁻ channel region 3 are formed to values such that the characteristics of this thyristor show the characteristics of the static induction thyristor.

At the position where the p ⁺ gate region 4 and the p ⁺ cathode short region 6 on the surface of the n ⁻ semiconductor region 2 are opposed to each other, the p ⁺ source region 21 is overlapped with the end of the p ⁺ gate region 4 (claim 9). Corresponding to the fifth semiconductor region of
There are formed, also (corresponding to the sixth semiconductor region of claim) p ⁺ drain region 22 while overlapping the end portion of the p ⁺ cathode short regions 6 are formed.

The p ⁺ source region 21 and the p ⁺ drain region 22 are shallowly formed in the same step, for example, to a depth of 2 μm or less, for example, a depth of about 1.5 μm. The formation of these regions 21 and 22 can also be performed by simultaneous diffusion with the n ⁺ cathode region 5. Further, these regions 21 and 22 are also regions of high impurity concentration, and the surface impurity concentration thereof is formed to about 1 × 10 ¹⁹ , for example. Note that p
^{The +} source region 21 and the p ⁺ drain region 22 are connected to the p ⁺ gate region 4 and the p ⁺ cathode short region 6 respectively.
The degree of overlap between them and the distance between the regions 21 and 22 will be described later in detail.

N ^- semiconductor region 2 in which the above regions are formed
A silicon oxide film 7 (corresponding to the insulating film in the claims) is formed on the surface of the same as in FIG. Further, a cathode electrode 8 and a cathode short-circuiting electrode 9 made of, for example, aluminum are provided respectively connected to the n ⁺ cathode region 5 and the p ⁺ cathode shorting region 6,
The electrodes are electrically connected to each other. Further, an anode electrode 11 made of, for example, aluminum is provided on the lower surface of the p ⁺ anode region 1.

On the surface of the silicon oxide film 7, a gate electrode 23 made of, for example, polysilicon is formed on the n ⁻ semiconductor region 2 between the p ⁺ source region 21 and the p ⁺ drain region 22 and in the vicinity thereof. (Corresponding to the electrode on the insulating film in the claims) is formed. The gate electrode 23 extends to a position on the surface of the silicon oxide film 7 so as to overlap the upper parts of the p ⁺ source region 21 and the p ⁺ drain region 22. In this way, p ⁺
Source region 21, p ⁺ drain region 22, those regions 2
Between the n ^- semiconductor region 2 and the n ^- semiconductor region 2 between p.
Channel MOS transistor (hereinafter referred to as pMOS)
Is configured.

Next, FIG. 2 shows the structure of the pMOS and its peripheral main parts. In the figure, the pMOS channel length D (distance between the p ⁺ source region 21 and the p ⁺ drain region 22) is designed to be as small as possible in order to reduce its resistance. However, this pMOS needs to be an enhancement type because it is a switch that becomes conductive only when the thyristor is turned off. Further, in consideration of manufacturing accuracy when forming a semiconductor region by diffusion, the channel length D is It is desirable to form it with a thickness of about 1 μm.

Since the p ⁺ source region 21 and the p ⁺ drain region 22 are formed shallow as described above, there is little variation in the spread of the regions. Therefore, the channel length D is formed within a very small error range with respect to the design value. As a result, in order to absorb the variation error of the channel length D, it is not necessary to give a large margin to the value and to design a large value, and the channel length of the pMOS can be stably reduced.

The p ⁺ source region 21 is the p ⁺ gate region 4
Is formed so as to extend to the end of the window (diffusion window) position provided for introducing the p-type impurity when the p ⁺ gate region 4 is formed. On the other hand, the p ⁺ drain region 22 is formed so as to overlap the end portion of the p ⁺ cathode short region 6 in the vicinity of the surface and extend to the lower portion of the cathode short electrode 9. That is, a part of the p ⁺ drain region 22 contacts the cathode shorting electrode 9.

In such formation, the position of the impurity introduction window (diffusion window) for forming the p ⁺ source region 21 and the p ⁺ drain region 22, the amount of the impurity introduced, the diffusion conditions such as temperature and time are set. It is realized by setting appropriately.

The lower part of FIG. 2 is a diagram for explaining the surface impurity concentration of the pMOS formed as described above. In the pMOS of the thyristor of this embodiment, the impurities of the p ⁺ source region 21 and the p ⁺ drain region 22 are added at the ends of the p ⁺ gate region 4 and the p ⁺ cathode short region 6, respectively. Is high. Since the p ⁺ source region 21 and the p ⁺ drain region 22 are regions formed by shallow diffusion, the n ⁻ semiconductor region 2 is formed at each end (the side where the two regions 21 and 22 face each other). It is formed with a high impurity concentration maintained near the boundary with.

Next, the operation of the thyristor having the above structure will be described. Since the turn-on operation is the same as that of the conventional thyristor described with reference to FIG. 6, the description thereof will be omitted. Here, the turn-off operation will be described with reference to FIGS. 1 and 2.

At turn-off, the pMOS is turned on by applying a negative voltage of a predetermined value or more to the gate electrode 23. That is, by applying the negative voltage, the p ⁺ source region 21 and the p ⁺ drain region 2 are
The n ^- semiconductor region 2 in the vicinity of the surface thereof is inverted from n-type to p-type to form a p-channel, and carriers move between the p ⁺ source region 21 and the p ⁺ drain region 22. To enable. This allows the p ⁺ gate region 4
And excess carriers existing in the p ^- channel region 3 or the n ^- semiconductor region 2 are drawn out to the cathode short-circuiting electrode 9, that is, the cathode terminal via the pMOS in the ON state, and the current flowing between the anode and the cathode of the thyristor is changed. Cut off.

When the excess carriers are extracted as described above, the carriers are the end of the p ⁺ gate region 4 near the surface, the p ⁺ source region 21, the pMOS channel, and the p ^+.
Drain region 22 and p ⁺ cathode short-circuit region 6
To reach the cathode short-circuiting electrode 9 via the surface vicinity region. However, as described above, since the channel length D of the pMOS channel can be formed to be sufficiently small almost as designed, its resistance value is small. Further, since the path through which the excess carriers pass is the area where the concentration of p-type impurities is high (excluding the channel area) as described above, the resistance value of the path is small. Therefore,
Since the excess carriers can reach the cathode terminal only through the path having a low resistance value, the extraction current at the time of turn-off increases and the turn-off operation is accelerated.
Moreover, the maximum controllable current can be increased.

It should be noted that the p ⁺ source region 21 and the p ⁺ drain region 22 are formed in various modes depending on the extent to which the p ⁺ gate region 4 and the p ⁺ cathode short region 6 are formed so as to overlap the end portions near the surfaces thereof. Can be considered. That, p ⁺ cathode short region 6 (or p ⁺ gate region 4) so that the surface impurity concentration of reaching a sufficiently high region p ⁺ drain region 22 (or p ⁺ source region 21)
Can be formed by stretching. For example, it is also effective to form the p ⁺ drain region 22 by extending it to the vicinity of the diffusion window position for the p ⁺ cathode short region 6. Also,
Since the distribution of the surface impurity concentration of the p ⁺ cathode short region 6 can be statistically calculated, the formation position of the p ⁺ drain region 22 may be determined based on the calculated value.
As an example, the surface impurity concentration of the p ⁺ cathode short region 6 is 1 of the surface impurity concentration at the diffusion window position in that region.
Use a position of about / 2 as a guide.

Further, the thyristor having the above-mentioned structure can be constructed by inverting the conductivity type of each semiconductor region of the thyristor as shown in FIG. The operation of the thyristor shown in FIG. 3 is basically the same as that described with reference to FIG. 1, but a negative voltage is applied to the gate electrode at turn-on and a positive voltage is applied at turn-off.

Further, although the electrostatic induction type thyristor has been described in the above embodiment, the present invention is not limited to this. For example, a BRT (Base) as shown in FIG. 4 is used.
Re-sistance controlled Thyristor). In the BRT, the p base region 4'is formed on the surface of the n ^- semiconductor region 2, and the p ⁺ cathode region 5 is selectively formed on the surface of the p base region 4 '. And
At the position where the p base region 4 ′ on the surface of the n ⁻ semiconductor region 2 and the p ⁺ cathode short region 6 face each other, the p ⁺ source region 21 overlaps with the end of the p base region 4 ′.
Is formed. The turn-on operation and turn-off operation of this BRT are the same as those of the thyristor shown in FIG.

Further, although the present invention is applied to the thyristor in the above embodiment, it may be applied to a transistor as shown in FIG. The structure of the main part of this transistor is basically the same as that of the thyristor shown in FIG. 1, but an n ⁺ drain (collector) region 31 is formed on the lower surface of the n ⁻ semiconductor region 2, and a p ⁻ channel region is formed. An n ⁺ source (emitter) region 32 is selectively formed on the surface portion of the inside 3.

[0040]

According to the present invention, since the source region and the drain region of the MOS transistor used for the turn-off operation are formed by shallow diffusion, the manufacturing accuracy of the formation position of these regions is improved and the channel length of the MOS transistor is improved. Variation is reduced. As a result, since the channel length of the MOS transistor can be formed to be sufficiently short as almost a designed value, the resistance value of the path for extracting excess carriers becomes small, which speeds up the turn-off operation, and
The maximum controllable current can be increased.

Further, since the impurity concentration of the source region and the drain region of the MOS transistor is increased, the resistance value of those regions is lowered. Therefore, also by this, similarly, the resistance value of the path for extracting the excess carriers is reduced, the turn-off operation is accelerated, and
The maximum controllable current can be increased.

[Brief description of drawings]

FIG. 1 is a sectional view of a thyristor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a MOS transistor portion of the thyristor shown in FIG. 1 and a main portion around the MOS transistor portion, and explaining a surface impurity concentration in the region.

3 is a sectional view of a thyristor in which the conductivity type of each semiconductor region of the thyristor shown in FIG. 1 is inverted.

FIG. 4 is a sectional view of an embodiment in which the present invention is applied to a BRT.

FIG. 5 is a sectional view of an embodiment in which the present invention is applied to a transistor.

FIG. 6 is a cross-sectional view of a conventional example of a thyristor using a MOS transistor for turn-off operation.

7 is a diagram showing a configuration of a MOS transistor portion of the thyristor shown in FIG. 6 and a main portion around the MOS transistor portion, and explaining a surface impurity concentration in the region.

[Explanation of symbols]

1 p ⁺ Anode region 2 n ^- Semiconductor region 3 p ^- Channel region 4 p ⁺ Gate region 5 n ⁺ Cathode region 6 p ⁺ Cathode short region 7 Silicon oxide film 8 Cathode electrode 9 Cathode short electrode 11 Anode electrode 21 p ⁺ Source Region 22 p ⁺ drain region 23 gate electrode

Claims (6)

[Claims] 1. A second semiconductor region of the second conductivity type is formed on the surface of the first semiconductor region of the first conductivity type, and a first semiconductor of the first conductivity type is formed on the surface of the second semiconductor region. Third semiconductor region is formed, and a second conductivity type fourth semiconductor region is formed on the surface of the first semiconductor region at a predetermined distance from the second semiconductor region, and the third semiconductor region is formed. And a fourth semiconductor region electrically connected to each other, wherein the second semiconductor region and the fourth semiconductor region are opposed to each other at a position on the surface of the first semiconductor region. A fifth semiconductor region of the second conductivity type that is connected to the second semiconductor region and is shallower than the second semiconductor region, and is connected to the fourth semiconductor region and is shallower than the fourth semiconductor region. A sixth semiconductor region of the second conductivity type is formed, and the fifth and sixth semiconductor regions are formed. And the first insulating film is formed on the surface of the semiconductor region, the semiconductor device characterized by forming a further electrode on top of the insulating film between them semiconductor region. 2. The fifth and sixth semiconductor regions serve as a source region and a drain region, respectively, and the surface portion of the first semiconductor region between the fifth and sixth semiconductor regions serves as a channel region, and each of them is formed. The distance between the fifth semiconductor region and the sixth semiconductor region is minimized within the range of satisfying the condition that the MOS transistor configured by the region and the insulating film and the electrode on the insulating film is of the enhancement type. The semiconductor device according to claim 1, wherein 3. The semiconductor device according to claim 1, wherein the fifth and sixth semiconductor regions are formed with a high impurity concentration. 4. The fifth semiconductor region is formed up to or near a diffusion window position when the second semiconductor region is formed in the surface portion of the second semiconductor region. Item 1. The semiconductor device according to item 1. 5. The sixth semiconductor region is formed up to or near a diffusion window position when the fourth semiconductor region is formed in a surface portion of the fourth semiconductor region. Item 1. The semiconductor device according to item 1. 6. The sixth semiconductor region is formed up to a position overlapping with an electrode connected to the fourth semiconductor region on a surface portion in the fourth semiconductor region. Semiconductor device.