JPH07219812A - Abnormality monitoring system - Google Patents

Abstract

PURPOSE:To discriminate an abnormal board without using an interrupting function and to attain the continuous operation of an abnormality monitoring system. CONSTITUTION:In a system where a system bus is connected with a main processor board 200, the function boards 210 and 220, and a monitor circuit part 230, a system abnormality signal line 2D is asserted by the abnormality information output parts 201, 211 and 221 of those boards with occurrence of the internal abnormality. At the same time, the abnormal device code of each board is outputted to a data bus 2B. Then an abnormality information input part 203 of the board 200 discriminates an abnormal function board by the abnormal device code. When the board 200 has an abnormal stop, an abnormality monitor circuit 251 of the part 230 and other boards collect the abnormal device codes and output the abnormality information to the outside to attain the continuous operation of a system taking over the board 200.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for constructing an information processing apparatus such as a microcomputer and a control apparatus using the same, and more particularly to a multi-processor (multi-processor) using a bus and a bus master for exchanging information. Master) configuration-related abnormality monitoring method at the system level.

[0002]

2. Description of the Related Art In an information processing device or control device using a microprocessor, generally, a plurality of functional elements are connected by a logical data channel called a bus, and data is exchanged between the elements. Control and processing by.

In order to realize this concretely, each functional element is housed in a printed wiring board (hereinafter referred to as a board) in which functions are integrated, and a plurality of boards are realized as a printed wiring board (hereinafter referred to as a backplane). The system is adopted by connecting to the system.

In such a system, a board having a right to use a single "bus" in one system (processor board, DMA board, etc., generally called a master), and a plurality of boards are provided. There is a single processor system in which a board (generally called a slave) that is subordinate to the bus of is implemented.

In addition, a multi-processor composed of a plurality of processor (master) boards and a plurality of slave boards.
There is a processor system (multi-master system).

The system as described above is connected by a logical data channel (a group of signals is regarded as one bundle) called a bus, but it is generally a general-purpose standard bus for microcomputers. As a multi-bus, V
ME buses and the like are known. Such a standard bus is widely used as an industrial control bus, and is a technology indispensable for constructing a control system at present.

In such a standard bus, as a means for monitoring an abnormality, a "system abnormality signal" is usually provided from one signal line.
(Hereinafter referred to as the SYSFAIL signal) is taken out. This signal is asserted when a board capable of monitoring its own abnormality detects an internal abnormality, and is intended for the system side to perform abnormality processing and notify the outside.

In many cases, there are a plurality of boards having anomaly monitoring capability on the bus which constitutes a multi-processor system. On the other hand, since this SYSFAIL signal is a single signal line, it is normally wired OR ( It is output after being ORed.

As described above, the SYSFAIL signal is provided to notify the system of an abnormality detection signal of a board in the system. In the current technology, (1) this is sent to the processor board that controls the system. To stop the operation of the system.

(2) This is notified to the module that monitors the system, and the person (operator) or another device is notified of the abnormality.

It is only used for the above purpose.

FIG. 5 shows the configuration of a conventional multi-processor system and the concept of abnormality monitoring. In the figure, 1
01 is a main processor board that controls the system, 102 is a sub processor board, 103 is an I / O board with an intelligent function inside, 104
Is a general slave I / O board, and 105 is an abnormality monitoring circuit for performing system abnormality monitoring.

Although the monitoring circuit 105 may be a dedicated board, it is a very small circuit, and therefore may be incorporated in a backplane forming a bus, a processor board, or the like.

Reference numeral 111 is a system bus for exchanging signals between the boards, and reference numeral 112 is a SYSFAIL signal which is one of the signal lines.

Each of the boards 101, 102 and 103 has a function of monitoring its own abnormality and outputting a SYSFAIL signal when an abnormality occurs. 104 is S when an abnormality occurs
It does not have the ability to output the YSFAIL signal.

Further, the main processor board 101
The abnormality monitoring circuit 105 has a capability of inputting a SYSFAIL signal to stop the control of the entire system and notifying an external operator or another device of the abnormality.

In the above configuration, the sub processor
If an abnormality occurs on the board 102, the board asserts the SYSFAIL signal 112. The main processor board 101 generates an internal interrupt or the like, detects this, and determines that there is an abnormality in the system, and stops the control of the system.

At the same time, the monitoring circuit 105 is a SYSFA.
Detecting that the IL signal is asserted and notifying the operator by means of notification such as LED display or buzzer,
The isolated DO (digital output) circuit or the like notifies another system or device as a signal.

[0019]

In the conventional abnormality monitoring system, when the abnormality detected by each board is notified via the SYSFAIL signal, the signal indicating that there is only one SYSFAIL signal line and wired OR is used. Therefore, it is not possible to know which board has an abnormality when this signal is asserted.

Therefore, the main
Regarding the processor board 101 and the monitoring board 105, it is not possible to limit the board in which an abnormality has occurred or stop the use of only that board to continue the operation of other parts of the system.

As one means for avoiding such an adverse effect, there is a method of notifying an abnormality detected by each board to the main processor board by using an interrupt, but (1) the interrupt circuit is complicated and each The amount of hardware that should be mounted on the board is large, and failures in this part are also possible.

(2) Processor that accepts interrupts
There is only one board in the system, and if it fails, it is almost impossible to detect anomalies.

The harmful effects such as the above are also left.

It is an object of the present invention to provide an abnormality monitoring system which enables a system to continue operating by discriminating a board in which an abnormality has occurred without using an interrupt function.

Another object of the present invention is to provide an abnormality monitoring system capable of discriminating a board in which an abnormality has occurred even when the main processor board has stopped functioning.

Further, another object of the present invention is to provide an abnormality monitoring system in which the processor board other than the main processor board is used to discriminate the board in which the abnormality has occurred so that the operation of the system can be continued. It is in.

[0027]

According to the present invention, in order to solve the above-mentioned problems, a plurality of function boards are coupled by a system bus, and each function board is connected to one system of the system bus for internal abnormality detection. An abnormality information output unit for asserting an abnormality signal line is provided, and the abnormality monitoring means provided on the main processor board of the function boards and the abnormality monitoring means provided on a dedicated board are abnormal due to the assertion of the system abnormality signal line. In a multi-processor system for monitoring, each of the function boards has an abnormal device code that becomes an exclusive dedicated code, and the abnormal device code is detected on the data bus of the system bus by internal abnormality detection. Means for outputting the signal to the main processor board, and the abnormality monitoring means of the main processor board detects that the system abnormality signal line is asserted. And performing the abnormality generated function board from the abnormal device code to determine to continue the system operation processing on the data bus when the.

Further, according to the present invention, the abnormality monitoring means provided on the dedicated board is such that the abnormality monitoring means of the main processor board reads the abnormal device code after the system abnormality signal line is asserted. It is characterized in that a timer for monitoring the time until a cycle is generated is provided, and the function board in which an abnormality has occurred is discriminated from the abnormal device code by the time-up of this timer, and output to the outside.

Further, in the present invention, the abnormality monitoring means provided on the dedicated board is provided with a read-back means for outputting the abnormal device code latched from the data bus to the system bus side again, and the main processor is provided. One of the function boards excluding the board is provided with a timer for determining that the main processor board is stopped when the command received from the main processor board exceeds a certain time, and the time-up of this timer Then, the abnormal device code is read from the read-back means, the functional board in which the abnormality has occurred is discriminated, and the system operation is continued.

[0030]

[Function] By discriminating the board that asserts the system abnormality signal line from the abnormal device code output on the data bus, only the control / processing for this abnormal board is stopped and the control / control by other boards is performed. Continue processing, enable abnormal recovery processing, and enable system operation to continue.

Abnormality stop of the main processor board is detected by monitoring the read cycle of abnormality information of the main processor board by the timer function of the abnormality monitoring means, and the abnormality monitoring means instead of the main processor board is detected. Enables the collection of abnormal device codes by and the determination of the board in which an abnormality has occurred.

By providing a function for reading back the abnormal device code in the abnormality monitoring means, the main processor
The function boards other than the board determine which function board has an error, and enable the same control / processing and error recovery processing as the main processor board.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram for abnormality monitoring showing an embodiment of the present invention. In the figure, 200 is a main processor board that controls the system, and 210 and 22.
Reference numeral 0 is a board having an abnormality monitoring capability, and 230 is a monitoring circuit unit.

201, 211 and 221 in the board are
An abnormality information output unit for outputting abnormality information to the bus. 20
2 is the CPU section in the main processor board. 20
Reference numeral 3 is an abnormality information input unit for fetching abnormality information and notifying the CPU. 231 is an abnormality monitoring circuit. Reference numeral 232 is an abnormality output circuit for notifying an abnormality (operator or other device) to the outside.

Further, 2A is an address bus in the system bus. 2B is a data bus in the system bus. Two
C is a read command signal (hereinafter referred to as RD signal). Two
D is a SYSFAIL signal.

Reference numerals 20a, 21a and 22a denote abnormality notification signals (hereinafter referred to as ERROR signals) detected in each board. 20b, 21b and 22b are data buses for outputting an abnormal device code described later. 20c, 21c and 22c output SYSFAIL signal. RD signal input for 20d, 21d and 22d. 20e, 21e, and 22e are input buses for address signals.

Reference numerals 20f and 23f are data buses into which the main processor and the abnormality monitoring circuit input the abnormal device code. 20g and 23g input SYSFAIL signal.
20h and 23h are RD signal outputs. 20j is an address output bus of the main processor board. 23j is an address input bus of the monitoring circuit. 20k is an interrupt signal for notifying the CPU of the generation of the SYSFAIL signal.

Reference numeral 20L is an internal bus for the CPU to control the abnormal input section. 23k is the latched abnormal device code information that the abnormal monitoring circuit passes to the abnormal output circuit.

Each control signal basically operates at a low level with meaningful negative logic, and the address bus and the data bus operate at a high level with meaningful positive logic. On the bus, all signals are assumed to be pulled up to the high level side.

The operation of this embodiment will be described in detail below.

First, it is assumed that the system is operating normally. The main processor board 200 controls the entire system.

Now, the board 210 internally detects an abnormality,
Assume that the 21a signal is asserted. At this time, (1) the abnormality information output unit 211 asserts the SYSFAIL signal in order to notify the system that there is an abnormality.

(2) The line of the SYSFAIL signal 2D is asserted, and the abnormality information input section 203 and the abnormality monitoring circuit 231 sense this through the lines of the signals 20g and 23g.

(3) Abnormality information input section 203 outputs signal 20k
The CPU 202 is notified of the occurrence of an abnormality by using the interrupt.

(4) The CPU 202 controls the abnormality information input section 203 using the control bus 20L, and
After the mastership of the bus is obtained (not shown), the address output unit 20j outputs all high-level addresses (for example, 32
In the case of bit address, "FFFF FFFF
h ”) is output and the RD signal 20h is asserted in the cycle.

(5) An address in which all the bits are high level and the RD signal are input to all the boards which are detecting the abnormality and the abnormality monitoring circuit 231.

(6) The board 210 asserting the SYSFAIL signal takes in all high level addresses through the bus 21e and inputs the RD signal 21.
A unique abnormal device code is output to the data bus 21b in synchronization with d.

The abnormality information output section 211 of the board 210 is
The SYSFAIL signal output at the end of this process is negated.

This abnormal device code is a code in which each specific one bit in the data is allocated to each board having an abnormality detecting capability, and can correspond to the boards corresponding to the number of bits of the data bus. Of the multiple data lines, only the bit corresponding to the board in which the abnormality has occurred goes low.

(7) The abnormality information input section 203 reads the abnormal device code via the data input bus 20f, transmits it to the CPU 202 via the internal bus 20L, and terminates the CPU read cycle. This is called an abnormal information read cycle.

At the same time, the abnormality monitoring circuit 231 takes in the abnormal device code output on the data bus in this cycle through the line of the signal 23f and latches it in synchronization with the RD signal 23h.

(8) The CPU 202 determines the board (here, the board 210) in which an abnormality has occurred from the received abnormal device code.

The abnormality monitoring circuit 231 notifies the outside of the latched abnormal device information through the abnormality output circuit 232.

As described above, in the conventional system, the main
Even if the processor senses the SYSFAIL signal, it does not know which board in the system has caused an error, so it cannot be determined whether or not further processing is possible.
Although the control of the entire system had to be stopped at this point, in the present embodiment, the board that asserted the SYSFAIL signal can be judged using the abnormal device code, so the main processor can logically do so. In some cases, it is possible to stop only the control for the board in which the abnormality has occurred, continue the processing thereafter, and perform the processing for the abnormality recovery.

Therefore, it becomes possible to approach the fault-tolerant system requirement that the system should not be stopped easily.

Next, the system is controlled by providing the "abnormality information input unit 231 of the abnormality monitoring circuit 230 with a" timer for monitoring the time from the occurrence of the abnormality to the occurrence of the abnormal information read cycle by the main processor "". Even if the board 200, which is the main processor, stops due to an abnormality, the operation will be described below for determining the device in which the abnormality has occurred.

Now, it is assumed that the circuit in the board 200 detects an abnormality and the signal 20a is asserted.

(11) The circuit 201 first asserts the SYSFAIL signal 20c in order to notify the system that an abnormality has occurred.

(12) The line of the SYSFAIL signal 2D is asserted, and the abnormality information input section 203 and the abnormality monitoring circuit 231 sense this through the 20g and 23g lines.

(13) The abnormality information input section 203 receives the signal 2
If 0a is asserted, the CPU 202 has already
It is considered that the operation cannot be guaranteed, and the abnormal interrupt 20k for this is not asserted, and interlock is performed so as not to generate an abnormal information read cycle to the system bus.

(14) SYS input through 23g
The FAIL signal activates an "abnormality information read cycle monitoring timer" (hereinafter referred to as a monitoring timer) in the abnormality monitoring circuit 231.

(15) Since the board is interlocked in (13) above, the board 200 does not cause an abnormal information read cycle. Therefore, the monitoring timer in the 231 circuit times out. Abnormality monitoring circuit 231
RD signal 23 using the pulse at the time up
Assert h.

In the case of an abnormality other than the board 200, the monitor timer is similarly activated, but since the abnormality information read cycle is performed by the board 200 within a fixed time, there is no time-up, and therefore RD No signal is output.

(16) When the RD signal 23h is asserted, the address bus 2A is not driven by any board, but is pulled up and all the lines are in the high level state.

(17) All high-level addresses and RD signals are input to all the boards that are performing abnormality detection and the abnormality monitoring circuit 231.

(18) The board 200 asserting the SYSFAIL signal takes in all high level addresses through the bus 20e and inputs the RD signal 2
A unique abnormal device code is output to the data bus 20b in synchronization with 0d.

The abnormal output circuit 201 of the board 200 negates the output SYSFAIL signal at the end of this processing.

(19) In the abnormality monitoring circuit 231, the abnormal device code output on the data bus in this cycle is fetched via the 23f line, and the RD signal 23h is fetched.
Latch this in sync with.

(20) The abnormality monitoring circuit 231 notifies the outside of the latched abnormal device information through the abnormality output circuit 232.

As described above, even if the main processor board controlling the system has an abnormality, the device can be discriminated and the abnormality can be notified to the outside.

Next, the abnormal device code latch in the abnormality monitoring circuit 231 is provided with a read-back buffer from the system bus side (hereinafter referred to as a device code read-back register), whereby "the main processor of the system" is read. -Even if a board malfunctions, the sub-processor board in the system can take over this and continue the operation without stopping the system. " This is as follows.

First, the system consists of a main processor
In addition to the board 200, a sub
Processor board (assuming 201 is that)
And the sub-processor board has stopped the main processor according to the protocol that the command received from the main processor board (details are not specified) is monitored by the timer (the command is received within a certain period of time). In that case, it will cause a time-up and will be referred to as a command timer hereinafter).

Now, assuming that the circuit inside the board 200 detects an abnormality and the signal 20a is asserted, the above (1
The operations 1) to (20) occur. Then, the next processing is further advanced.

(21) Since the board 200 has an abnormality and stops access to the system bus, the sub processor board 210 no longer receives a command from the board 200 and the command timer expires.

(22) Sub processor board 210
Detects that the board 200 has stopped, and
The abnormal device code read back register in the abnormality monitoring circuit 230 is read out via the bus.

(23) Based on this information, the sub processor board 210 can be connected to the main processor board 20.
It is possible to confirm that 0 has caused an abnormality, and further recognize the presence / absence of another board in an abnormal state and the board.

From the above, even when the main processor board of the system has an abnormality, the sub processor board in the system can take over this and continue the operation without stopping the system. Therefore, it becomes possible to approach the fault-tolerant system requirements.

Next, each part constituting the system of FIG. 1 will be described with reference to a more specific circuit configuration example.

FIG. 2 shows an example of the overall configuration of the abnormality information input section 203 of the main processor board 200 shown in FIG.

In the figure, reference numeral 300 is the entire configuration of the abnormality information input section 203 of the main processor board of FIG. In particular, the portion 3A surrounded by the alternate long and short dash line is a portion specially provided in this configuration, and the other portions are common to a general processor board.

Reference numeral 301 denotes an output portion of the address ADRS and RD signal in the system bus interface, and 303 denotes an input / output portion of the data DATA. Reference numeral 310 represents a CPU.

Reference numeral 302 denotes an interrupt generation circuit for inputting the SYSFAIL signal on the bus to interrupt the CPU.

Further, 30a is a data input bus for inputting an abnormal device code. 30b is SYSFAIL
Signal input. 30c is an RD signal output. 30d is an address output bus. 30e is local data of the CPU 310.
bus. 30f is an interrupt signal. 30g is a bidirectional control signal between the CPU and the abnormality information input section. 30h is the local address bus of the CPU. Reference numeral 30j is an abnormality detection signal of the internal circuit corresponding to 20a in FIG.

The circuit operation of FIG. 2 will be described below.

Now, when any of the boards in the system detects an abnormality and asserts the SYSFAIL signal on the bus, the SYSFAIL signal input 30b becomes asserted. Then, when the internal abnormality signal 30j is not asserted, the interrupt generation circuit 302 causes the interrupt signal 3
0f is asserted to notify the CPU 310 of the occurrence of an abnormality.

The CPU 310 starts the interrupt processing,
In this process, all high level signals are output to the address bus 30h, and the control signal 30g is used to notify the abnormality information input circuit 300 that a read operation will be performed.

Output circuit 30 for bus address and RD signal
1 is C when the internal abnormal signal is not asserted
All the address output buses 30d are driven to a high level under the control of the PU, and the RD signal 30c is asserted.
The CPU is notified that the cycle is terminated (ready signal) using the control signal 30g after a fixed time.

At the same time, when the internal abnormal signal 30j is not asserted, the data input / output unit 303 inputs the abnormal device code output on the bus through the data input bus 30a, and the CPU local data is input.・
This information is transmitted to the bus 30e.

As a result, the CPU 310 reads the abnormal device code and recognizes it.

Next, FIG. 3 shows a circuit configuration example of the abnormality information output units 201, 211, 221 in the main processor board and other abnormality detection boards.

In the figure, 400 is the entire abnormality information output section. Reference numeral 410 represents an internal circuit of the abnormality detection board.

An address decode circuit 401 receives the bus address ADRS and generates selection signals for various circuits from the input state. 402 is an RD signal input buffer. A NAND circuit 403 has an inverted input. 404 is a latch of an internal abnormal signal. 405 is an inverting buffer of the SYSFAIL signal of the open collector output. 406 is an inverter type three-state buffer for outputting an abnormal device code to the data bus. A data buffer 407 is used for normal processing.

Reference numeral 40a is an input / output bus for data DATA. 40b is a SYSFAIL signal output. 40c is an RD signal input. 40d is an address input bus. 40e is an internal circuit abnormality detection signal. 40f is a selection signal indicating that all high level states have been detected in the address decoder section. 40
g is the RD signal to the internal circuit. 40h is an inverted NAND (equivalent to OR) output of 40f and 40g. 40j is an abnormal device code signal buffered by the circuit 406. 40k is an internal data bus. 40L is an address decoder output signal for the internal circuit.

The portion 4A surrounded by the one-dot chain line is a portion unique to this abnormality monitoring system, and the other portions are included in the bus interface circuit of a normal board.

A section 4B surrounded by a dotted line is a setting section for selecting a bit whose board should output a low level to the data bus as an abnormal device code. Each abnormality detection board is set to output an abnormality signal to a bit having an exclusive number.

The setting section 4B, which is shown by mechanical setting, electrically and automatically selects exclusive output data bits when a geographical address input line is defined on the bus. It can also be configured as follows.

The operation of the circuit shown in FIG. 3 will be described below.

When an abnormality is detected in the internal circuit 410, the abnormality detection signal 40e is asserted. This is latched in the latch circuit 404 upon occurrence and
Through 05, the SYSFAIL signal on the bus is asserted.

Thereafter, if the board asserting the SYSFAIL signal is not the main processor board, an abnormal information read cycle is caused by this main processor board, and the board asserting the SYSFAIL signal is the main processor board. If it is a board, the abnormality monitoring circuit asserts the RD signal on the bus.

In any of these cases, the RD signal is pulsed while the address lines on the bus are all at the high level. Then, all the address input buses 40d are set to the high level state, so that the address decoder 4
01 output 40f is asserted.

Since the RD signal on the bus is input by the buffer 402 and the 40g signal is also asserted, the signal 40h which is the output of the inverted NAND circuit 403 is also asserted.

The activation of the signal 40h enables the 3-state buffer 406 and the data bit set in 4B is driven to the low level because the signal 40e is originally asserted.

The RD signal is a pulse, and once asserted, it is negated after a fixed time.
The signals are negated in the order of g, 40h, 40j, and the output of the abnormal device code information to the data bus ends.

On the other hand, at the edge when the 40h signal is negated, the latch circuit 404 in the abnormal state is cleared and the SYSFAIL signal output to the bus is negated.

Next, FIG. 4 shows the abnormality monitoring circuit section 2 in FIG.
An example of the circuit configuration of 31 is shown. In the figure, reference numeral 500 is the entire abnormality monitoring circuit, and 510 is an abnormality output circuit for outputting abnormality information to the outside.

An address decoder circuit 501 receives the bus address ADRS and generates selection signals for various circuits from the state. 502 is an input buffer for the RD signal.
Reference numeral 503 is a SYSFAIL signal input buffer. 504 is a 3-input inverted NAND circuit. Reference numeral 505 is an input latch circuit for an abnormal device code.

Reference numeral 506 is a timer circuit for monitoring the time from the occurrence of an abnormality to the occurrence of an abnormality information read cycle by the main processor. Reference numeral 507 is an open collector type inverted buffer for outputting the time-up signal of the timer circuit 506 as an RD signal to the bus.

Reference numeral 508 is an abnormal device code read back register. Reference numeral 509 is a 2-input inverted NAND circuit.

Reference numeral 50a is a data input bus. 50b
Is the SYSFAIL signal input. 50c is an RD signal input. 5
0d is an address input bus. 50e is S after buffer input
YSFAIL signal. 50f is the RD signal after buffer input. 50g is a selection signal indicating that all high level states have been detected in the address decoder section.

50h is 50e signal, 50f signal and 50g
This signal is asserted when all the signals are asserted, and indicates that the addresses are all at the high level when the SYSFAIL signal is generated and the RD signal is asserted.

Further, 50j is the abnormal device code information after the latch given to the abnormal output circuit 510. 50k
Is a selection signal indicating that the address state previously set by the address decoder unit 501 for reading the abnormal device code read-back register is detected.

50L is a signal which is asserted when both 50k and 50f are asserted, and indicates that the address of the abnormal device code read-back register 508 has been read. 50m is abnormal device code read back data
bus. 50n is a selection signal given to another circuit from the address decoder. Reference numeral 50p is a pulse signal indicating the time-up of the monitoring timer circuit 506.

The operation of FIG. 4 will be described below.

Now, assume that an abnormality is detected by an abnormality detection board other than the main processor board, and the SYSFAIL signal is asserted. This asserts the 50b signal input and interrupts the CPU of the main processor board, causing the processor board to generate an abnormal information read cycle.

This causes a high level read cycle for all address lines on the system bus. Then, the address decoder circuit 501 asserts the 50g signal by the address input of 50d.

Next, since the RD signal on the bus is asserted, the 50f signal is asserted through the buffer 502 having the input of the 50c signal. Since the 50b signal is already asserted and the 50e signal is also asserted through the buffer 503, the output 50h of the inverted NAND 504 is also activated.

At this point, RD is set on the abnormality detection board side.
Since the abnormal device code is output to the data bus in synchronization with the pulse, this code information is given to the section 50a.

The RD signal on the bus is a pulse, and when it is negated, the signals are negated in the order of 50c, 50f, and 50h. At the edge of the negation of the 50h signal, the latch circuit 505 causes the signal to rise above 50a. Abnormal device
Latch the cord. The output 50j of this latch is given to the abnormal output circuit 510, and this output circuit notifies this information to the operator or other external device as a display or an abnormal signal.

The above-mentioned operation realizes the first advantage described above. At this time, only the portion 5A surrounded by the one-dot chain line operates on FIG.

Now, assuming that the main processor board itself has an abnormality, SYSFAI
After the L signal is asserted, the main processor board does not generate an abnormal information read cycle, and thus no read cycle occurs on the bus.

At this time, if the timer circuit 506 for monitoring the time from the assertion of the SYSFAIL signal to the time of negation is provided, the timer circuit 506 times up after a fixed time and outputs the pulse signal of 50p. 5
The 0p signal is output to the RD signal line on the bus through the buffer 507.

Then, since the address line does not have a board to be driven and therefore all show a high level due to pull-up, the same state where the main processor has generated an abnormal read cycle is on the system bus. Will be realized. The subsequent operation is as described above.

As a result, the second advantage that the abnormal board can be discriminated even when an abnormality occurs in the main processor board is realized. In this case, the portions 5A and 5B surrounded by the alternate long and short dash line in FIG. 4 operate.

Finally, in addition to the main processor board in the system, a sub-processor
When the board is mounted and the main processor board stops abnormally, the abnormal device code latched in the abnormal device code input latch circuit 505 by the above operation can be read from the system bus side. If this is done, the sub processor that has detected that the command from the main processor board has stopped can read this information and accurately grasp the abnormal state of the system, and it may be possible to continue control beyond that. .

In this case, the address decoder circuit 501 detects an address preset for reading the abnormal device code read-back register 508,
Assert the signal. The output 50L signal of the NAND circuit 509 is asserted under the condition that this and the RD signal 50f are asserted, and by enabling the read-back buffer register 508, the abnormal device code latched in the input latch circuit 505 is transferred to the system bus. Read on upper data bus.

This is the third advantage. In this case, the portions 5A, 5B and 5C surrounded by the one-dot chain line in FIG. 4 operate.

In the embodiment, description will be made assuming that all address lines are at a high level state as an address for outputting an abnormal device code to the abnormal information output circuit. Main processor
This is because it is not necessary to have an address output circuit when the abnormality monitoring circuit takes over the read cycle of the abnormal device code when the board abnormally stops. This is advantageous in that it does not increase the amount of hardware.

Actually, if a predetermined address for reading the abnormal device code is set in the abnormality monitoring circuit and a circuit for outputting this is provided, it should be output when reading the abnormal device code. All addresses need not be limited to high level addresses.

[0129]

As described above, according to the present invention, in a multi-processor system in which an abnormality is monitored by asserting a system abnormality signal line, each function board detects an abnormality inside and outputs an abnormal device code for each board. Since it outputs to the data bus and the abnormality monitoring means of the main processor board determines the abnormal function board from the abnormal device code when the system abnormal signal line is asserted, the abnormal signal interrupt function is set. Without using it, the main processor board, if logically possible, can stop only the control of the board in which the error occurred and continue processing beyond it, or perform the error recovery processing. , Enables continuous system operation.

Further, according to the present invention, the abnormality monitoring means provided as a dedicated board is configured such that the main processor board is in the abnormal device state after the system abnormality signal line is asserted.
The main processor board is equipped with a timer that monitors the time until a code read cycle occurs, and when the timer expires, the function board in which an error has occurred is identified from the abnormal device code and output to the outside. It is possible to take out the information specifying the board in which the abnormality has occurred to the outside even after the stop.

Further, according to the present invention, the abnormality monitoring means provided as a dedicated board is provided with a read-back means for outputting the abnormal device code again to the system bus side, and is one of the function boards excluding the main processor board. The function board is provided with a timer that determines that the main processor board is stopped when the command received from the main processor board exceeds a certain time, and when this timer times out, the abnormal device code is read from the read-back means and abnormal Since the function board that occurred is identified,
Even when the processor board is stopped, the same function is taken over by another board, allowing the system operation to continue.

Further, since the present invention has a small amount of hardware for notifying and detecting an abnormality in each board and is simple, the failure monitoring in this portion hardly causes failure of abnormality monitoring, and reliability is high. Highly reliable abnormality monitoring is possible.

Further, since the present invention can realize the function by a slight change on the board side relating to the abnormality detection, it is not necessary to add or change the signal line of the standard bus.

[Brief description of drawings]

FIG. 1 is a system configuration example of an abnormality monitoring system showing an embodiment of the present invention.

FIG. 2 is a circuit configuration example of an abnormality information input unit of the processor board in the embodiment.

FIG. 3 is a circuit configuration example of an abnormality information output unit of the processor board and other abnormality detection boards in the embodiment.

FIG. 4 is a configuration example of a monitoring circuit according to the embodiment.

FIG. 5 shows an example of a conventional system abnormality monitoring method.

[Explanation of symbols]

 200 ... Main processor board 210, 220 ... Board having abnormality monitoring capability 230 ... Monitoring circuit unit 201, 211, 221, ... Abnormality information output unit 203 ... Abnormality information input unit 231, ... Abnormality monitoring circuit 232 ... Abnormality output circuit

Claims (3)

[Claims] 1. A plurality of function boards are coupled by a system bus, and each function board has an abnormality information output section for asserting one system abnormality signal line of the system bus for internal abnormality detection. In a multi-processor system in which the abnormality monitoring means provided on the main processor board of the boards and the abnormality monitoring means provided as a dedicated board perform abnormality monitoring by asserting the system abnormality signal line, each functional board is exclusive. Has an abnormal device code which becomes a dedicated code, and provides means for outputting the abnormal device code on the data bus of the system bus when detecting an internal abnormality, and monitors the main processor board for abnormalities. Means are provided for data transfer when the system fault signal line is asserted.
An abnormality monitoring method characterized in that a function board in which an abnormality has occurred is discriminated from the abnormal device code on the bus and processing for continuing system operation is performed. 2. The abnormality monitoring means provided on the dedicated board causes the abnormality monitoring means of the main processor board to cause a read cycle of the abnormal device code from the time when the system abnormality signal line is asserted. 2. The abnormality monitoring method according to claim 1, further comprising: a timer for monitoring the time until the abnormality is detected, and a function board in which an abnormality has occurred is discriminated from the abnormal device code by the time-up of the timer and is output to the outside. 3. The abnormality monitoring means provided on the dedicated board is provided with a read-back means for outputting the abnormal device code latched from the data bus to the system bus side again, and excludes the main processor board. One of the function boards is configured to operate when the command received from the main processor board exceeds a certain time.
A timer for determining that the processor board is stopped is provided, and when the timer expires, the abnormal device code is read from the read-back means, the functional board in which the abnormality has occurred is determined, and the system operation is continued. The abnormality monitoring method according to claim 1.