JPH07201851A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a method of manufacturing a semiconductor device using Cu as a wiring material, which prevents Cu oxidation and erosion during the process, and has a low resistance and a high reliability. Is to be realized by a simple method. A step of forming an insulating film 1 on a semiconductor substrate, a step of depositing an underlying barrier metal 2 on the insulating film 1, and a step of depositing a Cu layer 3 on the underlying barrier metal 2. Depositing an overlaid barrier metal 4 on the Cu layer 3, forming an oxide film mask 12 on the overlaid barrier metal 4, and depositing the overlaid barrier metal 4, C
The step of etching the u layer 3 and the underlying barrier metal 2 to form the wiring pattern 7, the step of depositing the side wall barrier metal 13 covering the wiring pattern 7 and the oxide film mask 12, and the horizontal direction of the side wall barrier metal 13 Parts by anisotropic etching to leave only vertical parts, a step of forming an interlayer film 8 covering the pattern, and a step of chemical mechanical polishing the interlayer film 8 and the oxide film mask 12 at the same time to remove the surface. And a step of flattening.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a wiring material made of Cu or C.
The present invention relates to a method for manufacturing a semiconductor device using a u alloy. Due to the miniaturization of wiring accompanying the recent high integration of LSI, electromigration and stress migration have become severe in the conventional wiring made of AL (aluminum) alloy. Therefore, W and Mo are used as alternative materials for AL.
Although high-melting-point metals such as, for example, are about to be put to practical use, there is a drawback that the specific resistance is as high as twice or more than AL.

Therefore, as a next-generation wiring material, C which is resistant to electromigration and has low resistance
u is drawing attention.

[0003]

2. Description of the Related Art FIGS. 5 to 7 show a standard process flow for forming Cu wiring by a conventional manufacturing method. First, a flat insulating film 1 is formed on a semiconductor substrate (B1 in the same figure). The insulating film 1 is, for example, SiO ₂ , PSG, BPSG
Etc.

An underlay barrier metal 2, a Cu layer 3, and an overlaid barrier metal 4 are sequentially formed thereon by a sputtering method (B2 to B4) to form a metal three-layer structure. The underlay barrier metal 2 not only prevents the Cu layer 3 from reacting with the insulating film 1, but also plays a role of bringing the Cu 3 and the insulating film 1 into close contact with each other. The additional barrier metal 4 is formed by chemical treatment and oxidation in the photolithography process that will be performed later.
It is provided to protect the Cu layer 3.

Next, in order to form a wiring pattern, a resist 5 is applied over the entire surface (B5), and exposure and development are performed by a normal photolithography method to form a resist mask 6.
Are formed (B6). Using this as a mask, etching is performed to form a wiring pattern 7 (B7), and finally, the resist mask 6 is removed by oxygen ashing to form the wiring pattern 7.
Is completed (B8).

Further, the interlayer film 8 is grown by the CVD method to cover the entire wiring pattern 7 (B9). For multi-layer wiring,
Again, the above steps are repeated from B2.

[0007]

Cu is very easily oxidized, and its surface is oxidized only by leaving it in the air for several hours. Also, due to the heat applied during the process, Si, Si
Reacts easily with O ₂ , PSG, etc. Further, it has low chemical resistance and is easily eroded during chemical treatment. If the heat applied during the process reacts with Si, SiO _2, etc., and oxidation proceeds to the inside, the low resistance, which is an advantage, is impaired. Further, when it is corroded by chemicals, the reliability of the wiring cannot be guaranteed.

The above problems will be specifically described along the conventional process flow shown in FIGS. Even in the related art, some measures are taken against such a problem. That is, by providing the additional barrier metal 4, the natural oxidation of the Cu layer 3 is prevented in the step B4, the Cu layer 3 is protected from the surfactant or the like used in the pretreatment of the resist coating in the step B4, and the developing solution or the like in the step B6. To protect the Cu layer 3. Further, the additional barrier metal 4 prevents oxidation of the upper surface of the Cu layer 3 during oxygen ashing of the resist in B8, and oxidation in the growth of the interlayer film 8 and reaction with the interlayer film 8 itself in B9 prevent the Cu layer 3 from being oxidized. Protect the upper surface of.

However, even with the additional barrier metal 4, the measures against the above problems are not perfect. That is, when oxygen ashing of the resist is performed in step B8, Cu
The sidewalls of layer 3 will be oxidized. Interlayer film 8 at B9
The side wall of the Cu layer 3 is also oxidized when growing
Further, the sidewall of the Cu layer 3 reacts with the interlayer film 8 in the subsequent heat treatment.

With the recent miniaturization of integrated circuits, the width of wiring has become smaller, and the cross-sectional shape thereof is changing from a horizontally long shape to a square shape and further to a vertically long shape. Therefore, when the side wall of the wiring is oxidized to increase the resistance at that portion, the influence on the resistance of the entire wiring is increasing. Especially Cu
This problem is serious in the case of wiring because oxidation proceeds to the inside.

An object of the present invention is to solve such problems and to realize Cu wiring having low resistance and high reliability inherent in Cu by a practical and simple process.

[0012]

According to the manufacturing method of the present invention, a step (A1) of forming an insulating film 1 on a semiconductor substrate and a step (A) of depositing an underlying barrier metal 2 on the insulating film 1 are performed.
2), a step (A3) of depositing the Cu layer 3 on the underlying barrier metal 2, a step (A4) of depositing an additional barrier metal 4 on the Cu layer 3, and a step of depositing the additional barrier metal 4 A step of patterning an oxide film mask 12 thereon (A5 to A9); a step of etching the overlaying barrier metal 4, the Cu layer 3, and the underlying barrier metal 2 to form a wiring pattern 7 (A10); A step of depositing the sidewall barrier metal 13 so as to cover the wiring pattern 7 and the oxide film mask 12 (A11), and a step of removing a horizontal portion of the sidewall barrier metal 13 by anisotropic etching and leaving a vertical portion (A12). And a step (A13) of forming the interlayer film 8 covering the pattern, and simultaneously polishing the interlayer film 8 and the oxide film mask 12 to expose the additional barrier metal 4, One the plus barrier step of flattening by aligning the upper surface of the exposed surface and the interlayer film 8 of metal 4 (A1
4) and are included.

[0013]

The operation of the present invention will be described with reference to FIGS. In the present invention, after forming the wiring pattern 7 in step A10, the wiring pattern 7 and the oxide film mask 12 are collectively covered with the sidewall barrier metal 13 without removing the oxide film mask 12 (A11). This makes Cu
The circumference of the layer 3 is completely covered with the barrier metal, and the Cu layer 3 is not oxidized or attacked by chemicals in any process thereafter.

After all, according to the present invention, from the beginning to the end of the process flow, the Cu layer 3 is never oxidized or exposed to chemicals, and the Cu wiring has low resistance and high reliability. Can be formed. Further, the present invention provides
The removal of the oxide film mask 12 and the planarization of the interlayer film 8 are combined to shorten the process. That is, in step A14, the interlayer film 8 is chemically mechanically polished to be planarized, and at the same time, the oxide film mask 12 is removed.

Therefore, according to the present invention, in a simple process,
It is possible to form Cu wiring suitable for multilayer wiring.

[0016]

1 to 4 show a process flow of an embodiment of the present invention. First, a flat insulating film 1 is formed on a semiconductor substrate (A1). The insulating film 1 is made of, for example, SiO ₂ , PS.
It is a film made of G, BPSG or the like. The underlying barrier metal 2 is formed by depositing 500N of TiN on the insulating film 1 by the sputtering method (A
2). The sputtering of TiN, for example, has a pressure of 3 mTo
Power of 4 kW in mixed gas atmosphere of Ar and N _{2 of} rr
It is performed under the conditions of. Underlay barrier metal 2 is Cu layer 3
Has a role of preventing the Cu layer 3 from reacting with the insulating film 1 and a role of an adhesion layer for preventing the Cu layer 3 from peeling off from the insulating film 1.

Then, a Cu layer 3 is formed on this by depositing Cu by 4000 Å by a sputtering method (A3). The Cu sputtering is performed in an Ar atmosphere with a pressure of 5 mTorr and a power of 4 kW, for example. Further, TiN is deposited thereon by 1000 Å by a sputtering method to form an additional barrier metal 4 (A4). The additional barrier metal 4 is
It serves to protect the upper surface of the Cu layer 3 from oxidation and corrosion by chemicals. In order to avoid natural oxidation of the upper surface of the Cu layer 3, it is desirable to sputter the Cu layer 3 and then form the additional barrier metal 4 continuously without exposing to the atmosphere. Further, the additional barrier metal 4 is formed in the subsequent step A1.
Since it plays a role of a stopper for chemical mechanical polishing in No. 4, it is 1000 Å thicker than the underlying barrier metal 2.

Next, in steps A5 to A9, an oxide film mask 12 is formed as an etching mask for patterning the wiring. First, the oxide film 11 is removed by plasma CVD or bias ECR-CVD.
Accumulate 000Å (A5). A resist 5 is applied thereon (A6), and a resist mask 6 is formed by a normal photolithography method (A7). The oxide film 11 is etched using this as a mask (A8), and finally the resist mask 6 is removed to complete the oxide film mask 12 (A8).
9).

Next, reactive ion etching is performed using the oxide film mask 12 as a mask to form the wiring pattern 7 (A10). Reactive ion etching is performed by, for example, SiCl at a substrate temperature of 400 ° C. and a pressure of 2.6 × 10 ⁻² Torr.
High frequency power of 400 W in mixed gas of ₄ , N ₂ and CH ₄
Is applied. The reason why the oxide film mask 12 is formed as a mask without using the resist as a mask is that the resist cannot withstand the high temperature of 400 ° C.

Next, without removing the oxide film mask 12,
Immediately, the sidewall barrier metal 13 is deposited by the thermal CVD method (A11). The side wall barrier metal 13 has a film thickness of 500Å
TiN. TiN by the thermal CVD method is, for example,
Deposition is carried out at a temperature of 450 ° C. using a mixed gas of titanium tetrachloride, ammonia and methylhydrazine at a pressure of 100 mTorr. The TiN may be formed by a sputtering method.

Through the above steps, the Cu layer 3 is not exposed to an oxidizing atmosphere or a corrosive chemical, and the surroundings thereof are covered with Ti.
I was able to completely enclose with N. Next, anisotropic etching is performed to remove only the horizontal portion of the sidewall barrier metal 13 by etching (A12). The horizontal portion is a portion on the insulating film 1 and a portion on the upper surface of the oxide film mask 12. The portion on the insulating film 1 needs to be removed in order to electrically separate adjacent wirings from each other, and the portion on the upper surface of the oxide film mask 12 needs to be removed by chemical mechanical processing in a subsequent step A14. It is necessary to remove it because it does not hinder polishing.

Next, the entire pattern is covered with the interlayer film 8 (A13). The interlayer film 8 is, for example, PSG, SiO ₂ or the like. Since the film thickness is flattened in the next step A14,
Make it thicker than the wiring pattern. Here, 7,000 Å is deposited. Next, chemical mechanical polishing is performed until the additional barrier metal 4 appears (A14). By this step, the oxide film mask 12 and the excess portion of the sidewall barrier metal 13 are removed, and the surface is completely planarized.

In the case of forming an upper layer wiring, the second insulating film 14 is formed thereon (A15), and the steps from A2 are repeated.

[0024]

According to the present invention, since the periphery of the Cu layer 3 is completely covered with the refractory metal or the refractory metal compound, the Cu layer 3 is not oxidized and is corroded by chemicals. Nothing. Therefore, it is possible to form a Cu wiring having low resistance and high reliability inherent in Cu.

Further, in the present invention, the step of enclosing the periphery of the Cu layer 3 and the planarization step are combined to simplify the step. Therefore, according to the present invention, in a simple process,
It is possible to form a Cu wiring having a low resistance and a high reliability, which has a flattening structure suitable for a multilayer wiring.

[0026]

[Brief description of drawings]

[0027]

FIG. 1 is a first diagram showing an example of the manufacturing method of the present invention (steps A1 to A4).

[0028]

FIG. 2 is a second diagram showing an example of the manufacturing method of the present invention (steps A5 to A8).

[0029]

FIG. 3 is a third diagram showing an example of the manufacturing method of the present invention (steps A9 to A12).

[0030]

FIG. 4 is a fourth diagram illustrating an example of the manufacturing method of the present invention (steps A13 to A15).

[0031]

FIG. 5 is a first diagram showing a conventional manufacturing method (steps B1 to B4).

[0032]

FIG. 6 is a second diagram illustrating a conventional manufacturing method (processes B5 to B8).

[0033]

FIG. 7 is a third diagram illustrating the conventional manufacturing method (step B9).

[0034]

[Explanation of symbols]

 1 Insulating Film 2 Underlay Barrier Metal (TiN) 3 Cu Layer 4 Overlay Barrier Metal (TiN) 5 Resist 6 Resist Mask 7 Wiring Pattern 8 Interlayer Film 11 Oxide Film 12 Oxide Film Mask 13 Sidewall Barrier Metal (TiN) 14 Second Insulation film

Claims (4)

[Claims] 1. A step of forming an insulating film (1) on a semiconductor substrate, a step of depositing an underlay barrier layer (2) on the insulating film (1), and a step of depositing the underlay barrier layer (2). A step of depositing a metal film (3) on the metal film (3), a step of depositing an overlaid barrier layer (4) on the metal film (3), and an etching mask (1
2) patterning and forming, the step of etching the overlaid barrier layer (4), the metal film (3), and the underlying barrier layer (2) to form a wiring pattern (7), and the wiring pattern (7) ) And a sidewall barrier layer (13) so as to cover the etching mask (12), and a step of removing a horizontal portion of the sidewall barrier layer (13) by anisotropic etching and leaving a vertical portion. By forming the interlayer film (8) covering the pattern and polishing the interlayer film (8) and the etching mask (12) at the same time, the additional barrier layer (4) is exposed and the additional barrier layer (4) is exposed. ) And the upper surface of the interlayer film (8) are aligned and planarized. 2. The method according to claim 1, wherein the metal film (3) is made of copper or a copper alloy. 3. The underlay barrier layer (2), the overlay barrier layer (4), and the side wall barrier layer (13) are made of TiN, W, TiW, Ta, Mo, or Nb, respectively. The manufacturing method according to claim 1, wherein 4. The method according to claim 1, wherein the etching mask (12) is one of a silicon oxide film, a silicon nitride film, and a resist.