JPH07200180A - Data transfer controller - Google Patents

Abstract

(57) [Abstract] [Purpose] To enable large-capacity and high-speed data transfer without using an expensive disk device. [Structure] Having a plurality of disk devices and a memory for storing data to be transferred, the disk interface control means 12a to 12c control the interface with the disk devices 11a to 11c and output a data transfer request signal, The host interface control means 14 controls the interface with the upper position device, outputs a data transfer request signal, and memory access request means 13a-13.
c outputs an address signal and an access request signal to the memory 17 in response to the data transfer request, and when there are a plurality of access requests at the same time, the memory access control means 16 outputs the memory based on the preset priority order. High-speed data transfer is possible by selecting a memory access requesting unit that permits access and operating each disk device in parallel with memory access as time division.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for controlling large-capacity data transfer used in an external storage device such as a computer.

[0002]

2. Description of the Related Art In recent years, as the data processing performance of computers has improved, the capacity of programs and data has increased, and it has been desired to develop a large-capacity external storage device as a peripheral device. In response to such a demand, an external storage device that realizes a large storage capacity by using a plurality of available disk devices has been developed.

In an external storage device using such a plurality of disk devices, there has been proposed a method of increasing not only the storage capacity but also the speed of data transfer. For example, while controlling the rotation synchronization of a plurality of disk devices, the phases of the rotation synchronization are evenly distributed, and the read / write start and end timings of the respective disk devices are shifted, so that the data transfer on the data bus is prevented. Those trying to avoid competition have been proposed. This conventional technique will be described with reference to the drawings.

FIG. 14 is a block diagram of a conventional device.
1 is a host computer, 142 is a control device, 143 is a data buffer, 144 is a control unit, 145 is a data bus, 146 is a control bus, 147 is a disk device, 148.
Is a rotation synchronization control device, and 149 is a data division / synthesis device.

FIG. 15 is a timing chart at the time of reading when the disk devices are connected in three columns in this device. In this example, the rotational synchronization phase of each disk device is shifted by 120 °, the disk device in the first column reads data from the disk medium, and then transfers the data to the data buffer. 2 in parallel
Read the lead of the disk device in the first row from the lead in the first row to 12
It is carried out with a delay of 0 °, and after the data transfer of the first column, the data transfer of the second column is also started with a delay of 120 °. Similarly, data is read and data is transferred also to the disk device in the third row, and the phases of the rotation synchronization are evenly distributed to avoid duplication of the use section of the data bus. 238527).

Further, in recent years, CD (compact disc)
Attention has been paid to the low-priced and large-capacity performance, and its use as a data disk for computers in addition to conventional music applications is in the limelight. That is, by storing programs, compressed moving image data, and audio data in a CD, new applications such as multimedia and games, which cannot be achieved by conventional magnetic disks and floppy disks, are being actively developed. .

[0007]

However, this conventional method requires a device for controlling the synchronous rotation with the phase evenly shifted for each disk device, and further, as each disk device, for synchronizing rotation. Since an expensive disk device having a function is required, there is a problem that the device becomes expensive.

Further, a CD generally has a lower data transfer rate than a magnetic disk, and it is necessary to consider the data transfer rate when developing an application using the CD. For example, in the process of developing an application that uses a CD, if data that is sequentially created is stored on a magnetic disk, a moving image or sound that can be reproduced without problems at the high data transfer rate of the magnetic disk in the data confirmation step is When data is stored in the CD in the final step, moving images and audio may be interrupted due to the low data transfer rate. In addition, a once-writable CD and a write-only device for the same have been commercially available in recent years. However, in the development of an application that requires creation of an enormous amount of data, it is not possible to use such a once-writable CD sequentially. There was a problem that the cost of creation would be very expensive.

The present invention solves the above problems. First, it provides a data transfer control device capable of high-speed data transfer with a large capacity without using an expensive disk device. It is an object of the present invention to provide an inexpensive data transfer control device for an application that requires a limited capacity and a limited data transfer rate.

[0010]

In order to solve the above problems, a data transfer control device of the present invention stores a plurality of disk devices and data to be transferred between the plurality of disk devices and a host device. For controlling the interface between the memory and the plurality of disk devices and outputting a data transfer request signal, and an address for the memory according to the data transfer request signal output from the disk interface control means. A first memory access requesting means for outputting a signal and an access requesting signal, a host interface controlling means for controlling an interface with a host device and outputting a data transfer requesting signal, and data output from the host interface controlling means. In response to the transfer request signal, the address for the memory is A second memory access request means for outputting a less signal and an access request signal, an access request signal and an address signal from said first memory access request means and said second memory access request means inputs,
Controls input / output of data between the memory and the first memory access requesting means or the second memory access requesting means, and sets a priority order when a plurality of access requests exist at the same time. Memory access control means for selecting either the first memory access requesting means or the second memory access requesting means based on the above.

Further, the data transfer control device of the present invention divides the address space of the memory into blocks, and the first memory access requesting means and the second memory access requesting means start data transfer. A start signal is input, data transfer within a block is performed based on a block address signal that selects the block, and a data transfer end signal indicating the end of data transfer within the block is output. A block address signal to be selected is generated, the data transfer start signal is output to each of the first memory access requesting means and the second memory access requesting means, and the first memory access requesting means and the second memory are output. The data transfer end signal is inputted from the access requesting means, and the first memory access requesting means and the second memory are inputted. It is characterized in that each of the access request means has a means for managing the transfer block to perform data transfer.

Further, the data transfer control device of the present invention is
When the means for managing the transfer block has a timer function and the data transfer in the block of the second access request means ends within a preset timer value, when the timer value is reached, the next And a block address indicating a block to be transferred to the second memory access requesting means, and a data transfer start signal to the second memory access requesting means.

[0013]

The data transfer control device of the present invention transfers data between each disk device and the host device via the memory, and the first memory access is performed in response to a data transfer request from each disk device. The requesting means and the second memory access requesting means respectively make access requests to the memory in response to a data transfer request from the host device,
If there are multiple access requests at the same time, the memory access control means selects the memory access request means for accessing the memory based on the preset priority order, and sets the memory access as time division to parallelize each disk. The high speed data transfer becomes possible by operating the above.

Further, in the data transfer control device of the present invention, the address space of the memory is divided into blocks, and the first memory access requesting means and the second memory access requesting means perform the data transfer within the block and transfer the data. The first and second memory access requesting means manage the selection of the block to be transferred and the transfer status, respectively, so that the block managing means controls the data transfer at high speed and with high reliability. Is possible.

Further, the data transfer control means of the present invention is
The means for managing the transfer block has a timer function, and the data transfer speed can be limited by controlling the data transfer time of the second memory access requesting means in block units using this timer function.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, a first embodiment of the present invention will be described for the purpose of realizing a large capacity and a high data transfer rate. FIG. 1 is a block diagram of the data transfer control device of the first embodiment.

Reference numeral 11 denotes a disk device, and in this embodiment, three magnetic disk devices 11a, 11b and 11c having a SCSI interface were used. 12a, 12
Reference numerals b and 12c are disk interface control means for controlling the interfaces of the disk devices 11a, 11b and 11c, and are general-purpose SCSI protocol control ICs.
Was used.

Reference numerals 13a, 13b and 13c are first memory access request means for outputting an access request signal in response to a data transfer request of the disk interface control means 12a, 12b and 12c, and a function for generating an address for a memory which will be described later. It is also equipped with.

Reference numeral 14 denotes a host interface control means for controlling an interface with a host device (for example, a host computer device) that requests data transfer to this device. In this embodiment, the interface with the host device is a SCSI interface. , The disk interface control means 12a, 12b, 12c and S
An IC for controlling the CSI protocol was used.

Reference numeral 15 is a host interface control means 1.
No. 4, which is a second memory access requesting means for outputting an access requesting signal in response to the data transfer request, and has a function of generating an address for the memory similarly to the first memory access requesting means 13a, 13b, 13c. Is.

Reference numeral 16 is a first memory access request means 13
a, 13b, 13c and second memory access requesting means 1
In response to the access request of No. 5, the memory access control unit selects an address from each memory access request unit based on the set priority and generates a control signal for accessing the memory.

Reference numeral 17 is a memory for temporarily storing data. In the present embodiment, an access time of 70 nsec.
RAM was used. Reference numeral 18 denotes each disk device 11a, 11b, 11c via the disk interface control means 12a, 12b, 12c in response to a data transfer request command from the host device input to the device via the host interface control means 14. This is a device control unit that controls the entire device by setting a command and setting a priority order for access to the memory access control unit 16. In this embodiment, a general-purpose CPU is used.

The IC used as the disk interface control means 12a, 12b, 12c in the present embodiment has a register for setting an operation mode, the number of transfer data, etc. inside, and is a SCSI for transferring data and control signals to and from a SCSI device. A bus, a data transfer request signal BREQ, a data transfer enable signal BACK, and a data transfer bus composed of a data BDAT bus for inputting / outputting data transferred by the SCSI bus, and a bus related to input / output of internal registers Is. The SCSI bus is connected to each disk device 11a, 11b, 11c, and the data transfer bus is the first memory access request means 13a, 13.
b and 13c, and the bus related to the input / output of the register is connected to the CPU 18. When the disk interface control means 12a, 12b, 12c input / output data in byte units via the SCSI bus,
Handshake using the BREQ signal and the BACK signal is performed, and the first memory access requesting means 1 is connected to the BDAT bus.
Data is transferred to 3a, 13b, and 13c.

Similarly, the SCSI bus of the host interface control means 14 is connected to the host device, the data transfer buses (BREQ, BACK, BDAT) are connected to the second memory access request means 15 and the bus for register input / output. Is connected to the CPU 18, and when data is input and output in byte units via the SCSI bus, the BRE
Perform a handshake using the Q and BACK signals,
Data is transferred to and from the second memory access requesting means 15 via the BDAT bus.

First memory access request means 13a, 1
3b, 13c, and second memory access requesting means 1
Reference numeral 5 includes a counter for generating an address XADD for the memory 17 and a bidirectional data latch, respectively.
a, 12b, 12c, or when data transfer is performed with the host interface control means 15 by handshake using the BREQ signal and the BACK signal, the value of the counter is incremented and the memory access control means 16 and the XREQ signal are transmitted. A handshake is performed using the XACK signal, and data is transferred via the XDAT bus.

The operation of the data transfer control device of this embodiment configured as described above will be described. In FIG. 2, data is read from the memory 17 and the disk device 11a, via the disk interface control means 12a, 12b, 12c,
11 is a timing chart when transferring data to 11b and 11c, and FIG. 3 is a timing chart when storing data input to this device in the memory 17 via the disk interface control means 12a, 12b and 12c. is there.

First, referring to FIG. 2, the disk device 11a,
A case of transferring data to 11b and 11c will be described. When a data transfer request comes from the disk device on the SCSI bus, the disk interface control means 12a, 1
2b and 12c make the BREQ signal active (“H” level) and the first memory access requesting means 13a and 13
Request data from b and 13c. When the first memory access requesting means 13a, 13b, 13c recognize that the BREQ signal is active, the first memory access requesting means 13a, 13b, 13c outputs valid data to the BDAT bus and activates the BACK signal to output the data. When the disk interface control means 12a, 12b, 12c recognize that the BACK signal is active, they indicate that the BREQ signal has been made inactive ("L" level) and that data has been received, in preparation for the transfer of the next data.

On the other hand, the first memory access requesting means 13
When a, 13b, and 13c recognize the deactivation of the BREQ signal, they output the address XADD at which the data to be transferred next on the memory 17 is stored and X
Data is requested by making the REQ signal active. XRE
The memory access control means 16 which recognizes the active state of the Q signal selects an address according to the set priority order, accesses the memory 17, and outputs valid data as X.
It indicates that data is output by outputting to the DAT bus and activating the XACK signal.

Further, the first memory access requesting means 1
When 3a, 13b, 13c recognize that the XACK signal is active, they deactivate the XREQ signal and deactivate the BACK signal, thereby making the disk interface control means 12a, 12b, 1
2c indicates that the next data is ready.

The data stored in the memory 17 in the above sequence is transferred to each disk device 1 via the SCSI bus.
Transfer to 1a, 11b, 11c. Next, the operation of storing the data input to this apparatus in the memory 17 will be described with reference to FIG.

Disk unit 11 via SCSI bus
When data is transferred from a, 11b, and 11c, the disk interface control means 12a, 12b, and 12c are set to B.
It indicates that the received data is output to the DAT bus, the BREQ signal is activated ("H" level), and the data is output to the first memory access requesting means 13a, 13b, 13c. First memory access requesting means 13
When a, 13b, and 13c recognize that the BREQ signal is active, they latch valid data on the BDAT bus and
Data is input by activating the K signal. Disk interface control means 12
When a, 12b, and 12c recognize that the BACK signal is active, they deactivate the BREQ signal ("L" level).
To prepare for the next data transfer.

On the other hand, the first memory access requesting means 13
a, 13b, 13c output the received data on the XDAT bus, output the address on the memory 17 where the next data should be stored to the XADD bus, activate the XREQ signal, and request the data transfer. Memory access control means 16 recognizing the active state of the XREQ signal
Selects an address according to the set priority and X
It shows that the valid data input from the DAT bus is stored in the memory 17, and the data is stored in the memory 17 by activating the XACK signal.

Further, the first memory access requesting means 1
When 3a, 13b, 13c recognize that the XACK signal is active, they deactivate the XREQ signal and deactivate the BACK signal, thereby making the disk interface control means 12a, 12b, 1
2c indicates that the following data can be input.

The data transferred from each disk device 11a, 11b, 11c via the SCSI bus in the above sequence is stored in the memory 17. As described above, referring to FIGS. 2 and 3, the disk devices 11a 1
Although the operation of data transfer from b and 11c to the memory access control means 16 has been described, the data transfer with the host device is similarly performed by the host interface control means 14 and the second memory access control means 15.

Next, each disk device 11a, 11b, 1
The memory access control that enables the parallel operation of 1c will be described. In the present embodiment, a plurality of access requests to the memory 17 are time-divisionally processed to perform parallel processing at a level where there is no operational problem. Further, in this embodiment, an SRAM having an access time of 70 nsec is used as the memory 17, and the first memory access requesting means 13a, 13b,
13c, a configuration in which the memory access is controlled by dividing the cycle into 100-nsec cycles including the time required for the handshake of the access request signal XREQ and the access permission signal XACK from the second memory access request means 15, and performing time division in cycle units. I am trying. When there are a plurality of access requests in the same cycle, the memory access control means 16 selects access to the memory 17 according to the set priority. Data is transferred from the host device and each disk device 11a, 11b, 11c
FIG. 4 is a timing chart for memory access when writing data to the disk device 11a, 11b, 11
FIG. 5 shows a timing chart regarding memory access when data is read from c and transferred to a higher-level device.

In this embodiment, when data is transferred from the host device and written to each disk device 11a, 11b, 11c, the priority of the access request for the host interface is higher than the priority of the access request for the transfer of each disk device. Is set to. With this setting, as shown in FIG. 4, in the cycle in which the access does not conflict, the memory access to the disk device or the host interface that requested the access is performed, and in the cycle in which the access conflicts, the access to the host interface is preferentially performed. The access related to the transfer of the disk device is executed in the next cycle.

On the contrary, the disk devices 11a, 11b, 11
When the data is read from c and transferred to the higher-level device, the priority of the access request for the transfer of each disk device is set higher than the priority of the access request for the host interface. With this setting, as shown in FIG. 5, in the cycle in which the access conflicts, the access related to the transfer of the disk device is given priority, and the access related to the host interface is executed in the next cycle.

Further, in the present embodiment, the data transferred to and from the host device is divided into blocks of 2 KB (2048 bytes), and the data is distributed and stored in each disk device in block units. FIG. 6 shows the relationship between the data transfer with the host device and the data stored in each disk device. Reference numeral 61 in FIG. 6 is host interface control means 1.
4 shows the data transferred between the host device and this device via 4, and 62, 63 and 64 are provided to the respective disk devices 11a, 11b and 11c via the disk interface control means 12a, 12b and 12c. It shows the data to be stored. That is, in this embodiment, the data transferred to and from the host device is transferred to each disk device 11
The data is stored in blocks a, 11b, and 11c in blocks. When transferring data to a higher-level device, the transfer order of the data read from each disk device 11a, 11b, 11c in block units is managed and transferred to the higher-level device.

The apparatus configuration and operation of this embodiment have been described above. Next, the relationship of transfer processing between the host device and each disk device will be described. Each disk device 11a,
FIG. 7 shows the relationship between the transfer processing for 11b and 11c and the transfer processing for the host device. FIG. 7A shows a case where the data transferred from the host device is stored in each disk device.
FIG. 2B shows the case where the data read from each disk device is transferred to the host device, and each data is 2.048 mse.
The blocks to be transferred in the c cycle are shown. Each of the disk devices 11a, 11b, 11c used in this embodiment has a transfer capacity of 1 MByte / sec.
The time required for transfer processing of one block (2048 bytes) is 2.048 msec.
Data for 3 blocks can be transferred within 48 msec.

As shown in FIG. 7, in the present embodiment, the disk drives 11a, 11b, 11c can be operated in parallel by time division processing relating to the memory cycle time.
At the time when each disk device 11a, 11b, 11c performs the transfer processing of one block, the host interface 3
Block transfer processing becomes possible, and 3 of each disk device
Double transfer rate is possible.

Next, a second embodiment of the present invention will be described. In the second embodiment of the present invention, the memory is divided into blocks, and the selection of each block and the management of a transfer block for transferring data in each block are performed by the CPU. FIG. 8 is a block diagram of the data transfer control device of the second embodiment. The configuration is almost the same as that of the first embodiment, but the first memory access requesting means 8
3a, 83b, 83c, and the second memory access requesting means 85 including the I / O port of the CPU 88, the CPU 88 sets the block address of the block to be transferred by each memory access requesting means, and the transfer processing within the block. Is detected by the CPU 88, the CPU 88 manages the selection of each block and the data transfer of each block. In the present embodiment, the memory 87 is an SRAM having a capacity of 32 KB, the capacity of one block is 2 KB, and 16 blocks are provided.

First memory access request means 83a, 8
FIG. 9 shows an internal block configuration diagram common to the third and third memory access requesting means 85. Reference numeral 91 is a sequencer, which is a disk interface control means 82a,
82b and 82c, a handshake using the BREQ signal and the BACK signal with the host interface means 84,
XREQ signal with memory access control means 86, XAC
Handshake using the K signal, clock supply to the counter, and the output XADD [10..0] of the counter are input to determine the end of the transfer processing within the page, and if it is, END the I / O. It has a function to output signals.

Reference numeral 92 denotes a bidirectional data latch, which is disk interface control means 82a, 82b, 82.
c, or latches the data transferred between the host interface means 84 and the memory access control means 86.

Reference numeral 93 is a counter, which counts up according to the clock given from the sequencer 91 and outputs the address XADD [10..0] in the block. Reference numeral 94 denotes an I / O of the CPU 88, an output port of a block address XADD [14..11] for selecting a block, an output port of a START signal for instructing the sequencer 91 to start an operation, and an end of transfer processing in the block. END to read
It consists of a signal input port.

With the above configuration, the first memory access requesting means 83a, 83b, 83c and the second memory access requesting means 85 each have a processing function relating to transfer within a block. Further, the CPU 88 controls the transfer in block units through the input / output ports of the I / O 94 provided in the first memory access requesting means 83a, 83b, 83c and the second memory access requesting means 85.

Next, the CPU relating to the data transfer of this embodiment
The processing of 88 will be described. FIG. 10 shows a flowchart for transferring data from the host device to this device and storing it in each disk device.
FIG. 11 shows a flowchart for transferring data to the host device.

When a data write command is set in this device from the host device via the host interface control means 84, the CPU 88 branches to the subroutine shown in FIG. 10, and first in S101, the host interface control is performed in accordance with the command. Parameters for data transfer are set in the means 84 and the disk interface control means 82a, 82b, 82c.

In S102, the block address on the host interface side is set via the I / O port of the second memory access requesting means 85, and the transfer within the block to the memory 87 is started by the START signal.

In S103, the END signal of the I / O port of the second memory access requesting means 85 is polled to wait for the transfer end of the block set in S102.

When the transfer is completed, the block address to be transferred next is set to the second memory access requesting means 85 in S104, and the transfer in the block is similarly started.

In S105, the block address of the block for which the transfer from the host device has been completed in S103 is set in the first memory access requesting means, and transfer to the disk device is started.

In S106, the second memory access requesting means 85 is polled, and in S107, the END signal of the I / O port of the first memory access requesting means is polled to judge the end of transfer.

When it is judged in S107 that the transfer of the block of the first memory access requesting means is completed, it is judged in S108 whether or not the next block may be transferred to the first memory access requesting means. That is, from the block address currently transferred by the second memory access requesting means, the first
Memory access request means determines whether the data of the block address to be transferred next is already stored in the memory 87. If already stored, the next block can be transferred, and the next transfer is started in S109.
It branches to S106. But if not stored,
Since it is not possible to transfer the next block, S
At 110, the transfer completion of the second memory access requesting means is awaited, at S111, the transfer of the next block is started for the second memory access, and the process similarly branches to S106.

When the transfer of the block of the second memory access requesting means is judged in S106, the process branches to S112 to judge whether or not the data transfer from the host device is completed, and the transfer is not completed. In that case, the process branches to S113.

In S113, it is determined whether the second block may be transferred to the second memory access requesting means. That is, it is determined from the block address currently transferred by the first memory access request means whether or not the data from the higher-level device is overwritten on the block whose transfer has not been completed to the disk device. If not overwritten, the next transfer is started in S114, and S106 is executed.
Branch to. However, if it is overwritten,
In S115, the completion of the transfer of the first memory access requesting means is waited, and in S116, the first memory access requesting means is made to start the transfer of the next block, and similarly S106.
Branch to.

When it is determined in S112 that the transfer from the host device has been completed, S117 to S119
In the step, all the data stored in the memory 87 is stored in the disk device, and the subroutine ends.

When a data read command is set from the host device, the CPU 88 branches to the subroutine shown in FIG. In the subroutine shown in FIG. 11, since the data transfer source is the disk device and the transfer destination is the higher-level device, the positions of the first memory access requesting means and the second memory access requesting means are switched, but FIG.
It performs almost the same processing as the subroutine shown in.

As described above, in the data transfer control device of the present embodiment, the CPU 88 manages the transfer in block units according to the above configuration and the processing contents of the CPU 88. Therefore, for example, waiting for rotation or seek of the head is caused. Then, even if the data transfer does not end within the time expected by the disk device, or if the data transfer takes time due to a problem on the host device side, reliable data transfer control without disturbing the order of data transfer In addition to the above, it is possible to perform high-speed data transfer similar to that of the first embodiment when there is no trouble as described above.

Next, as a third embodiment of the present invention, a data transfer control device capable of limiting the large capacity and the data transfer speed will be described. The configuration of the device of this embodiment is similar to that of the data transfer control device used in the second embodiment, but CP
U88 having a timer function was used. Further, a part of the program executed by the CPU 88 was changed by using the timer function.

FIG. 12 is a flowchart of the changed part.
Shown in. 11A shows S102 of FIG. 10 and S2 of FIG.
It is a flowchart which shows the process which changed 05. S3
In 01, the block address is set to the second memory access requesting means and the transfer operation is started as in S102 and S205. In S302, the operation of the timer for limiting the transfer speed is started. There is. Further, FIG. 10B shows S111 and S114 of FIG. 10 and S2 of FIG.
It is a flowchart which shows the process which changed 09, S216, and S219. In S401, before the transfer of the next block is started, it is judged that the timer has ended with respect to the set value of the timer. If not, the data transfer rate exceeds the required limit. To wait. Then, in S402, the block address is set to the second memory access requesting means, the transfer operation is started, and in S403, similarly to S302, the operation of the timer for limiting the transfer speed of the next block is started. It is a thing. Further, in the present embodiment, the value of the timer for the transfer of each block is set to 1.024 msec so that the data transfer rate to the host device is 2 MByte / sec.

In this embodiment, each disk device 81
FIG. 13 shows the relationship of transfer processing when data is read from a, 81b, and 81c and transferred to the higher-level device. FIG.
As shown in FIG. 2, the process of reading data in block units from each disk device 81a, 81b, 81c is 2.04.
It is completed in 8 msec, but 3 to the host device.
3.072 mse for transfer of block (6144 bytes)
c is required, and a transfer rate of 2 MByte / sec can be realized.

Although three disk devices are used in this embodiment, if the required data transfer speed is lower than that of one disk device, the disk interface control means and the first memory access requesting means are used. Even if a plurality of disk drives are not used, a plurality of disk devices can be connected on the SCSI bus in a daisy chain to achieve the required large capacity. Further, when the required data transfer rate is higher than that of one disk device, the minimum number of disk interface control means capable of realizing a transfer rate higher than the speed required by the parallel operation are provided. The transfer rate can be limited by the timer function using the first memory access requesting means.

Further, in this embodiment, the block capacity is set to 2
Although KByte is used, the present invention is not limited to the capacity of the block, and by making the capacity of the block smaller, the data transfer rate can be more accurately limited.

[0064]

As described above, according to the data transfer control device of the present invention, memory devices are accessed in a time-division manner so that each disk device operates in parallel, and each disk device performs a transfer process of one block. Since the host interface can perform the transfer processing of blocks corresponding to the number of disk devices at the time of performing, it is possible to realize a high-speed data transfer rate proportional to the number of disk devices.

Further, since a large capacity and a high transfer rate are realized and transfer control is performed in block units, for example, due to rotation wait or head seek,
If data transfer does not end within the time expected by each disk device, or if data transfer takes time due to a problem on the host device side, reliable data transfer control can be performed without disturbing the data transfer order. Becomes

Furthermore, by managing the data transfer time to the host device in block units using the timer function, it has become possible to satisfy the large capacity and the required data transfer speed limit.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a data transfer control device according to a first embodiment of the present invention.

FIG. 2 is a timing chart when data is transferred from the memory to the disk device in the data transfer control device according to the first embodiment of the present invention.

FIG. 3 is a timing chart when data is stored in the memory from the disk device in the data transfer control device according to the first embodiment of the present invention.

FIG. 4 is a timing chart regarding memory access when transferring data from a host device to a disk device in the data transfer control device according to the first embodiment of the present invention.

FIG. 5 is a timing chart regarding memory access when transferring data from a disk device to a host device in the data transfer control device according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a relationship between data transferred from a host device and data stored in a disk device in the data transfer control device according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a relationship between a transfer process regarding a disk device and a transfer process between a host device and the data transfer control device according to the first embodiment of the present invention.

FIG. 8 is a block configuration diagram of a data transfer control device according to a second embodiment of the present invention.

FIG. 9 is a block diagram showing the internal structure of a memory access requesting unit in the data transfer control device according to the second embodiment of the present invention.

FIG. 10 is a flowchart for storing data from a host device in the data transfer control device according to the second embodiment of the present invention to a disk device.

FIG. 11 is a flowchart for transferring data from a disk device to a host device in the data transfer control device according to the second embodiment of the present invention.

FIG. 12 is a flowchart showing a main part of processing in the data transfer control device of the third embodiment of the present invention.

FIG. 13 is a diagram showing a relationship of transfer processing between a disk device and a host device in the data transfer control device according to the third embodiment of the present invention.

FIG. 14 is a block diagram showing the configuration of a conventional data transfer control device.

FIG. 15 is a timing chart showing the operation of the conventional data transfer control device.

[Explanation of Codes] 11a, 11b, 11c, 81a, 81b, 81c
Disk device 12a, 12b, 12c, 82a, 82b, 82c
Disk interface control means 13a, 13b, 13c, 83a, 83b, 83c
First memory access requesting means 14, 84 Host interface control means 15, 85 Second memory access requesting means 16, 86 Memory access control means 17, 87 Memory 18, 88 CPU

Claims (3)

[Claims] 1. A plurality of disk devices for transferring data with a host device, a memory for storing data to be transferred between the plurality of disk devices and the host device, and the plurality of disk devices. A disk interface control unit for controlling an interface with the memory unit and outputting a data transfer request signal; and outputting an address signal and an access request signal for the memory according to the data transfer request signal output from the disk interface control unit. No. 1 memory access requesting unit and a host interface controlling unit for controlling an interface with a higher-level device and outputting a data transfer requesting signal, and a memory for the memory according to the data transfer requesting signal output from the host interface controlling unit. Address signal and access request signal Second memory access requesting means for outputting the memory access requesting means and the second memory access requesting means for inputting access request signals and address signals from the second memory access requesting means The input / output of data to / from the requesting means or the second memory access requesting means is controlled, and when there are a plurality of access requests at the same time, the first memory access is performed based on the set priority. A data transfer control device comprising memory access control means for selecting either the request means or the second memory access request means. 2. An address space of a memory is divided into blocks, and the first memory access requesting means and the second memory access requesting means input a data transfer start signal for starting data transfer, Data transfer within a block is performed based on a block address signal to be selected, and a data transfer end signal indicating the end of data transfer within the block is output. A block address signal for selecting the block is generated, The data transfer start signal is output to each of the first memory access requesting unit and the second memory access requesting unit, and the data transfer end signal is output from the first memory access requesting unit and the second memory access requesting unit. Input, and each of the first memory access requesting means and the second memory access requesting means transfers data. The data transfer control device according to claim 1, characterized in that a means for managing the transfer block to perform. 3. The means for managing the transfer block has a timer function, and when the data transfer in the block of the second access requesting means is completed within a preset timer value, the timer value is reached. 3. At that time, a block address indicating a block to be transferred next is output, and a data transfer start signal is output to the second memory access requesting means. Data transfer control device.