JPH07177027A - Phase locked loop circuit device and phase comparator thereof - Google Patents

Abstract

PURPOSE:To shorten phase locking time by supplying a bias voltage to the output terminal of a loop filter before an external clock signal is supplied, and preventing a charge pump circuit from being operated. CONSTITUTION:A bias voltage supply circuit B is provided at the output terminal of the loop filter 3, and when a voltage of low level is supplied to a switch signal 11 before the external clock signal 6 is inputted, voltages in which a power supply voltage is voltage-divided by the on-resistance of transistors(TR) 12, 13 are outputted, which charge the capacitance C of the loop filter 3 in a moment. Thereby, a control voltage added on the input terminal of a voltage controlled oscillation circuit 4 is increased, in a moment, and the oscillation frequency of the circuit 4 can also rise in a short time. After that, an operation is performed by supplying the external clock signal 6. Also, when the bias voltage is supplied, waste current pass can be eliminated by preventing the charge pump circuit 2 from being operated by the input of a control signal 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit device configured as a semiconductor integrated circuit device and a phase comparator thereof.

[0002]

2. Description of the Related Art FIG. 12 shows, for example, the IE Journal of Solid State Circuits (IEEE).
E Journal of Solid-State
Circuits), vol. SC-22, No. Two
FIG. 2 is a block diagram showing a conventional phase locked loop circuit device shown in April 1987 pp 255-261, in which 1 is a phase comparator, which is an external clock signal 6 and a clock driver serving as a reference for phase locking. The rising phases of the internal clock signals 7 given from 5 are compared, and when they are not synchronized, either the up signal U or the down signal D is output.

A charge pump circuit 2 receives the up signal U or the down signal D and outputs positive or negative charges, respectively. A loop filter 3 smoothes and accumulates the output 9 of the charge pump circuit 2. This loop filter 3 has a resistor R
And a capacitance C. Further, 4 is a voltage controlled oscillation circuit, which changes the oscillation frequency according to the output voltage of the loop filter 3 (hereinafter referred to as control voltage). The clock driver 5 generates the oscillation signal 10 output from the voltage controlled oscillation circuit 4 at a desired duty ratio,
Supply inside the integrated circuit.

FIG. 13 shows the relationship of the oscillation frequency with respect to the input voltage of the voltage controlled oscillator circuit 4, FIG. 14 shows a circuit configuration example of the charge pump circuit 2, and FIG. 15 shows a phase locked loop circuit during phase locking. The time change of the oscillation frequency is shown. FIG. 16 is a simple timing chart showing the operation of the phase locked loop circuit device before and after the input of the external clock signal 6. In the figure, a is an external clock signal,
Reference symbol b indicates an internal clock signal, and reference symbol c indicates a control voltage.

Next, the operation will be described. The voltage controlled oscillator circuit 4 outputs signals having different oscillation frequencies according to the control voltage obtained as the output signal of the loop filter 3. Before the external clock signal 6 is input, the phase-locked loop circuit device is in the non-operating state, and the voltage-controlled oscillation circuit 4
Is self-oscillating. As shown in FIG. 13, when the control voltage rises, the oscillation frequency increases, and when the control voltage falls, the oscillation frequency also decreases.

As can be seen from the example of FIG. 13, the oscillation frequency is not proportional to the control voltage in the low and high control voltage regions. In order to obtain the frequency stability of the phase locked loop circuit device, it is required that the control voltage of the voltage controlled oscillator circuit 4 has good linearity with respect to frequency characteristics. Therefore, it is usually designed to oscillate the internal clock signal 7 having a target frequency in a control voltage range in which the oscillation frequency changes substantially linearly, that is, in about 1/2 of the power supply voltage.

The phase comparator 1 compares the phases and frequencies of the external clock signal 6 and the internal clock signal 7 and outputs an up signal U and a down signal D. In this case, the pulse width of the up signal U and the down signal D changes according to the frequency difference or phase difference to be compared.

The charge pump circuit 2 has a circuit configuration as shown in FIG. 14, for example, and receives an up signal U or a down signal D which is an output from the phase comparator 1 and receives a positive or negative signal depending on the pulse width. Is supplied to the loop filter 3.

The loop filter 3 is composed of a resistance R and a capacitance C, and smoothes and outputs the charge supplied from the charge pump circuit 2 by a time constant determined by the resistance R and the capacitance C. Therefore, the control voltage that is the output does not change suddenly but changes gradually.

When the external clock signal 6 is input to the phase locked loop circuit device having such a configuration, the phase comparator 1 compares the frequencies of the external clock signal 6 and the internal clock signal 7. In this case, since the internal clock frequency is lower than the external clock frequency, the up signal is output. In response to this, the charge pump circuit 2 supplies charges to the loop filter 3.

Therefore, the supply of positive charges causes the control voltage to gradually rise. In response to this, the voltage controlled oscillator circuit 4
Gradually raises the oscillation frequency. This state is as shown in FIGS. 15 and 16, and this process is repeated until finally the internal clock signal 7 and the external clock signal 6
The frequencies and phases of are the same.

In this state, the charge pump circuit 2 supplies the loop filter 3 with a very small amount of charge. Furthermore, when this charge amount is integrated by the loop filter 3, the control voltage that is the output becomes almost constant with almost no change. Therefore, the voltage controlled oscillator circuit 4 continues to output the internal clock signal 7 having the same frequency and phase, and maintains the synchronized state.

Next, the circuit configuration of a conventional phase comparator used in a phase locked loop circuit device or the like will be described. FIG. 17 shows, for example, the IE Journal of Solid State Circuits (IEEE J
individual of Solid-State Cir
cits), vol. SC-22, No. February 1
FIG. 21 is a circuit diagram showing a conventional general phase comparator 1 shown in 987 pp 255-261.
26 are 2-input NAND gates as gates, 27 are 4-input NAND gates as gates, 28 and 29 are 3-input NAND gates as gates, and 66 to 69 are inverter circuits.

Input terminals 35 and 36 are connected to one input terminals of the NAND gates 21 and 26, respectively.
An external clock signal 6 and an internal clock signal 7 are provided respectively. Output terminals 37 and 38 are connected to the output terminals of the NAND gates 28 and 29, and an up signal U and a down signal D are applied to these output terminals 37 and 38, respectively, and both are connected to a charge pump circuit (see FIG. Connected (not shown).

According to this, the phase comparator 1 compares the phases of the signals given to the input terminals 35 and 36 and outputs a pulse signal having a pulse width corresponding to the phase difference to the output terminal 37 or 38. To do. The up signal U is output as a pulse signal related to the phase difference when the internal clock signal 7 is delayed, and the down signal D is output when the internal clock signal 7 is advanced.

Inverter circuits 66 to 6 shown in FIG.
In the case of the phase comparator 1 in which 9 is inserted, as the phase difference between the two input clocks approaches, there is a problem that a pulse corresponding to the phase difference does not change from a certain value, that is, a so-called dead zone occurs. there were. Therefore, the phase comparator 1
Regarding the circuit configuration of, it is necessary to devise the circuit so as not to cause a dead zone.

FIG. 18 shows, for example, Japanese Patent Publication No. 58-43932.
FIG. 2 is a circuit diagram showing a phase comparator 1 described in Japanese Patent Laid-Open Publication No. 1-39, in which a dead zone is prevented from occurring. In the figure, 40 is a delay means, and this delay means 40 is an inverter circuit 41-
44, and the other circuit parts are the same as those in FIG.

In this configuration example, the dead zone is eliminated by inserting the delay means 40. The reason will be described below. In FIG. 19, the potential applied to the terminal 35 (that is, the external clock signal 6), the potential applied to the terminal 36 (that is, the internal clock signal 7), and the gates 21, 26, 27, and 2.
It is a timing chart which shows the mutual relation of the electric potential of the output of 8 and 29.

Prior to the explanation of FIG. 19, let us first consider the case where both the external clock signal 6 and the internal clock signal 7 are in the low state. In this case, the gates 21 and 26 always output the high state. Gates 22 and 25
, The output of the gate 27 becomes low, the outputs of the gates 23 and 24 become high, and the outputs of the gates 22 and 25 eventually become low.

Therefore, it is understood that the outputs of the gates 28 and 29 are always in the high state as long as both the external clock signal 6 and the internal clock signal 7 are in the low state. After such a state, if the external clock signal 6 and the internal clock signal 7 turn to the high state, the gates 21 and 26
Goes low and the gates 22 and 25 output a high state.

Thereafter, as shown in FIG. 19, the external clock signal 6 first falls, and then the internal clock signal 7
Will fall with a delay of phase T1. The output of the gate 21 changes to the high state in response to the fall of the external clock signal 6, but the output of the gate 26 remains in the low state because the internal clock signal 7 remains in the high state. Since the output of the gate 27 does not change from the high state, the output of the gate 28 changes to the low state. on the other hand,
The output of gate 29 remains high.

Then, when the internal clock signal 7 falls, the output of the gate 26 changes to the high state, all four inputs of the gate 27 become the high state, and the output of the gate 27 changes to the low state. As a result, the output of the gate 28 changes from the low state to the high state again, and the pulse signal reflecting the phase difference between the external clock signal 6 and the internal clock signal 7 is output.

On the other hand, the output of the gate 29 turns to a low state in response to the output of the gate 26 changing to a high state, but the gate 27 receiving the output of the gate 26 changes its output to a low state. Immediately returns to the high state. Therefore, the output of the gate 29 outputs a pulse signal having a constant width regardless of the phase difference between the external clock signal 6 and the internal clock signal 7.

From the above, the pulse width of the up signal U or the down signal D, which has detected the phase difference, is determined by the gate 21 (or gate 26), the gate 27, the gate 28 (or the gate 29). ) And the delay value of the path from the gate 21 (or gate 26) to the gate 28 (or gate 29) directly, the phase difference T1 between the external clock signal 6 and the internal clock signal 7 is added. It can be seen that the width of the other pulse becomes the value of the difference between the delay values of the two paths.

Therefore, the gate 21 (or the gate 26)
When the delay of the path directly reaching the gate 28 (or the gate 29) is larger than the delay of the path passing through the gate 27, the width of the pulse detecting the phase difference is the phase difference T.
As a result of being smaller than 1, the up signal U (or the down signal D) may not be generated, which is a dead zone.

From this, in the configuration example shown in FIG. 18, the delay means 40 is inserted at the output side of the gate 27 to increase the delay of the path passing through the gate 27 and to generate the dead zone of the phase comparator 1. Is being prevented.

[0027]

Since the conventional phase locked loop circuit device is constructed as described above, the control voltage is, for example, 0 when the external clock signal 6 is not input.
The voltage is as low as V. This is because the phase comparator 1 continues to output the down signal unless the external clock signal 6 is input, so that the charge pump circuit 2 continues to extract the charge from the capacitance C of the loop filter 3 and reduces the control voltage. on the other hand,
The control voltage corresponding to the external clock frequency is, for example, about 1/2 of the power supply voltage as described above.

Therefore, in order to synchronize with the external clock signal 6, it is necessary to change the control voltage from a low voltage to about 1/2 of the power supply voltage, but as described above, the control voltage gradually changes. However, there is a problem that it takes time to reach and converge to the control voltage corresponding to the external clock frequency.

Further, when performing a functional test of the phase-locked loop circuit device, the internal clock signal 7 must first be synchronized with the test clock signal, unlike when testing a circuit without the phase-locked loop circuit device. I won't. It is obvious that the functional test of the phase locked loop circuit device cannot be performed in the period until the internal clock signal 7 is synchronized with the test clock signal, and the external clock pattern must be continuously supplied until the synchronization is achieved. As described above, there is a problem that a long clock pattern is required before the functional test pattern, which causes an increase in the pattern memory as the number of patterns increases.

Further, in the conventional phase comparator 1 in which the generation of the dead zone is prevented, the delay means 40 is composed of an even number of inverter circuits 41 to 44, so that the delay value of the delay means 40 can be arbitrarily adjusted. As a result, the delay difference between the route passing through the gate 27 and the route directly reaching the gate 28 (or the gate 29) may have a large value.

Thus, due to the large delay difference,
The pulse widths of the up signal U and the down signal D are wider than the phase difference of the clocks to be detected, and are output at the same time. Therefore, when applied to the charge pump circuit 2, the amount of charge supplied to the loop filter 3 is increased. Rather, the amount of charge penetrating through the charge pump circuit 2 becomes more dominant,
There is a problem that the input potential of the loop filter 3 is fixed to a potential of about ½ of the power supply voltage and the phase of the clock controlled by the phase locked loop circuit is deviated.

According to the first aspect of the invention, the synchronization time can be shortened by allowing the control voltage to quickly reach the level corresponding to the external clock frequency by the input of the bias voltage before the external clock signal is applied. Another object of the present invention is to obtain a phase-locked loop circuit device capable of efficiently increasing the control voltage by eliminating a wasteful current path in the charge pump circuit when supplying the bias voltage.

According to the second aspect of the present invention, by directly supplying the bias voltage to the capacitance of the loop filter, the phase-locked loop circuit device capable of making the control voltage reach the level corresponding to the external clock frequency more quickly. The purpose is to

According to the invention of claim 3, the operation of the charge pump circuit is forcibly controlled by the low level potential or the high level potential selected by the selector circuit.
An object of the present invention is to obtain a phase-locked loop circuit device that can quickly bring the oscillation frequency of the voltage-controlled oscillator circuit to near the external clock frequency and significantly shorten the period until completion of phase synchronization.

It is an object of the present invention to provide a phase locked loop circuit device capable of preventing the occurrence of a phase dead zone and suppressing the amount of charge penetrating through the charge pump circuit of the next stage.

According to the invention of claim 5, by adjusting the size of the transistor constituting the gate circuit provided on the two output terminal sides, the speed at which the up signal and the down signal transit to the low state or the high state is adjusted. It is an object of the present invention to obtain a phase comparator of a phase locked loop circuit device that can adjust the transition timing without changing.

It is an object of the invention of claim 6 to obtain a phase comparator of a phase locked loop circuit device which can shorten the synchronization time by fixing the input potential of the loop filter to ½ of the power supply voltage. To do.

[0038]

According to another aspect of the present invention, there is provided a phase locked loop circuit device including a bias voltage supply circuit for supplying a bias voltage to an output terminal of a loop filter, and a charge pump circuit for supplying electric charge. The control signal for switching the permission / prohibition can be input.

The phase-locked loop circuit device according to the invention of claim 2 is provided with a bias voltage supply circuit for supplying a bias voltage to the connection point of the resistance and the capacitance forming the loop filter.

A phase locked loop circuit device according to a third aspect of the present invention is provided with a selection circuit for forcibly switching an up signal or a down signal into a charge pump circuit by inputting a selection signal.

According to a fourth aspect of the present invention, the phase comparator detects the phase difference and changes the potential of the output pulse signal,
Two inverter circuits are respectively inserted in series on a pair of transmission paths for transmitting the first change from the change of the input signal, and the delay of each one of the inverter circuits can be set to an arbitrary value. The second capacitance is connected to each of the inverter circuits one by one, and the gate circuit on the transmission path for transmitting the second change of the pulse signal from the change of the input signal is connected to the 2-input NA.
It is composed of a composite gate group consisting of an ND gate, a 2-input NOR gate and an inverter circuit, and a third capacitance of the composite gate group is set so that the delay of one of the composite gate groups can be set to an arbitrary value. It is connected to one.

A phase comparator according to a fifth aspect of the present invention is a phase comparator which allows the delay of one of the pair of inverter circuits and the delay of the composite gate to be arbitrarily selected by changing the gate capacitance by adjusting the transistor size. , Provided on the output terminal side.

According to the sixth aspect of the present invention, in the circuit for comparing and detecting the phase difference between the external clock signal and the internal clock signal, the output of the 4-input NAND gate is directly or by switching the selection signal. It is possible to selectively input to a three-input NAND gate on the output side via a delay means.

[0044]

In the phase locked loop circuit device according to the invention of claim 1, before the external clock signal is applied, a bias voltage is applied to the output terminal of the loop filter, and the charge pump circuit is not operated to lower the bias voltage. And change the control voltage to a desired value more quickly.

In the phase-locked loop circuit device according to the second aspect of the present invention, the bias voltage is applied to the connection point of the resistor and the capacitance forming the loop filter, so that the control voltage can be raised more efficiently and quickly.

According to the third aspect of the present invention, the phase locked loop circuit device forcibly inputs both the up signal and the down signal, which are the outputs of the phase comparator, to the charge pump circuit before applying the external clock signal. The control voltage is quickly changed by.

According to the fourth aspect of the present invention, in the phase comparator, two output pulse signals are inserted in series while the signal change of the one of the two input signals, which is the phase advance, is transmitted to the output terminal. The first potential change of the output pulse signal is delayed by the first or second capacitance, and the first potential change of the output pulse signal is given. The second potential change of the output pulse signal is delayed by the composite gate group and the third capacitance while being transmitted to the input pulse signal, and the width of the output pulse signal is accurately adjusted to the input signal. Equal to the phase difference of.

According to the fifth aspect of the invention, the phase comparator does not change the speed of state transition of the up signal and the down signal by adjusting the size of the transistors forming the gate circuit and the composite gate circuit provided on the output terminal side. Moreover, only the timing of the transition can be adjusted.

In the phase comparator according to the sixth aspect of the invention, by inserting the delay circuit, the pulse width of the up signal and the down signal is widened, and the amount of charge supplied to the loop filter and the amount of charge extracted are both increased to make the loop. The input potential of the filter is changed to about 1/2 of the power supply voltage to shorten the synchronization time of the phase locked loop circuit.

[0050]

【Example】

Embodiment 1 Hereinafter, an embodiment of the invention of claim 1 will be described with reference to the drawings. In FIG. 1, 1 is a phase comparator, 2 is a charge pump circuit, 3 is a loop filter, 4 is a voltage controlled oscillator circuit, and 5 is a clock driver. Reference numeral 6 is an external clock signal supplied from the outside, 7 is an internal clock signal fed back from the inside of the chip, and U and D are an up signal and a down signal output from the phase comparator 1, respectively.

Further, 9 is the output of the charge pump circuit, 1
Reference numeral 0 is an oscillation signal of the voltage controlled oscillation circuit 4, B is a bias voltage supply circuit including a PMOS transistor 12, an NMOS transistor 13, and an inverter circuit 14, 11
Is a switching signal for determining selection / non-selection of the bias voltage supply circuit B, and 15 is an output of the bias voltage supply circuit B, which is connected to the output terminal of the charge pump circuit. The transistor size of each of the transistors 12 and 13 can be optimized according to the target frequency. Reference numeral 16 is a control signal for operating / not operating the charge pump circuit 2.

FIG. 2 is a timing chart showing the phase synchronization of the phase locked loop circuit device before and after the input of the external clock signal 6. In FIG. 2, (a) is the external clock signal and (b) is the internal clock. A signal, (c) shows a control voltage, and (d) shows a switching signal of the bias voltage supply circuit.

Next, the operation will be described. In the phase-locked loop circuit device of this embodiment, the bias voltage supply circuit B is provided at the output end of the loop filter 3, and before inputting the external clock signal 6, as shown in FIG. When a low-level voltage is applied to, a voltage obtained by dividing the power supply voltage by the ON resistances of the transistors 12 and 13 is output, and the capacitance of the loop filter 3 is instantly charged. As a result, the control voltage applied to the input terminal of the voltage controlled oscillator circuit 4 also instantly rises as shown in FIG. The value of this control voltage is close to the control voltage corresponding to the operating frequency or test frequency of this phase locked loop circuit device. Conversely, the sizes of the transistors 12 and 13 in the bias voltage supply circuit B are determined in advance so that the desired voltage level can be obtained. With such a circuit configuration, it is not necessary to prepare a power supply in addition to the power supply voltage.

By adopting such a circuit configuration, the voltage controlled oscillator circuit 4 as shown in FIGS. 2 (a) and 2 (b).
The oscillation frequency of rises to near the frequency corresponding to the operating frequency or the phase convergence at the test frequency in a short time. Thereafter, the switching signal 11 is set to a high level voltage to disconnect it from the loop of the phase locked loop circuit device, and the external clock signal 6 is applied to operate the conventional phase locked loop circuit device.

In the above circuit, the charge pump circuit 2 is still operating even when the output of the bias voltage supply circuit B is applied. As described above, the phase comparator 1 continues to output the down signal D when the external clock signal 6 is not input, and the NMOS transistor S of the charge pump circuit 2 that receives the signal is received.
This is because 2 continues to be on.

That is, when the bias voltage is supplied to the output terminal of the output 9, current may flow through the path on the charge pump circuit 2 side, and the control voltage may not be efficiently increased. Therefore, when the bias voltage is applied, the constant current source circuits 19 and 19 are input by inputting the control signal 16.
Both the PMOS transistor S1 and the NMOS transistor S2 between them are turned off to prevent the charge pump circuit 2 from operating and to eliminate a wasteful current path.

As a result, as shown in FIG. 2, the control voltage C changes faster than in the conventional case. After raising the control voltage C in this way, the control signal 16 is set to a low level voltage,
The switching signal 11 is set to a high level voltage to disconnect it from the loop of the phase locked loop circuit device, and the external clock signal 6 is applied to operate the conventional phase locked loop circuit device. According to this, the control voltage can be raised more quickly.

Example 2. FIG. 4 shows another embodiment of the invention of claim 2, which is different from FIG. 1 in that the bias voltage is supplied to the node 9a connecting the resistor R and the capacitance C forming the loop filter 3, and the charge pump The point is that it has a control signal 16 for operating / non-operating the circuit 2.

According to this embodiment, first, the capacitance C is directly charged with the bias voltage without passing through the resistor R, so that the voltage at the node 9a is increased at a high speed, and the control voltage is increased at a higher speed.

Further, in order to prevent the charge pump circuit 2 from operating when a bias voltage is applied, it is made inactive by a control signal to eliminate a wasteful current path. After efficiently raising the control voltage in this way, the switching signal 11 is set to a high level voltage to disconnect it from the loop of the phase-locked loop circuit device, and the external clock signal 6 is supplied to the conventional phase-locked loop circuit device. Take action. As a result, the control voltage can be raised more quickly and the synchronization time can be significantly shortened.

Example 3. FIG. 5 shows an embodiment of the invention of claim 3 in which selector circuits 17a and 17b are provided between the phase comparator 1 and the charge pump circuit 2.

Up signal U output from the phase comparator 1
And down signal D to selector circuits 17a and 1a, respectively.
One input of 7b and the other input are set so that the up signal U and the down signal D are forcibly input to the charge pump circuit 2, respectively. Then, the outputs of the selector circuits 17a and 17b are input to the charge pump circuit 2. For example, the charge pump circuit 2 having the configuration shown in FIG.
Then, when the up signal U is at the low level, electric charges are supplied to the loop filter 3 to increase the voltage of the output 9, but when the up signal U is at the high level, the operation is not performed. When the down signal D is high level, the loop filter 3
Although the electric charge is extracted from the output to reduce the voltage of the output 9, the operation is not performed at the low level. In this case, the signal entering the selector circuit 17a together with the up signal U is the ground potential 20 which is a low level voltage, and the signal entering the selector circuit 17b together with the down signal D is the voltage of the voltage supply source 30 which is a high level voltage. Set. Reference numeral 18 is a selection signal, which is two selector circuits 17a and 17b.
Connected to select the input signal.

FIG. 6 shows the selector circuit 17a shown in FIG.
FIG. 17 is a circuit diagram showing details of 17b, which are composed of inverters 71 and 72, AND gates 73 to 76, and OR gates 77 and 78.

Next, the operation will be described. Before the external clock signal 6 is applied, the selection signal 18 is forcibly set to a state in which the up signal U and the down signal D are continuously output, that is, a high level voltage. As a result, the selector circuit 1
The output signal U2 of 7a shows a low level voltage, the output signal D2 shows a high level voltage, and the control voltage of the output 9 instantly rises to a voltage determined by the on-resistance ratio of the transistors forming the charge pump circuit 2, Along with this, the oscillation frequency of the voltage controlled oscillator circuit 4 also increases to near the target frequency.

The value of the control voltage is, for example, the PMOS of FIG.
If the ON resistances of the transistor and the NMOS transistor are equal, the voltage will be half the power supply voltage. After an appropriate period, the selection signal 18 is switched to the normal operation state, and the external clock signal 6 is input to operate the phase locked loop circuit device. At this time, the oscillation frequency has already reached the vicinity of the external clock frequency, and the operation during the period marked with * in FIG. 15 does not have to be performed, so the period required to complete the phase synchronization is greatly shortened. .

Example 4. FIG. 7 is a circuit diagram of a phase comparator showing an embodiment of the invention of claim 4, and in FIG.
1, 52 are 2-input NAND gates, 53 is 2-input NOR gate
Gates 54 to 58 are inverter circuits and have 2 inputs N
A gate circuit 27A including AND gates 51 and 52, a 2-input NOR gate 53, and an inverter circuit 54 corresponds to the 4-input NAND gate 27 shown in FIG. 61
˜63 is a capacitance, and 20 is a ground potential. Note that the other parts are the same as those in FIG. 17, and thus duplicated description thereof will be omitted.

In this embodiment, the gate 2 of the conventional example is used.
Inverter circuits 55 and 56 are provided on the path directly from 1 to the gate 28 and the path directly from the gate 26 to the gate 29.
And 57, 58 are inserted, and the capacitance 61, 57 is added to the output side of the inverter circuits 55, 57.
By connecting 62 and changing the capacitance value, gate 2
The delay of the path from 1 to the gate 28 and the path from the gate 26 to the gate 29 is adjusted to a desired value, and
The time at which the output potentials of the gate 28 and the gate 29 described in 1) are changed to the low state is set.

Next, the path from the gate 21 (or gate 26) in the conventional example to the gate 28 (or gate 29) via the 4-input NAND gate 27 is shown in FIG.
8 input NAND gate 27 and delay means 40, instead of 2 input NAND gates 51, 52, 2 input NO
A gate circuit 27A of a composite gate group including an R gate 53 and an inverter circuit 54 is connected, and a 2-input NO of these is connected.
By connecting a capacitance 63 to the output side of the R gate 53 and changing this capacitance value, the delay of the path from the gate 21 (or gate 26) to the gate 28 (or gate 29) via the gate circuit 27A is reduced. , Gate 21 to gate 2
8 and the delay value of the route from the gate 26 to the gate 29 are adjusted to values different from each other to set the time for the output potentials of the gate 28 and the gate 29 described in FIG. 19 to transit to the high state again. ing.

Therefore, according to the present invention, it is possible to make the pulse width of the output up signal U or the down signal D whose phase difference is detected exactly equal to the phase difference between the input signals. Moreover, since the pulse width of the side where the phase difference is not detected can be adjusted to an extremely narrow width, the dead zone of the phase comparator 1 is prevented from occurring and the inside of the charge pump circuit 2 of the next stage is penetrated. The amount of electric charge generated can be suppressed to a negligible amount.

Furthermore, the 4-input N used in the conventional example
Since the AND gate 27 has four NMOSs connected in series, there is a problem that the delay value greatly differs between the four inputs as the power supply voltage decreases. However, in this embodiment, the two-input NAND gates 51 and 52 are provided. , A two-input NOR gate 53, and an inverter circuit 54 are used as a composite gate group, so that it is possible to expect an effect that the difference between the delay from the gate 21 and the delay from the gate 26 is not different even under a low voltage. .

In FIG. 7, the capacitance 61 is on the output side of the inverter circuit 55, the capacitance 62 is on the output side of the inverter circuit 57, and the capacitance 63 is two.
Although the case where the capacitors are connected to the output side of the input NOR gate 53 is shown, the capacitance 61 is connected to the inverter circuit 5.
A capacitance 62 is provided on the output side of the inverter circuit 5
A capacitance 63 is provided on the output side of the inverter circuit 5
4 may be connected to the output side, and the capacitance 63
May be divided into two and connected to the output sides of the two-input NAND gates 51 and 52, respectively.

Example 5. Further, in the configuration of FIG. 7, the outputs of the 2-input NAND gates 21 and 22 are connected to the input side of the 2-input NAND gate 51, and the 2-input NAND gate 25,
Although the case where the output of 26 is connected to the input side of the 2-input NAND gate 52 is shown, the 2-input NAND gates 22 and 25 are connected.
You may change the connection of. This case will be described with reference to FIG. In this embodiment, the two-input NAND gates 51 and 5 are used.
Two-input NAND gates 59 and 60 correspond to 2, and other parts are the same as those in FIG.

In this embodiment, the 2-input NAND gate 59 is always placed on the path for transitioning the up signal U and the down signal D to the high state again in response to the change of the input signal. Does not matter. Therefore, the capacitance 63 that adjusts the delay of this path is
Output side of 2-input NOR gate 53, inverter circuit 54
May be connected not only to the output side of the above, but also to the output side of the 2-input NAND gate 59.

Since the delay of the 2-input NAND gate 60 is not fixed, the size of the transistors forming the 2-input NAND gate 60 and the 2-input NAND gate 60 are not limited.
NMO of 2-input NOR gate 53 connected to the output of
The size of S can be reduced.

Example 6. In the embodiment shown in FIG. 7, capacitances 61, 62 for adjusting the delay are provided inside the circuit.
Although the case where 63 is provided is shown, these capacitances 61, 62, 63 may be the input capacitances of the next stage.
An example of such a configuration will be described below.

FIG. 9 is a circuit diagram showing a phase comparator according to an embodiment of the invention of claim 5, and 201 to 208 in the figure.
Is a PMOS transistor, 211 to 218 are NMOS transistors, and 30 is a voltage supply source, and these constitute gate circuits 28A and 29A, respectively, and shown in FIG.
It corresponds to the input NAND gates 28 and 29. In addition,
The other parts are the same as those in FIG. 7, and the duplicated description is omitted here.

In the configuration example of FIG. 9, the gate circuits 28A, 2A
Inside the 9A circuit, PMOS transistors 202, 20
6, NMOS transistors 213 and 217 are added. Of these, the gate capacitance of the PMOS transistor 202 is the capacitance 61 of FIG. 7, and the gate capacitance of the PMOS transistor 206 is the capacitance 62 of FIG.
The gate capacitances of the MOS transistors 213 and 217 correspond to the capacitance 63 of FIG. 7, respectively.
The reason for this will be described below.

Inside the gate circuits 28A, 29A, the PMOS transistors 201, 202, 20 are received in response to the inverter circuits 56, 58 changing to the high state.
5,206 off, NMOS transistors 211,21
As a result of 5 being turned on, the potentials of the up signal U and the down signal D transit to the low state, and then the inverter circuit 54 changes to the low state.
2, 213, 216, and 217 are turned off, and the PMOS transistors 203 and 207 are turned on. As a result, the potentials of the up signal U and the down signal D transit to the high state again.

Therefore, the speed at which the potentials of the up signal U and the down signal D transit is determined by the NMOS transistors 211 and 211.
15 and the amount of current charged and discharged in the PMOS transistors 203 and 207.
1, 202, 205, 206, NMOS transistor 2
It has little relation to the amount of current charged and discharged by 12, 213, 216, and 217.

On the other hand, the delay when the inverter circuit 56 changes to the high state is the PMOS transistors 201 and 20.
2. The delay when the gate capacitance of the NMOS transistor 211 is charged / discharged and the inverter circuit 58 changes to the high state is delayed by the PMOS transistor 205,
206, it depends on the time for charging / discharging the gate capacitance of the NMOS transistor 215.

Therefore, the capacitance 61 shown in FIG.
PMOS transistor 2 with a gate capacitance equivalent to
02, even if a PMOS transistor 206 having a gate capacitance corresponding to the capacitance 62 is added and the transistor size is changed, the speed at which the up signal U and the down signal D transit to the low state is not changed, Only the timing of transition to the low state can be adjusted.

Similarly, the delay when the inverter circuit 54 changes to the high state depends on the PMOS transistors 203 and 2.
07, NMOS transistors 212, 213, 216,
Since it depends on the time for charging / discharging the gate capacitance of 217, if NMOS transistors 213 and 217 having a gate capacitance equivalent to half the capacitance 63 shown in FIG. 7 are added and the size of these transistors is changed, It is possible to adjust only the timing of the transition to the high state again without changing the speed at which the up signal U and the down signal D transit to the high state.

In the example of FIG. 9, PMOS transistors 201 and 202 and PMOS transistors 205 and 20 are used.
6, the NMOS transistors 212 and 213, and the NMOS transistors 216 and 217 are separately connected in parallel, but they are each configured by one transistor, and the same size adjustment is performed. You can expect an effect.

Example 7. FIG. 10 is a circuit diagram of a phase comparator showing an embodiment of the invention of claim 6, and in FIG.
Reference numeral 0 is a delay means, 18 is a selection signal, and 117 is a selector circuit. Since the other parts are the same as those in FIG. 18, the duplicated description will be omitted.

FIG. 10 shows a 4-input NAND circuit used as the phase comparator 1 of the circuit shown in FIG. 12 in order to reduce the synchronization time of the phase-locked loop circuit device.
The delay means 40 is connected to the output of the gate 27,
The output of the 4-input NAND gate 27 and the output via the delay means 40 can be selected by the selector circuit 117. By switching the potential of the selection signal 18 during the test, the 4-input NAND gate 27
Is transmitted to the 3-input NAND gates 28 and 29 via the delay means 40.

The operation of the circuit of FIG. 10 is similar to the operation described with reference to FIG. That is, the insertion of the delay means 40 delays the timing at which the up signal U and the down signal D rise from the low state to the high state, and the pulse widths of the up signal U and the down signal D become wider.

Therefore, if the delay value of the delay means 40 is set to a sufficiently large value, both pulse widths become significantly wider than the phase difference to be detected in the asynchronous state. Therefore, when applied to the charge pump circuit 2, In addition, the period for penetrating the inside of the charge pump circuit 2 becomes longer, and the input potential of the loop filter 3 is fixed to a potential of about ½ of the power supply voltage.

After the potential of about 1/2 of the power supply voltage is accumulated in the capacitance C of the loop filter 3, the selection signal 18 is switched so as not to pass through the delay means 40, and the phase locked loop circuit outputs it. It does not disturb the operation of the clock.

In the circuit configuration of FIG. 10, if the frequencies of the external clock signal 6 and the internal clock signal 7 are different, the phase difference between the two may be greatly different, and as a result of this difference being added to the width of the output pulse, The pulse widths of the up signal U and the down signal D when the delay means 40 is inserted are not the same.

FIG. 11 shows an example in which this point is improved. In this configuration example, a selector circuit 118 similar to the above selector circuit 117 is connected to the input terminal 36 to interlock with the selection signal 18, the internal clock signal 7 is supplied to the gate 26 during normal operation, and the external clock signal is supplied during testing. The clock signal 6 is supplied to the gate 26.

According to this, since the input phase difference between the gates 21 and 26 when the delay means 40 is inserted becomes almost 0, the pulse widths of the up signal U and the down signal D at this time have the same value, Even though the external clock signal 6 and the internal clock signal 7 are asynchronous, the input potential of the loop filter can be accurately fixed to 1/2 the power supply voltage.

[0092]

As described above, according to the invention of claim 1, the bias voltage supply circuit for supplying the bias voltage to the output end of the loop filter is provided, and the charge pump circuit is controlled to switch the supply or non-supply of the charge. Since the signal can be input, there is an effect that a useless current path in the charge pump circuit at the time of supplying the bias voltage is eliminated and the control voltage can be efficiently increased.

According to the second aspect of the invention, since the bias voltage supply circuit for supplying the bias voltage is provided at the connection point of the resistance and the capacitance forming the loop filter, the bias voltage is directly applied to the capacitance of the loop filter. By supplying the voltage, it is possible to obtain the voltage that allows the control voltage to reach the level corresponding to the external clock frequency more quickly.

According to the third aspect of the invention, since the selection circuit forcibly switching the up signal or the down signal into the charge pump circuit by the input of the selection signal is provided, the low level selected by the selector circuit is provided. By forcibly controlling the operation of the charge pump circuit by the potential of the voltage or the high level potential, the oscillation frequency of the voltage controlled oscillation circuit is quickly reached near the external clock frequency, and the period until the completion of phase synchronization is significantly increased. There is an effect that what can be shortened is obtained.

According to the fourth aspect of the present invention, in the potential change of the pulse signal which is detected and the phase difference is output, two inverter circuits are provided on each of the pair of transmission paths for transmitting the first change from the change of the input signal. The first and second capacitances are connected in series to each of the inverter circuits so that the delay of each of the inverter circuits can be set to an arbitrary value, and the pulse of The gate circuit on the transmission path for transmitting the second change of the signal from the change of the input signal is composed of a composite gate group including a 2-input NAND gate, a 2-input NOR gate, and an inverter circuit, and of the composite gate group, Since the third capacitance is connected to one of the composite gate groups so that one delay can be set to an arbitrary value, there is no phase difference. Thereby preventing the occurrence of band, there is an effect that can be obtained which can suppress the amount of charge through the interior next stage of the charge pump circuit.

According to the invention of claim 5, the delay of one of the pair of inverter circuits and the delay of the composite gate are
Since the gate circuit that allows arbitrary selection according to the change in the gate capacitance due to the adjustment of the transistor size is provided on the output terminal side, the sizes of the transistors that form the gate circuits provided on the two output terminal sides are adjusted. As a result, there is an effect that it is possible to adjust the transition timing of the up signal and the down signal without changing the transition speed to the low state or the high state.

According to the invention of claim 6, in the circuit for comparing and detecting the phase difference between the external clock signal and the internal clock signal, the 4-input NAND is selected by switching the selection signal.
Since the output of the gate can be selectively input to the 3-input NAND gate on the output side directly or via the delay means, the input potential of the loop filter is fixed to ½ of the power supply voltage to achieve synchronization. There is an effect that what can be shortened is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a phase-locked loop circuit device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing signals of respective parts of the block of FIG.

FIG. 3 is a circuit diagram showing details of a charge pump circuit in FIG.

FIG. 4 is a block diagram showing a phase locked loop circuit device according to an embodiment of the present invention.

FIG. 5 is a block diagram showing a phase locked loop circuit device according to an embodiment of the invention of claim 3;

6 is a circuit diagram showing details of a selector circuit of FIG.

FIG. 7 is a circuit diagram showing a phase comparator according to an embodiment of the present invention.

FIG. 8 is a circuit diagram showing a phase comparator according to another embodiment of the invention of claim 4;

FIG. 9 is a circuit diagram showing a phase comparator according to an embodiment of the invention of claim 5;

FIG. 10 is a circuit diagram showing a phase comparator according to an embodiment of the invention of claim 6;

FIG. 11 is a circuit diagram showing a phase comparator according to another embodiment of the invention of claim 6;

FIG. 12 is a block diagram showing a conventional phase locked loop circuit device.

13 is a gain characteristic diagram showing a gain characteristic of the voltage controlled oscillator circuit in FIG.

FIG. 14 is a circuit diagram showing details of the charge pump circuit in FIG.

FIG. 15 is a circuit diagram showing a time change of an oscillation frequency during phase synchronization.

16 is a timing chart showing signals of respective parts of the block of FIG.

FIG. 17 is a circuit diagram showing a conventional phase comparator.

FIG. 18 is a circuit diagram showing another conventional example of the phase comparator.

19 is a timing chart showing signals of various parts of the circuit of FIG.

[Explanation of symbols]

1 Phase Comparator 2 Charge Pump Circuit 3 Loop Filter 4 Voltage Control Oscillation Circuit 6 External Clock Signal 7 Internal Clock Signal U Up Signal D Down Signal R Resistance C Capacitance B Bias Voltage Supply Circuit 16 Control Signal 17a, 17b, 117 Selector Circuit 18 Selection signal 35, 36 Input terminal 37, 38 Output terminal 40 Delay means 54-58, 41-44 Inverter circuit 21-26, 51, 52, 59, 60 2-input NAND
Gate 53 2-input NOR gate 28,29 3-input NAND gate 27 4-input NAND gate 61-63 capacitance 201-208 PMOS transistor (transistor) 211-218 NMOS transistor (transistor) 27A, 27B, 28A, 29A Gate circuit

Claims (6)

[Claims] 1. A loop filter comprising a resistor and a capacitance, a voltage controlled oscillator circuit for generating an internal clock signal for internal synchronization in response to an output of the loop filter, an external clock signal and the voltage controlled oscillator circuit. Corresponding to the comparison result by the phase comparator for detecting and comparing the phase difference with the internal clock signal of, usually, the charge is supplied to the loop filter or the charge is extracted from the loop filter, A charge pump circuit for stopping the supply and extraction of electric charges by switching input of the control signal, and a bias voltage supply circuit for supplying a bias voltage of a set level to the loop filter before the external clock signal is applied. Phase locked loop circuit device. 2. The phase-locked loop circuit device according to claim 1, wherein a bias voltage supply circuit for supplying a bias voltage is connected to a connection point between the resistance and the capacitance forming the loop filter. 3. A loop filter comprising a resistor and a capacitance, a voltage controlled oscillator circuit for generating an internal clock signal for internal synchronization in response to an output of the loop filter, an external clock signal and the voltage controlled oscillator circuit. Output a signal corresponding to the comparison result by the phase comparator, which detects and compares the phase difference with the internal clock signal, while comparing the phase difference by switching input of the selection signal from the outside. And a charge pump circuit for supplying an electric charge to the loop filter or for extracting an electric charge from the loop filter according to the output result of the selector circuit. A phase-locked loop circuit device equipped with. 4. Two input terminals for inputting an external clock signal and an internal clock signal, and a phase difference between the input terminals are detected to supply an electric charge to a loop filter or extract an electric charge from the loop filter. In a phase comparator of a phase locked loop circuit device having two output terminals for outputting a pulse signal for controlling a charge pump circuit, a pair of transmissions for transmitting the first potential change of the pulse signal from the change of the input signal. On the path, two inverter circuits are inserted in series, and the delay of one of the pair of inverter circuits can be set to an arbitrary value.
One of each of the inverter circuits inserted in series is connected to the output side of one of the inverter circuits.
And a second capacitance, and two 2-input N provided on a transmission path for transmitting the second potential change of the pulse signal from the change of the input signal.
4 composed of a composite gate consisting of an AND gate, one 2-input NOR gate and one inverter circuit
In order to set the delay of the input gate circuit and the composite gate to an arbitrary value, the 2-input NAND gate, 2
A phase comparator for a phase-locked loop circuit device, comprising a third capacitance connected to any one of an input NOR gate and an inverter circuit. 5. An input terminal for inputting an external clock signal and an internal clock signal, and a phase difference between the input terminals are detected to supply an electric charge to a loop filter or extract an electric charge from the loop filter. In a phase comparator of a phase locked loop circuit device having two output terminals for outputting a pulse signal for controlling a charge pump circuit, a pair of transmissions for transmitting the first potential change of the pulse signal from the change of the input signal. Two 2-input NAND gates are provided on the path, and two 2-input NAND gates are provided on each of the inverter circuits inserted in series and on the transfer path for transmitting the second potential change of the pulse signal from the change of the input signal. , 1
A four-input gate circuit composed of a composite gate composed of two 2-input NOR gates and one inverter circuit, a delay of one of the pair of inverter circuits and a delay of the composite gate are provided in the gate of the next stage. ,
A phase comparator of a phase-locked loop circuit device, comprising: a gate circuit that can be arbitrarily adjusted by changing a gate capacitance by adjusting a transistor size on a side that changes to an off state upon receiving a potential change. 6. Two input terminals for inputting an external clock signal and an internal clock signal and a phase difference between the input terminals are detected to supply an electric charge to a loop filter or extract an electric charge from the loop filter. In a phase comparator of a phase-locked loop circuit device having two output terminals for outputting a pulse signal for controlling a charge pump circuit, a pair of first electric potentials for transmitting a first potential change of the pulse signal from a change of an input signal. A single 3-input NAND gate connected via a transmission path, and a 4-input NAND gate connected via a second transmission path for transmitting the second potential change of the pulse signal from the change of the input signal. , The 4
It is connected to the input NAND gate directly and via a delay means composed of a plurality of inverter circuits, and when the selection signal is input from the outside, the output of the 4-input NAND gate or the output thereof is output through the delay means. And a selector circuit for selectively inputting to each of the three-input NAND gates.