JPH07176997A - Schmitt trigger circuit - Google Patents

Abstract

PURPOSE:To improve the resistance to electrostatic destruction while an equal characteristic of a conventional Schmidt trigger circuit is kept in the circuit operation by providing a 4th P-channel MOS transistor(TR) between a 3rd N-channel MOS TR and a power supply potential point. CONSTITUTION:A P-channel MOS TR 31 is arranged between an N-channel MOS TR 16 and a power supply potential point VDD in this Schmidt trigger circuit. A gate of the P-channel MOS TR 31 connects to ground via a resistor 32. The forming of a parasitic TR in a conventional circuit is prevented through the arrangement of the P-channel MOS TR 31. Thus, the resistance to electrostatic destruction is improved. Since the gate of the P-channel MOS TR 31 is set to a ground potential, a power supply potential VDD is applied to the N-channel MOS TR 16 and the the same characteristic as that of a conventional Schmidt trigger circuit is kept in the circuit operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Schmitt trigger circuit using a MOS transistor.

[0002]

2. Description of the Related Art A Schmitt trigger circuit using a MOS transistor also has various configurations, one of which is proposed in Japanese Patent Publication No. 59-1005. FIG. 4 is a circuit diagram of the Schmitt trigger circuit proposed in this publication. Assuming that the input IN is at the “L” level, the node N is at the “H” level and the output OUT
Is at the'L 'level because the logic of the node N is inverted by the inverter 10.

At this time, the two P-channel MOS transistors 11 and 12 are in the ON state because the input IN is "L", and the P-channel MOS transistor 13 is in the ON state.
Is off because node N is'H '. The two N-channel MOS transistors 14 and 15 are
Since the input IN is'L ', it is in the off state, and the N-channel MOS transistor 16 is in the on state, because the node N is'H'.

Here, when the input IN gradually shifts to the "H" level, first the N-channel MOS transistor 15
Starts to turn on and the N-channel MOS transistor 16 is in the on-state, so that the power supply V _DD → N-channel M
A current starts to flow through the path of OS transistor 16 → N-channel MOS transistor 15 → ground GND. The N-channel MOS transistor 15 is still in the initial stage when the N-channel MOS transistor 15 starts to turn on.
Has a large resistance, the potential at the connection point between the N-channel MOS transistor 15 and the N-channel MOS transistor 16 is high. When the input IN further goes to the “H” side, N
The resistance of the channel MOS transistor 15 is lowered,
N-channel MOS transistor 15 and N-channel M
The potential of the connection point with the OS transistor 16 decreases. Input I
When N further rises, the N-channel MOS transistor 14 is turned on this time. Then, the charges charged in the node N are transferred to the N-channel MOS transistor 1
It flows via the 4 → N channel MOS transistor 15, and the potential of the node N suddenly becomes the “L” level. In this way, a rapid signal inversion occurs. The same applies when the input IN shifts from the “H” level to the “L” level. In this case, the P-channel MOS transistor 1
1, 12, 13 are N-channel MOS transistors 1
4, 15 and 16 play the above-mentioned roles.

[0005]

In the Schmitt trigger circuit shown in FIG. 4, the N-channel MOS transistor 16 is used.
The source is connected to the power supply V _DD, while the source is the ground GND of the N-channel MOS transistor 15 of the
It is connected to the. Moreover, since these two N-channel MOS transistors 15 and 16 are connected to each other, they are often arranged close to each other in layout.
At this time, as indicated by the broken line in FIG.
There may be a parasitic NPN transistor 20 in which the source of the OS transistor 16 is the collector, the source of the N-channel MOS transistor 15 is the emitter, and the P-type well in the middle is the base. At this time, when noise such as static electricity is applied between the power supply V _DD and the ground GND, the NPN transistor 20 is turned on, and a large current flows through the NPN transistor 20, which may melt the wiring or destroy the PN junction. There is.

On the other hand, in order to avoid this, N channel M
If an attempt is made to increase the distance between the sources of the OS transistors 15 and 16, a large area will be occupied when the Schmitt trigger circuit is built.
Incidentally, here, the N-channel MOS transistor 15,
16 has been described, the same applies to the P-channel MOS transistors 11 and 13, and between them, as shown in FIG.
In some cases, a parasitic PNP transistor 21 indicated by a broken line may be formed, which causes the same problem as described above.

In view of the above circumstances, it is an object of the present invention to provide a Schmitt trigger circuit in which formation of a parasitic transistor as shown in the Schmitt trigger circuit of FIG. 4 is prevented.

[0008]

A first Schmitt trigger circuit of the present invention for achieving the above object is a parasitic transistor 2 on the N-channel MOS transistor 16 side shown in FIG.
0 is prevented from being formed, and (1_1) each gate is connected to a common signal input terminal and is connected in series between a power supply potential and a ground potential,
A first P-channel MOS transistor, a second P-channel MOS transistor, a first P-channel MOS transistor, and a first P-channel MOS transistor in order from the power supply potential side.
N-channel MOS transistor and second N-channel MOS transistor (1_2) connected between the first connection point between the first P-channel MOS transistor and the second P-channel MOS transistor and the ground potential. The gate of the second P-channel MOS transistor and the first N-channel
A third P-channel MOS transistor (1_3) connected to a second connection point with the channel MOS transistor, and a third connection point between the first N-channel MOS transistor and the second N-channel MOS transistor, A third N-channel MOS transistor having a gate connected to the second connection point, which is connected in series with the power supply potential in series from the third connection point side, and the gate is grounded directly or via an impedance element A fourth P-channel MOS transistor connected to the electric potential is provided.

A second Schmitt trigger circuit of the present invention which achieves the above object is a P channel MO shown in FIG.
The formation of the parasitic transistor 21 on the side of the S-transistor 13 is prevented, and (2_1) each gate is connected to the common signal input terminal and is connected in series between the power supply potential and the ground potential.
A first P-channel MOS transistor, a second P-channel MOS transistor, a first P-channel MOS transistor, and a first P-channel MOS transistor in order from the power supply potential side.
N-channel MOS transistor and second N-channel MOS transistor (2_2) Series connection between the first connection point between the first P-channel MOS transistor and the second P-channel MOS transistor and the ground potential And a third P-channel MOS transistor whose gate is connected to a second connection point between the second P-channel MOS transistor and the first N-channel MOS transistor in this order from the first connection point side, Third N-channel MOS transistor whose gate is connected to the power supply potential directly or via an impedance element (2_3) A third connection point between the first N-channel MOS transistor and the second N-channel MOS transistor , Connected to the power supply potential and the gate connected to the second connection point The fourth N-channel MOS
It is characterized by having a transistor.

Further, a third Schmitt trigger circuit of the present invention is an N-channel MOS transistor 1 shown in FIG.
It is intended to prevent the formation of both the 6-side parasitic transistor 20 and the P-channel MOS transistor 13-side parasitic transistor 21. (3_1) Each gate is connected to a common signal input terminal and the power supply potential is increased. Connected in series between the
A first P-channel MOS transistor, a second P-channel MOS transistor, a first P-channel MOS transistor, and a first P-channel MOS transistor in order from the power supply potential side.
N-channel MOS transistor and second N-channel MOS transistor (3_2) Series connection between the first connection point between the first P-channel MOS transistor and the second P-channel MOS transistor and the ground potential And a third P-channel MO whose gate is connected to a second connection point between the second P-channel MOS transistor and the first N-channel MOS transistor in this order from the first connection point side.
A third N-channel MOS transistor whose gate is connected to the power source potential directly or via an impedance element (3_3) between the first N-channel MOS transistor and the second N-channel MOS transistor. A fourth N-channel MOS transistor having a gate connected to the second connection point, which is connected in series between the three connection points and the power supply potential, in order from the third connection point side, and a gate directly or with an impedance element. Fourth connected to ground potential via
The P-channel MOS transistor is included.

[0011]

The parasitic transistor 20 shown in FIG. 4 is formed because the N-channel MOS transistor 16 is connected to the power supply potential, and the parasitic transistor 21 is because the P-channel MOS transistor 13 is connected to the ground potential. Is formed.

Therefore, the first Schmitt trigger circuit of the present invention includes the third N-channel MOS transistor (N-channel MOS transistor shown in FIG. 4) described in (1_3) above.
Between the transistor 16) and the power supply potential, the above (1_
Since the fourth P-channel MOS transistor described in 3) is provided, the parasitic transistor 20 shown in FIG. 4 is not formed. In addition, since the gate of the fourth P-channel MOS transistor is connected to the ground potential, the power supply voltage passes through the fourth P-channel MOS transistor to the third N-channel MOS transistor (see FIG. 4). The characteristic as a Schmitt trigger circuit is transmitted to the N-channel MOS transistor 16) shown, and the characteristics as a Schmitt trigger circuit are maintained as usual.

The second Schmitt trigger circuit of the present invention is the third P-channel M described in (2_2) above.
Between the OS transistor ((P-channel MOS transistor 13 shown in FIG. 4) and the ground potential, the above (2_2)
Since the parasitic transistor 21 shown in FIG. 4 is not formed because the third N-channel MOS transistor described in 1. is provided, and the gate of the third N-channel MOS transistor is connected to the power supply potential, the Schmitt trigger The characteristics of the circuit are maintained as they were in the past, and since the electrostatic breakdown voltage is improved, the Schmitt trigger circuit becomes excellent.

Furthermore, since the third Schmitt trigger circuit of the present invention has the features of both the first and second Schmitt trigger circuits, the formation of both parasitic transistors 20 and 21 shown in FIG. Therefore, the electrostatic breakdown withstand voltage is further improved, and the characteristics of the Schmitt trigger circuit are maintained as before.

[0015]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a circuit diagram of an embodiment of the first Schmitt trigger circuit of the present invention. The same components as those of the conventional Schmitt trigger circuit shown in FIG. 4 are designated by the same reference numerals as those shown in FIG. 4, and only the differences will be described.

The Schmitt trigger circuit shown in FIG.
A P-channel MOS transistor 31 is arranged between the channel MOS transistor 16 and the power supply potential V _DD . The gate of the P-channel MOS transistor 31 is grounded via the resistor 32. By arranging this P-channel MOS transistor 31,
The formation of the parasitic transistor 20 shown in FIG. Therefore, the electrostatic breakdown voltage is improved. Since the gate of the P-channel MOS transistor 31 is kept at the ground potential, the power supply voltage V _DD is applied to the N-channel MOS transistor 16, and therefore, in terms of circuit operation, the characteristics of the conventional Schmitt trigger circuit shown in FIG. Equivalent properties are retained.

FIG. 2 is a circuit diagram of an embodiment of the second Schmitt trigger circuit of the present invention. Similar to the case of FIG. 1, the same components as those of the conventional Schmitt trigger circuit shown in FIG. 4 are designated by the same reference numerals as those of FIG. 4, and only different points will be described. . The Schmitt trigger circuit shown in FIG. 2 includes an N-channel MO between the P-channel MOS transistor 13 and the ground potential GND.
The S transistor 33 is arranged. The gate of the N-channel MOS transistor 33 is connected to the power supply via the resistor 34.

This N-channel MOS transistor 33
By arranging, the parasitic transistor 2 shown in FIG.
The formation of 1's is prevented. Therefore, the electrostatic breakdown voltage is improved. Since the gate of the N-channel MOS transistor 33 is kept at the power supply voltage V _DD , the P-channel MOS transistor 33
The transistor 13 is substantially grounded in circuit operation, and therefore, in circuit operation, characteristics equivalent to those of the conventional Schmitt trigger circuit shown in FIG. 4 are retained.

FIG. 3 is a circuit diagram of an embodiment of the third Schmitt trigger circuit of the present invention. This is a composite of the embodiment of the first Schmitt trigger circuit shown in FIG. 1 and the embodiment of the second Schmitt trigger circuit shown in FIG. 2, and a description thereof will be omitted.

[0020]

As described above, according to the Schmitt trigger circuit of the present invention, characteristics equivalent to those of the conventional Schmitt trigger circuit are maintained in terms of circuit operation, and electrostatic breakdown voltage is improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a first Schmitt trigger circuit of the present invention.

FIG. 2 is a circuit diagram of an embodiment of a second Schmitt trigger circuit of the present invention.

FIG. 3 is a circuit diagram of an embodiment of a third Schmitt trigger circuit of the present invention.

FIG. 4 is a circuit diagram of a conventional Schmitt trigger circuit.

[Explanation of symbols]

10 Inverter 11, 12, 13, 31 P-channel MOS transistor 14, 15, 16, 33 N-channel MOS transistor 32, 34 Resistance

Claims (3)

[Claims] 1. A first P-channel MOS transistor and a second P-channel MOS transistor connected in series to a common signal input terminal and connected in series between a power supply potential and a ground potential, from the power supply potential side. Channel MOS transistor,
A first N-channel MOS transistor, a second N-channel MOS transistor, the first P-channel MOS transistor and the second
Is connected between the first connection point with the P-channel MOS transistor and the ground potential and the gate is
The second P-channel MOS transistor and the first
A third P-channel MOS transistor connected to a second connection point with the N-channel MOS transistor of
And a third portion between the first N-channel MOS transistor and the second N-channel MOS transistor.
The third terminal connected in series between the connection point and the power supply potential.
In order from the connection point side, a third N-channel MOS transistor whose gate is connected to the second connection point and a fourth P-channel MOS transistor whose gate is connected to the ground potential directly or via an impedance element are provided. A Schmitt trigger circuit characterized in that 2. A first P-channel MOS transistor and a second P-channel MOS transistor, which are connected to a common signal input terminal and connected in series between a power supply potential and a ground potential, in order from the power supply potential side. Channel MOS transistor,
A first N-channel MOS transistor, a second N-channel MOS transistor, the first P-channel MOS transistor and the second
Of the second P-channel MOS transistor connected in series between the first connection point between the second P-channel MOS transistor and the second P-channel MOS transistor and the ground potential.
A third P-channel MOS transistor connected to a second connection point between the transistor and the first N-channel MOS transistor, and a third N-channel gate connected to the power supply potential directly or via an impedance element. A channel MOS transistor, and the first N-channel MOS transistor and the second N-channel M
A Schmitt characterized by comprising a fourth N-channel MOS transistor connected between a third connection point with the OS transistor and the power supply potential and having a gate connected to the second connection point. Trigger circuit. 3. A first P-channel MOS transistor and a second P-channel MOS transistor connected in series to a common signal input terminal and connected in series between a power supply potential and a ground potential, from the power supply potential side. Channel MOS transistor,
A first N-channel MOS transistor, a second N-channel MOS transistor, the first P-channel MOS transistor and the second
Of the second P-channel MOS transistor connected in series between the first connection point between the second P-channel MOS transistor and the second P-channel MOS transistor and the ground potential.
A third P-channel MOS transistor connected to a second connection point between the transistor and the first N-channel MOS transistor, and a third P-channel MOS transistor whose gate is connected to the power supply potential directly or via an impedance element. N
A channel MOS transistor, and a third connection point between the first N-channel MOS transistor and the second N-channel MOS transistor and a third connection point connected in series between a power supply potential and the third connection point side. In sequence, a fourth N-channel MOS transistor having a gate connected to the second connection point and a fourth P-channel MOS transistor having a gate connected to the ground potential directly or via an impedance element are provided. Schmitt trigger circuit.