JPH07176757A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To simply perform nuclear formation by a selective nuclear formation method and large diameter makeup of polycrystalline silicon by solid phase growth without using lithography method. CONSTITUTION:An XeCl eximer laser irradiats (irradiated regions 5) in the shape of grating on amorphous silicon 2 on a a substrate by using diffraction grating. Later, in a nitric atmosphere heat treatment of 600 deg. is performed for performing solid phase growth in order to grow crystal grains having crystallites 5 as nuclei. In case a selective nucleus formation method is not used, a crystal grain diameter is about 1 to 2mum and the maximum obtainable crystal grain diameter is about 4mum and mobility of a thin film transistor having this as a channel region can be improved from 80cm<2>/Vs to 150cm<2>/Vs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor.

[0002]

2. Description of the Related Art A thin film transistor is a semiconductor that forms a MOS type transistor by forming a semiconductor thin film of silicon or the like on an insulating substrate of quartz glass or the like, and forming a channel forming region in which a channel is formed, source and drain regions. It is a device. Since a thin film transistor having a polycrystalline semiconductor film as a channel forming region can be easily formed on an insulating substrate, it is widely applied as a load element of SRAM, a switching transistor of a liquid crystal display device, a driving circuit, or the like. However, since the crystal grain boundaries in the channel forming region greatly deteriorate the transistor characteristics, a method of increasing the crystal grain size or controlling the crystal grain size and the position of the crystal grain has been widely studied.

As one method of controlling the position of crystal grains, there is a method called quantum annealing method as disclosed in Japanese Patent Laid-Open No. 60-37721. In this method, the amorphous semiconductor layer or the polycrystalline semiconductor film is crystallized by irradiating the amorphous semiconductor layer with a light beam obtained by processing an energy beam such as a laser beam into a fine pattern to control the position of crystal grains. It is an attempt to do.

As an attempt to control the crystal grain size, there is a selective nucleation method as shown in FIG. Hereinafter, the selective nucleation method will be described with reference to FIG. Amorphous silicon 2 is formed on an insulating substrate 1 such as a quartz substrate using a disilane gas at about 475 ° C. by a low pressure chemical growth method. After that, a protective oxide film 3 is deposited with a thickness of 50 nm, and then a silicon film 4 is sputtered with a thickness of 200 nm as a laser light shielding film, and a window of 1 μm or less is opened in a specific portion of the sputtered silicon film (FIG. 6A). Then, XeCl excimer laser is irradiated. Since this laser light has a very high absorption coefficient in the silicon film, only the amorphous silicon surface portion of the opening is annealed, and several microcrystalline silicon nuclei 5 are formed in this area. Next, after removing the sputtered silicon film 4 and the protective oxide film 3, a heat treatment is performed in nitrogen at 600 ° C. to expand the crystallized region 6 around the microcrystal 5 serving as a seed (FIG. 6B). Among the crystal grains in the seed region, those with a high growth rate selectively spread to the amorphous region,
Basically, it can be considered that single or approximately two crystal grains are generated and grown from the seed region. In this way, the crystallization of the entire film is completed. The above process is called a selective nucleation method. By this method, the position of the crystal grain can be set at an arbitrary position. The crystal grain size is limited by the generation of nuclei other than the seed portion, but the crystal grain size becomes 4 to 5 μm by optimizing various conditions, and the crystal grain size of the polycrystalline silicon formed by the conventional solid phase growth method. 1-2 which is the diameter
It can be much larger than μm.

After that, a thin film transistor is formed in the single crystal region by the following steps. First, the channel forming region 12 is basically formed by patterning at a position where a single crystal grain is formed, and then the gate oxide film 8 and polycrystalline silicon are deposited, and then the resistance is reduced by a phosphorus diffusion method to perform patterning. Then, the gate electrode 9 is formed. A source region 10 and a drain region 11 are formed by ion implantation. After depositing the interlayer film 13, heat treatment at about 900 ° C. is performed to reflow the interlayer film and activate impurities in the source and drain regions (FIG. 6C). Then, contact holes are opened, aluminum is sputtered, and then patterned to form wiring, and hydrogen alloying is performed at about 400 ° C. in a hydrogen atmosphere to complete a thin film transistor.
By making the size of the manufactured thin film transistor equal to or smaller than the crystal grain size, basically, it is possible to prevent the channel region from including crystal grain boundaries, so that a very high mobility can be obtained. For example, in the case of n-ch, which was 60 cm ² / Vs in the method without using a normal seed, high mobility of 150 cm ² / Vs or more can be obtained by using this selective nucleus growth method.

[0006]

When the transistor size is equal to or larger than the crystal grain size, it is inevitable that several crystal grains exist in the channel formation region of one transistor. In this case, it is not always necessary to control the nucleation position itself, and it is important to increase the crystal grain size and reduce the density of crystal grain boundaries in the channel region. When the quantum annealing method is used as a method of increasing the grain size, the lithography step is not used, so the process is simple, but after recrystallization, undulations and irregularities occur on the surface of the silicon film, resulting in deterioration of TFT characteristics. Bring In order to avoid this, a method of annealing after depositing an oxide film on amorphous silicon has been studied. However, in this method, oxygen diffuses from the oxide film into the polycrystalline silicon to increase the mobility. There is a problem of lowering it. In the selective nucleation method by local annealing using laser light for the purpose of single crystallization of the channel formation region, it is a problem in the quantum annealing method because it is annealed and crystallized in the furnace after nucleation. Such surface roughness does not occur. However, since a light-shielding film is provided on a specific portion for patterning, lithography and etching steps are required, which causes a problem that the steps are complicated.

An object of the present invention is to solve such a conventional problem and simplify the control of the crystal grain size distribution and the position of the crystal grain boundary during crystallization of amorphous silicon without using a lithography method. The purpose is to improve TFT characteristics and reduce variations.

[0008]

According to the present invention, an amorphous semiconductor film is locally heat-treated in a dot or stripe pattern at a specific cycle to form crystal nuclei, and then the whole film is heat-treated. The method for producing a thin film transistor is characterized in that the polycrystalline semiconductor film obtained by subjecting to a solid phase growth is used as a channel formation region. Here, the dot-shaped or stripe-shaped local heat treatment is performed by processing the energy rays into lattice points and irradiating the amorphous semiconductor film, or by focusing the energy rays to the amorphous semiconductor film. It is preferable to perform the irradiation by irradiating the periodical positions.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a plan view for explaining one embodiment of the present invention in the order of steps, and FIG. 2 is a cross-sectional view of a thin film transistor obtained according to this embodiment. This embodiment will be described with reference to FIG. Amorphous silicon 2 is deposited to a thickness of 80 nm on the quartz substrate 1 by using low pressure chemical growth using disilane. Then, as shown in FIG. 1A, a diffraction grating was used to holographically process and irradiate a XeCl excimer laser into a grating shape. The lattice points were spaced at 1 to 8 μm intervals (in FIG. 1, 4 μm intervals were shown), and in order to irradiate the entire surface of the wafer, irradiation was performed by shifting so that the beam irradiation regions overlap in the X and Y directions. The irradiation energy is
The irradiation area (seed area) 5 was set to 180 mJ / cm ² so that some fine crystals were generated. afterwards,
The entire film was crystallized by heat treatment at 600 ° C. in a nitrogen atmosphere. As shown in FIG. 1B, the crystallization is performed by crystal growth using microcrystalline silicon in the irradiation region (seed region) 5 as a nucleus, and the growth is stopped when the crystal grains 6 grown from the adjacent seed come into contact with each other. To do. In the subsequent steps, using the frame 12 of FIG. 1B as a channel forming region, a thin film transistor whose cross section is shown in FIG. 2 was manufactured in the same manner as in the conventional example.

FIG. 3 shows the relationship between the mobility and the seed spacing of the thin film transistor obtained in this example. As is clear from FIG. 3, in the method of the present embodiment, the mobility is improved from the seed interval of 3 μm to 7 μm, and the maximum mobility is 140 cm ² / Vs at the seed interval of about 4 μm. If the seed region spacing is too wide, the crystal grains nucleated from the amorphous silicon region 2 remaining between the crystal grains 6 nucleated from the seed region hinder the increase in grain size and lower the mobility. Is believed to bring. The optimum value of the seed region interval depends on the seed formation method, amorphous silicon formation conditions, amorphous silicon film thickness, solid-phase growth conditions, etc., so optimization is necessary within those process conditions. Is.

As described above, the method described in the present embodiment is characterized in that the seed regions are arranged in a grid pattern with an equal interval of about 4 μm, so that the grain size can be increased. In addition, according to this method, the periodic seed region can be formed by a much simpler process without the need for complicated processes such as the light-shielding film deposition, the lithography process, and the etching process, which are required in the conventional example. In addition, the surface roughness, which is a problem in the quantum annealing method, does not occur as in the conventional selective nucleation method.

The annealing process for seed formation may be an annealing process using a focused electron beam, an ion beam or the like. Further, when the method of melting only the surface of the polycrystalline silicon film by laser irradiation is used, the crystal grain size,
Without changing the orientation, the crystal defects in the crystal grains can be reduced, the mobility becomes about 200 cm ² / Vs, and the TFT characteristics can be further improved.

Embodiment 2 An example in which the present invention is applied to a transistor constituting a drive circuit and a switching transistor of a pixel portion used in a liquid crystal display device will be described with reference to FIG. A light-shielding film is formed in a region where the pixel switching transistor is formed on the underlying transparent substrate, and an underlying oxide film is deposited, and then an amorphous silicon film is deposited under the same conditions as in Example 1.
After that, nucleation was performed by irradiating the transistors and the pixel transistors included in the peripheral drive circuit with a focused electron beam. Transistors that make up the drive circuit have a gate length of 8μ
m, the transistor in the pixel portion has a gate length of 8 μm and an offset length of 1 μm. In the drive circuit transistor, the internuclear distance is set to 3 to 7 μm as described in Example 1, the crystal grain boundaries exist at the source end, and the crystal grain boundaries do not exist at the drain end. The nucleation position was determined so as to be in the position of the frame 12 in (). In the pixel portion transistor, nucleation was performed so that the gate end portion was located at the position of the frame 16 in FIG. In the nucleation, the nuclei were formed in the whole pixel interval with the arrangement period of the pixel transistors being 50 μm so that all the pixel transistors were nucleated. The alignment of the wafer was performed using the alignment mark on the layer of the light shielding film. The subsequent steps are the same as those of the conventional thin film transistor. After forming the aluminum wiring, plasma hydrogenation treatment was performed.

FIG. 5 shows the output characteristics of the transistors that form the drive circuit of this embodiment. In the figure, (a) shows the case where annealing is performed without controlling the positions of the crystal grain boundaries according to the conventional example, and (b) shows the case according to this example. As can be seen by comparing the characteristics, as the mobility increases, not only the on-current increases, but also the breakdown voltage between the source and drain improves. This is because the density of the grain boundary of the drain junction, which causes avalanche breakdown, was reduced, and the density of the grain boundary of the source junction was increased to shorten the carrier lifetime and This is probably because the bipolar effect could be reduced. In the pixel transistor, not only the on-current increased but also the leakage current could be reduced from 0.3 pA to 0.1 pA or less by the method of this embodiment. It is considered that this is because the density of the crystal grain boundary at the drain side junction could be reduced.

[0015]

As described above, according to the present invention, when the amorphous semiconductor layer is crystallized, the heat treatment is locally performed on the amorphous semiconductor layer at a specific cycle, and then the entire film is subjected to heat treatment. By using the method of forming by performing heat treatment and solid-phase growth, by promoting nucleation and growth from the locally heat-treated part, the crystal grain size can be increased and mobility of thin film transistor is improved. The effect is that you can do it. When controlling the position of the crystal grain boundary, it also has the effect of improving the source-drain breakdown voltage and reducing the leak current. Further, there is also an effect that the steps such as the lithography step and the etching step, which are required in the conventional selective nucleation method, are not necessary and the steps can be simplified.

[Brief description of drawings]

FIG. 1 is a process explanatory diagram of Example 1 of the present invention.

FIG. 2 is a cross-sectional view of a thin film transistor obtained according to Example 1 of the present invention.

FIG. 3 is a diagram showing a relationship between mobility and a seed interval.

FIG. 4 is an explanatory diagram of a second embodiment of the present invention.

FIG. 5 is a diagram showing transistor characteristics of a TFT of Example 2 in comparison with a conventional example.

FIG. 6 is a process cross-sectional view of a thin film transistor using a selective nucleation method according to a conventional example.

[Explanation of symbols]

 1 Insulating Substrate (Quartz Substrate) 2 Amorphous Silicon 3 Protective Oxide Film 4 Silicon Film 5 Irradiation Area (Microcrystalline Silicon Nucleus) 6 Solid Phase-Grown Silicon Crystal Grain 7 Crystal Grain Boundary 8 Gate Oxide Film 9 Gate Electrode 10 Source Region 11 drain region 12 channel formation region 13 interlayer film

Claims (3)

[Claims] 1. An amorphous semiconductor film is locally heat-treated in a dot or stripe pattern at a specific cycle to form crystal nuclei, and then the whole film is heat-treated for solid phase growth. A method of manufacturing a thin film transistor, which comprises using the obtained polycrystalline semiconductor film as a channel formation region. 2. The method for manufacturing a thin film transistor according to claim 1, wherein the dot-shaped or stripe-shaped local heat treatment is performed by processing energy rays into lattice points and irradiating the amorphous semiconductor film. 3. The method of manufacturing a thin film transistor according to claim 1, wherein the dot-shaped or stripe-shaped local heat treatment is performed by converging an energy beam and irradiating it to a periodic position of the amorphous semiconductor film.