JPH07176706A - Nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] A unit cell area can be reduced without increasing the bit line capacitance and erroneous writing at the time of writing data, and a NAND cell type E that enables high integration is achieved.
Provide EPROM. In a NAND cell type EEPROM, a cell array in which NAND cells in which memory cells in which floating gates and control gates are stacked are connected in series are arranged in a matrix, and a drain diffusion layer on one end side of the NAND cells is a plurality of NAND cells Multiple first cells directly connected in cell units
A bit line BL1, a second bit line BL2 to which the first bit line BL1 is connected via a selection transistor S2, and a source diffusion layer on the other end side of the NAND cell are connected via a selection transistor S1. Source line,
Control gate CG of each memory cell constituting the NAND cell
Are respectively connected to word lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a NAND cell type non-volatile semiconductor memory device (EEPROM) using an electrically rewritable memory cell having a structure in which a charge storage layer and a control gate are laminated.

[0002]

2. Description of the Related Art Conventionally, an N-type memory cell having a plurality of memory cells connected in series has been proposed as a highly-integrated EEPROM.
An AND cell type is known. In the first proposed NAND cell type, a plurality of memory cells whose threshold voltage goes up and down 0V by writing / erasing data are arranged in series, and selection transistors are connected in series on the drain side and the source side. It is a cell structure having a different configuration. The NAND memory cells are arranged in a matrix to form an EEPROM memory array. After that, for the purpose of further reducing the cell area, a structure in which the drain side select transistor is eliminated from the above structure is proposed.

The operation of the NAND cell type EEPROM is as follows. Data writing is sequentially performed from the memory cell farther from the bit line. In the case of n channel, for example, a high potential Vpp (for example, 20V) is applied to the control gate of the selected memory cell, and the intermediate potential Vpp is applied to the control gate of the memory cell on the bit line side.
m1 (for example, 0 V) is applied. Further, 0 V (for example, data “1”) or the intermediate potential Vm2 (for example, data “0” and Vm2 is 5 V, for example) is applied to the bit line according to the data. At this time, the potential of the bit line is transmitted to the drain of the selected memory cell through the non-selected memory cell. Further, 0 V is applied to the source side select gate so that no current flows through the NAND cell to the common source when Vm2 is applied to the bit line.

When there is data to be written (“1” data), a high electric field is applied between the gate of the selected memory cell and the drain / substrate, and electrons are tunnel-injected from the substrate to the floating gate. As a result, the threshold value of the selected memory cell moves in the positive direction. When there is no data to be written (“0” data), the threshold value does not change.

In data erasing, a high potential is applied to a p-type substrate (in the case of a well structure, an n-type substrate and a p-type well formed therein), and the control gates and select gates of all memory cells are set to 0V. It As a result, in all the memory cells, electrons in the floating gate are emitted to the substrate, and the threshold value moves in the negative direction.

In the data reading, the power supply potential Vcc = 5V is applied to the selected gate and the control gate of the non-selected memory cell to turn it on, and 0V is applied to the gate of the selected memory cell. Further, a potential of 0 V is applied to the source line and a potential of 1 V or higher is applied to the bit line. At this time, "0" or "1" of the held data is determined depending on whether or not a current flows through the bit line.

By the way, in the cell structure in which the selection transistor on the drain side is omitted from the conventional NAND cell,
Although it is possible to reduce the chip area and increase the integration of the NAND cell type EEPROM, there are the following problems. That is,
Since the drain diffusion layers of a plurality of NAND cells are directly connected to the bit line, the capacity of the bit line becomes large. Therefore, there is a high possibility that erroneous writing will occur at the time of writing data, and there is a problem that reliability is reduced.

[0008]

As described above, in the conventional cell structure in which the selection transistor on the drain side is omitted from the NAND cell in order to achieve high integration, the unit cell area is small, but the bit line capacitance is large. There is a problem that the possibility of erroneous writing at the time of writing data increases.

The present invention has been made in consideration of the above circumstances, and an object thereof is to avoid the problems of an increase in bit line capacity and erroneous writing at the time of writing data.
An object of the present invention is to provide a NAND cell type EEPROM capable of reducing the unit cell area and achieving high integration and reliability improvement.

[0010]

SUMMARY OF THE INVENTION The essence of the present invention is to connect a branch bit line to a trunk bit line through a select transistor, and to connect a branch cell with a drain diffusion layer of a NAND cell. It is a direct connection.

That is, the present invention is a NAND cell type EEPRO.
In M, a NAND cell in which electrically rewritable memory cells in which a charge storage layer and a control gate are laminated on a semiconductor substrate via an insulating film are connected in series so that adjacent ones share a source and a drain And configure this NA
A cell array in which ND cells are arranged in a matrix;
A plurality of NANs are provided in the drain diffusion layer on one end side of the AND cell.
A plurality of first bit lines directly connected in units of D cells,
A second bit line connected to each of these first bit lines via a selection transistor, a source line connected to each of the other source diffusion layers of the NAND cells via a selection transistor, and a NAND cell are configured. And a word line connected to the control gate of each memory cell.

Here, the following are preferred embodiments of the present invention. (1) The memory cell is a FETMOS type memory cell using a floating gate as a charge storage layer. (2) The select transistor is composed of the gate electrode made of the first-layer polycrystalline silicon and the wiring made of the second-layer polycrystalline silicon, and is formed at the same time as the transistor of the memory cell.

[0013]

In the present invention, the drain side select transistor is completely removed from the original NAND cell, and one select transistor is attached to each of the plurality of NAND cells. That is, a plurality of NAs sharing the same first bit line
One selection transistor is provided for each ND cell, and the second bit line and the first bit line are connected via this.

Therefore, at the time of data reading, most of the non-selected NAND cells can be separated from the bit line by turning off the non-selected selection transistor, so that the bit line capacitance can be reduced as compared with the case where all the selection transistors are removed. The increase can be kept small. Further, for the same reason, the possibility of erroneous writing at the time of writing data can be suppressed to a small level, and thus reliability can be improved.

[0015]

Embodiments will be described below with reference to the drawings. FIG. 1 shows an N of an EEPROM according to an embodiment of the present invention.
2A and 2B are plan views showing an AND cell structure, and FIGS. 2A and 2B are cross-sectional views taken along arrows AA 'and BB'. Further, FIG. 3 is an equivalent circuit of this NAND cell.

In this embodiment, four memory cells M1 ...
M4 is connected in series in such a manner that the source and drain diffusion layers are shared by adjacent ones to form a NAND cell. Such NAND cells are arranged in a matrix to form a cell array. The drain on one end side of the NAND cell is directly connected to the first bit line BL1, and the source on the other end side is connected to the common source line (ground line) via the selection gate S1. First bit line BL1
Is directly connected to the drain of another NAND cell (not shown) and is connected to the second bit line B via the select gate S2.
It is connected to L2. Control gate CG of each memory cell
_{1 to} CG ₄ are arranged in a direction intersecting with the first bit line BL1 to form the word line WL.

In this embodiment, four memory cells form one NAND cell, but generally two n-th power memory cells (n = 1, 2, ...) Form one NAND cell. can do.

A specific memory cell structure is as shown in FIG. A p-type well 1'is formed on the n-type silicon substrate 1, and memory cells are arranged in the p-type well 1 '. The peripheral circuit will be formed in a p-type well different from the memory cell. Four memory cells and one select gate are formed in a region surrounded by the element isolation insulating film 2 of the p-type well 1 '.

Each memory cell has 5 to 5 on the p-type well 1 '.
A floating gate 4 (4 ₁ to 4 ₄ ) made of first-layer polycrystalline silicon having a thickness of 50 to 400 nm formed through a first gate insulating film 3 ₁ made of a thermal oxide film having a thickness of 20 nm.
Control gates 6 (6 _{1 to} 6 ₄ ) made of second-layer polycrystalline silicon having a thickness of 100 to 400 nm formed via a second gate insulating film 5 made of a thermal oxide film having a thickness of ˜40 nm. The n-type layer 9 serving as the source / drain diffusion layer of each memory cell is shared by the adjacent ones.
Memory cells are connected in series.

[0020] The source-side end of the NAND cell, p-type well 1 'gate insulating film 3 ₂ first-layer gate electrode 4 formed of polycrystalline silicon via made of a thermal oxide film 5~40nm on A select gate with ₅ is formed.
Here, the gate insulating film 3 ₂ may be the same as the first gate insulating film 3 ₁ . A wiring 6 ₅ made of the second-layer polycrystalline silicon is arranged on the gate electrode 4 ₅ in an overlapping manner. The gate electrode 4 ₅ and the wiring 6 ₅ are connected by through holes at predetermined intervals to reduce the resistance.

Also, for each of a plurality of NAND cells, a gate electrode 4 ₆ formed of the first-layer polycrystalline silicon is formed on the p-type well 1 ′ through a gate insulating film 3 ₂ made of a thermal oxide film of 5 to 40 nm. A select gate having is formed. A gate electrode 4 ₆ wiring according to the second-layer polycrystalline silicon 6 ₆
Are arranged in a stack. The gate electrode 4 ₆ and the wiring 6 ₆ are connected by through holes at predetermined intervals to reduce the resistance.

Here, the floating gates 4 ₁ to 4 ₁ of each memory cell are
4 ₄ and the control gates 6 _{1 to} 6 ₄ , the gate electrode 4 ₅ and the wiring 6 _{5 of the} selection gate, and the gate electrode 4 ₆ and the wiring 6 ₆ are patterned and aligned in the channel length direction using the same etching mask. ing. The n-type layer 9 serving as a source / drain diffusion layer is formed by ion implantation of arsenic or phosphorus using these electrodes as a mask.

The CVD insulating film 7 ₁ is formed on the substrate on which the elements are formed.
Covered with a third polycrystalline silicon layer on which the first
Bit line 8 is provided. The drain on one end side of the NAND cell is directly connected to the first bit line 8 without passing through the select gate, and is also connected to the select gate having the gate electrode 4 ₆ .

[0024] On the first bit line 8, it is covered by a CVD dielectric film 7 _2, the second bit line 10 is arranged by an Al film thereon. The first bit line 8 is connected to the second bit line 10 via the select gate having the gate electrode 4 ₆ .

2B, the drain diffusion layer on one end side of the plurality of NAND cells and the source or drain of the select gate having the gate electrode 4 ₆ are provided in different regions. These may be the same as shown.
In this case, the region of the element isolation insulating film 2 shown in FIG. 2B is not necessary, which is effective in miniaturizing the element.

FIG. 5 shows the second bit line BL2 (BL2A, B2).
8 NAND cell parts adjacent to each other connected to (L2B) are shown, and the EEPROM operation will be described using this. Although the NAND cell is composed of two memory cells in this figure, it is needless to say that it may be composed of three or more memory cells. Also, the drains of two NAND cells are connected to the first bit line, but three or more N
Of course, the drain of the AND cell may be connected.

First, in the data erasing, the memory cells constituting the NAND cell are collectively erased. Therefore, in this embodiment, the gate electrodes SGD1 and SG of the selection gate S are
The control gates CG1 to CG8 of D2 and SGS1 to SGS4 and all memory cells in the NAND cell are set to 0V, and the boosted high voltage Vpp '(for example, 18V) is applied to the n-type substrate 1 and the p-type well 1'. . Further, the second bit line BL2
Is also supplied with a high potential Vpp '.

As a result, an electric field is applied between the control gates CG of all the memory cells and the p-type well 1 ', and electrons are emitted from the floating gate 4 to the p-type well 1'by a tunnel current. Therefore, the threshold values of all the memory cells are moved in the negative direction to be in the "0" state.

Next, data writing is sequentially performed from the memory cell on the source line side in the NAND cell, that is, the memory cell farther from the bit line BL. Now, memory cell M
A case where "1" data writing is selectively performed on 8 (cell A surrounded by a broken line in FIG. 5) will be described.

Gate electrode SGS1 of the source side select gate
~ SGS4 is set to 0V, the gate electrode SGD1 of the non-selected drain side selection gate is also set to 0V, and the power source potential V is applied to the gate electrode SGD2 of the selected drain side selection gate.
an intermediate potential between the cc and the high potential Vpp V _M (e.g. (1/2)
Vpp) is applied. Also, the high potential Vpp (e.g. 16～18V) is applied to the control gate CG8, intermediate voltage V _M is applied to the remaining control gate CG1 ~CG7. Further, 0V is applied to the selected bit line BL2A, and the power supply potential Vcc (5V) is applied to the non-selected bit line BL2B.
The p-type well 1'is set to 0V and the n-type substrate 1 is set to Vcc.

As a result, in the selected cell A, 0 V of the bit line BL2A is transmitted to the drain, a high electric field is applied between the bit line BL2A and the control gate CG8, and electrons are injected into the floating gate. As a result, in the cell A, the threshold value moves in the positive direction, and "1" is written.

At this time, since all the drain side select gates having SGD1 as the gate electrode are closed, the branch bit line B
The potential of the trunk bit lines BL2A and BL2B is not transmitted to L1A1 and BL1B1. Therefore, the control gates CG1 to CG4
No electric field is applied between the channel and drain, and M ₁ ~
The threshold change of M _4, M ₉ ~M ₁₂ is not.

[0033] becomes the other memory cells M ₅ ~M ₇ in write mode leading to the branch bit line BL1A2, the electric field is small, no threshold changing. Unselected branch bit line B
In L1B2 side of the memory cell M ₁₃ ~M _15, the control gate is an intermediate potential V _M, the channel potential is Vcc, the potential difference is a 3 to 4V, not too threshold changing. Similarly, the memory cell M ₁₆ on the side of the bit line BL1B2 is also in the write mode, but its electric field is still small and the threshold value does not change.

[0034] In the above write operation, the control gate of the memory cell is a high potential Vpp and the intermediate voltage V _M is applied, the current flowing Since only the tunnel current is most 1μA or less. In addition, when collectively erasing, the n-type substrate 1 and p
The type well 1'is raised to a high potential Vpp '. The current flowing at this time is a tunnel current and a leak current between the p-type well and the n-type substrate of the peripheral circuit which is kept at 0V.
It is 0 μA or less. Therefore, the high potentials Vpp and Vpp 'used for writing and erasing (these may have the same value).
Can be sufficiently covered by a booster circuit provided inside the chip.

Further, since the current flowing due to the high voltage at the time of selective writing is minute as described above, it is possible to simultaneously write data to all the memory cells connected to one control gate line (word line). That is, page mode writing can be performed, and high speed writing can be performed accordingly.

The data read operation is performed as follows. Explaining the cell A of FIG. 5, 0V is applied to the non-selected SGD1 of the drain side select gates, and Vcc is applied to the selected SGD2.
₇ the memory cell for "1" state to the control gate CG7 of still Vcc is applied as a potential enough to turn on, the control gate CG8 of the selected memory cell M ₈ is a 0V. For example, 0V is applied to the other control gates CG1 to CG6. Then, a read potential of about 1 to 5 V is applied to the bit line BL2A connected to the selected cell, and the other non-selected bit lines BL2B are set to 0 V.

In this way, when the threshold value of the cell A is low, a current flows through the second bit line BL2A, and when it is high, the second bit line BL2A has a second current value.
No current will flow through the bit line BL2A. Therefore,
The data "0" or "1" is discriminated depending on whether or not a current flows through the bit line BL2A.

As described above, according to this embodiment, since the drain side select gate is one for each of the plurality of NAND cells, the bit line capacitance is increased as compared with the case where all the drain side select gates are removed. Can be kept small. Therefore, the possibility of erroneous writing at the time of writing data can be suppressed to a low level, and thereby reliability can be improved.

Further, since the number of select gates is smaller than that in the case where select gates are provided on the drain side of all NAND cells, the cell area can be reduced.
In other words, according to the present embodiment, highly integrated and highly reliable NAND
A cell type EEPROM can be realized.

The present invention is not limited to the above embodiment. Although the FETMOS type memory cell having the floating gate and the control gate is used in the embodiment, the present invention can be similarly applied to the case of using the MNOS type memory cell. Further, conditions such as the number of memory cells forming the NAND cell and the number of NAND cells directly connected to the first bit line may be appropriately determined according to the specifications. In addition, various modifications can be made without departing from the scope of the present invention.

[0041]

As described in detail above, according to the present invention, N
A plurality of NANs are provided in the drain diffusion layer on one end side of the AND cell.
Since each D cell is directly connected to the first bit line and the first bit line is connected to each second bit line through the selection transistor, there is a problem of increase in bit line capacity and erroneous writing during data writing. The unit cell area can be reduced without inviting, and it becomes possible to realize a NAND cell type EEPROM capable of achieving high integration and high reliability.

[Brief description of drawings]

FIG. 1 is an NA of an EEPROM according to an embodiment of the present invention.
FIG. 3 is a plan view showing an ND cell structure.

FIG. 2 is a sectional view taken along the line AA ′, BB ′ of FIG.

FIG. 3 is an equivalent circuit diagram of the NAND cell of FIGS. 1 and 2.

FIG. 4 is a cross-sectional view showing a modified example corresponding to the configuration of FIG.

FIG. 5 is a circuit diagram showing eight NAND cell units adjacent to each other connected to a second bit line.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... N-type silicon substrate 1 '... P-type well 2 ... Element isolation oxide film 3 ... First gate insulating film 4 ... Floating gate (charge storage layer) 5 ... Second gate insulating film 6 ... Control gate 7 ... CVD insulating film 8 ... first bit line 9 ... source-drain diffusion layer (n-type layer) 10 ... second bit line M ₁ ~M ₄ ... memory cell S ... selection gate CG ₁ ~CG ₄ ... control gate BL1 ... first bit line BL2 ... second bit line WL ... word line

Claims (1)

[Claims] 1. An electrically rewritable non-volatile memory cell in which a charge storage layer and a control gate are laminated on a semiconductor substrate via an insulating film is connected in series so that adjacent ones share a source and a drain. To form a NAND cell,
A cell array in which the NAND cells are arranged in a matrix, a plurality of first bit lines directly connected to the drain diffusion layer on one end side of the NAND cells in units of a plurality of NAND cells, and the first bit lines A second bit line connected via a select transistor; a source line connected to the source diffusion layer on the other end side of the NAND cell via a select transistor; and a memory cell forming each NAND cell. A non-volatile semiconductor memory device comprising: a word line connected to each control gate.