JPH07176147A - Digital signal recording / reproducing apparatus - Google Patents

Abstract

(57) [Summary] (Modified) [Object] The present invention reduces the load of error correction decoding in a digital signal recording / reproducing apparatus for recording and reproducing a digital signal on a medium such as a magnetic tape, a magnetic disk or an optical disk. And improve the error correction capability of the system. According to the present invention, a means for detecting an error in a reproduced codeword sequence and a means for replacing an erroneous codeword with a regular codeword are provided in an mn conversion decoder 93. When converting an n-bit reproduction codeword sequence into an m-bit data word sequence during reproduction, an error in the reproduction codeword sequence is detected in codeword units and an error detection flag is generated to humming the error codeword. DS closest in distance and in code sequence
V is replaced with a regular code word that approaches 0, and the error correction decoder 100 uses the error detection flag as an erasure flag, i is the random error correction number, j is the erasure error correction number, and d is the minimum Hamming distance. Then, the correction is performed within the range of the expression of 2i + j + 1 ≦ d.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording / reproducing apparatus for recording and reproducing a digital signal on a medium such as a magnetic tape, a magnetic disk or an optical disk.

[0002]

2. Description of the Related Art In a digital VTR and a magnetic disk device, an error correction code is used as a technique for correcting an error caused by dust, scratches or noise on a tape or disk during reproduction. In a digital VTR for recording an image signal on a magnetic tape, a Reed-Solomon code is used as an error correction code for detecting an error in 1-byte units and correcting the error. The Reed-Solomon code often forms a product code including an inner code having a code length of N1 and an outer code having a code length of N2 as shown in FIG. On the recording side, a parity p1 for data d1 in the horizontal direction and a parity p2 for data d2 in the vertical direction are added in the order of vertical and horizontal, and are sequentially recorded on the tape while scanning in the horizontal direction. During reproduction, decoding (correction) is performed from the inner code by the error correction decoder, and errors that cannot be corrected by the inner code are corrected by the outer code when viewed from the vertical direction. Generally, in a digital VTR, the inner code uses random correction.
In the inner code, all the symbols that could not be corrected using random correction are regarded as errors, and an erasure flag is set. On the other hand, when the random correction in the inner code is completed, the correction is performed in the outer code. In the outer code, the position of the symbol indicated by the erasure flag is set as the error position, and the erasure correction for obtaining only the error value is performed. Theoretically, errors are corrected up to (p1 / 2) bytes in the random correction of the inner code and up to p2 bytes in the erasure correction of the outer code. The erasure correction that uses the erasure flag to obtain only the error value is superior to the random correction that obtains the error position and the error value in terms of the correction capability in terms of the number of corrections.

A technique for converting digital data to be recorded on a recording medium such as a digital VTR into a recording code adapted to the characteristics of the recording system is called recording encoding.
Many types of recording codes have been proposed.
For example, as an example of the recording code for reducing the DC component, M
There are two codes and NRZ-ASE code. Examples of the recording code for improving the recording wavelength include (1,7) code. Examples of recording codes that can improve both the DC component and the recording wavelength include 8-12 conversion codes and 8-14 conversion codes. The 8-12 transform code and the 8-14 transform code are generally called m-n transform codes because they convert a sequence of m-bit data words into a sequence of n-bit code words using a predetermined conversion rule. For both the 8-12 converted code and the 8-14 converted code, the run length (“1”,
The minimum value of the consecutive number of "0") is 2 bits. Therefore, the m-n conversion code is (2 × m /
It is possible to lengthen the shortest recording wavelength by the ratio of n). Further, the 8-14 conversion code can be DC-free, and the 8-12 conversion code can be used in combination with word inversion to reduce the DC component.

In a digital VTR and a magnetic disk device, processing is carried out in the order of error correction coding and recording coding during recording, and processing is carried out in order of decoding for recording coding and decoding for error correction coding during reproduction. Normally, all of these processes are performed independently.

On the other hand, a conventional example in which these processes are integrated to improve the performance of a system is disclosed in Japanese Patent Laid-Open No. 03-149923.
There is an issue. Japanese Patent Laid-Open No. 03-149923 discloses an example in which error correction capability is improved by using error information detected in decoding for recording encoding during reproduction.
Decoding for recording coding during reproduction, that is, an erasure flag is set for a symbol in which an error is detected in nm conversion, and erasure correction and random correction are switched according to the number of flags to correct the inner code.

When an m-n conversion code is used in recording coding, when converting a sequence of m-bit data words into a sequence of n-bit code words, if a condition of n> m is satisfied, an n-bit reproduction code word is obtained. Errors may be detected when the sequence is inversely transformed into an m-bit data word sequence. Correspondence from an m-bit data word to an n-bit code word does not always use all bit patterns of "1" and "0" that can be represented by n bits. 8-14 conversion code, 8-12 as an mn conversion code for converting an m-bit data word into an n-bit code word
Converted codes can be mentioned. The rate of using an n-bit bit pattern as a code word is 4.7% in the case of the 8-14 converted code and 9.8% in the case of the 8-12 converted code. Not so much. Therefore, when an error occurs during reproduction, and an n-bit bit pattern that does not correspond to an m-bit data word is reproduced, it can be detected as an error.

[0007]

In the above-mentioned prior art, the effect of erasure correction is exhibited only when the number of errors in the inner code is less than the maximum number of erasure corrections and all of them can be detected. However, not all errors can be detected by the nm conversion. If an n-bit bit pattern that is not regular and does not correspond to an m-bit data word is reproduced, it can be detected as an error, but if it is replaced with a regular code word, it cannot be detected as an error and an undetected error occurs. It may occur. The detection failure is proportional to the usage rate of the bit pattern, and the higher the usage rate, the more the detection failure occurs. In the conventional example, the inner code in which the detection omission occurs at the time of nm conversion has a configuration in which the effect of improving the correction capability cannot be obtained. Error detection is unavoidable for both the 8-14 converted code and the 8-12 converted code, and this problem always occurs. In particular, the m-n conversion code with a high utilization rate (for example, 8-9 conversion code,
When it is applied to 8-10 conversion code, etc.), it becomes a big problem, and the effect of improving the correction capability by the nm conversion cannot be expected.

It is an object of the present invention to provide a recording / reproducing apparatus for a digital signal, which has a high error correction capability when an error is detected in nm conversion during reproduction, and further to detect a normal code while detecting an error code word. Another object of the present invention is to provide a digital signal recording / reproducing apparatus having a function of replacing words.

[0009]

SUMMARY OF THE INVENTION According to the present invention, an error detection flag is set for an n-bit code word that has an error during reproduction and cannot correspond to an m-bit data word, and the error detection flag is set. When the minimum Hamming distance to the parity of the inner code is dmin, i is the random correction number, and j is the erasure correction number, the inner code correction is 2i + j.
Random correction and erasure correction mixed algorithms are used within the range of + 1 ≦ dmin.

Further, when an error is detected in advance, an erroneous codeword is replaced with the most appropriate codeword by using the run length and DSV which are the characteristic parameters of the recording code, and is input to the error correction decoder in the next stage. It also has a means to do.

[0011]

According to the present invention, an error detection flag is set for an error code word detected at the time of nm conversion, erasure correction is made for a code word that can be detected, and random correction is made for a code word that cannot be detected. Thus, the effect of improving the correction capability (the number of corrections) can be obtained even when the detection and correction are performed and the detection failure exists.

Furthermore, when an error is detected in advance, an erroneous codeword is replaced with the most suitable codeword in terms of run length and DSV, and the codeword is input to the error correction decoder in the next stage, whereby a more excellent correction is performed. Ability can be realized.

[0013]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a digital signal recording / reproducing apparatus using the present invention for 8-14 conversion code. In FIG. 1, an analog video signal is input from the input terminal 120, and the A / D
It is quantized by the converter 10 into, for example, 8 bits. Next, the error correction encoder 20 forms a product code including an inner code and an outer code, and parity is added in the order of the outer code and the inner code. The synchronization adding circuit 30 adds a synchronization pattern to the data series to which the parity has been added at regular intervals. Before being recorded on the tape, the input m = 8-bit data word sequence is n = 14 by the m-n conversion encoder 40.
The run length, that is, the number of consecutive "1" s and "0s" (NRZL rule) in the code sequence after conversion after conversion to a bit codeword sequence is limited to between 2 bits and 7 bits. In addition, DSV (Digital Sum Var) in the code sequence
iation), that is, the cumulative sum when "1" is +1 and "0" is -1 is always +7 to -7, and +2 to -2 at the last bit position of the codeword. By always reducing the absolute value of DSV, the DC component of the signal is kept in balance, and the influence of low frequency cutoff due to the rotary transformer or magnetic recording / reproducing characteristics can be prevented. Using the P / S converter 50,
After converting the 14-bit code word into serial data, it is recorded by a recording / reproducing system 60 including a tape and a head. At the time of reproduction, an image is reproduced by the sync detector 70, the S / P converter 80, the mn conversion decoder 90 for the mn conversion encoder 40, the error correction decoder 100 for the error correction encoder 20, and the D / A converter 110. The signal is reproduced and output from the output terminal 130. According to the present invention, a general digital VTR independently executes a series of processes such as synchronization detection, S / P, nm conversion decoding, and error correction decoding during reproduction.
Error detection flag 14 that can be detected during m conversion decoding, that is, when converting a 14-bit code word to an 8-bit data word
0 is sent to the error correction decoder 100 to improve the error correction capability, and at the time when the error is detected by the nm conversion decoder 90, the error code word is replaced by the most appropriate regular code word to make the error. The burden on the correction decoder 100 is reduced.

The configuration and operation of the nm conversion decoder 90 and the error correction decoder 100, which are the features of the present invention, will be described in detail with reference to FIG. The reproduction signal 94 of n = 14 bits input to the nm conversion decoder 90 is replaced by the replacement processing unit 91,
It is input to each error detection unit 92. Error detector 92
Then, it is analyzed whether or not the input codeword is included in the regular codeword group. If the input codeword 94 is not included in the regular codewords, the inner code correction processing unit 10 included in the error correction decoder 100 is set with the error detection flag 140.
Send to 1. The error detection unit 92 outputs "1" for a legitimate codeword and "0" for a non-regular codeword.
It can be realized with a simple configuration. The replacement processing unit 91 does not replace the regular code word and outputs it as it is. On the other hand, with respect to the erroneous codeword, the normal codeword 95 which has the shortest Hamming distance for the 14-bit bit pattern and brings the DSV in the code sequence close to 0 is output. The code word 95 is sequentially converted into an 8-bit data word 96 and input to the error correction decoder 100 in the next stage.

FIG. 4 shows a specific example of the replacement processing in the replacement processing unit 91. Here, consider a case where an error occurs in the codeword at time t = T and DSV = -2 at the final point of the 14-bit codeword at t = T-1. As can be seen from FIG. 4, the 14-bit codeword at t = T has one isolated bit and is not included in the normal codeword.
The replacement processing unit 91 replaces the codeword and the error detection unit detects an error. The replacement processing unit 91 prepares two replacement code words that are included in a regular code word, have the shortest Hamming distance, and have different DSV polarities. In this embodiment, CDS = + so that the DSV at time t = T-1 approaches 0.
The code word “01100111100110” of 2 is selected and replaced. Here, CDS (Code Digital S
um) is a cumulative sum when "1" in the codeword is +1 and "0" is -1. The replacement processing unit 91 has an up / down counter for counting DSV and a 15-bit address −14.
It can be configured by a bit output ROM. The address input of the ROM has a total of 15 bits of 14 bits of the code word and 1 bit of the DSV polarity, and two code words having different DSV polarities are recorded with respect to the input of one code word.

The error correction decoder 100 comprises an inner code correction processing unit 101 and an outer code correction processing unit 102, and performs correction from the inner code. In the inner code correction processing unit 101, when the minimum Hamming distance with respect to the parity of the inner code is dmin, the number of corrections by erasure correction is j, and the number of corrections by random correction is i, the error detection flag 140 is set as an erasure flag and Random correction and erasure correction mixed algorithms are used within the range. For the correction algorithm that includes both random correction and erasure correction, refer to "Technical Report of the Television Society of Japan vol.17, No.2".
7, pp.13-18, VIR'93-27 (May.1993) ".

[0017]

## EQU00001 ## 2i + j + 1.ltoreq.dmin For example, dmin = 9 in the inner code having the code length N1 in FIG.
When the number of true errors = 5 and the number of error detection flags is two, the theoretical limit is from j = 0 to i = 4 and up to 4 corrections when the number of error detection flags is 2, and the number of errors in FIG. The error case of 5 is uncorrectable. Further, even in the method of performing erasure correction using the error detection flag according to the prior art, Japanese Patent Laid-Open No. 03-149923, the number of true error is 5 and the number of error detection flag is 2, which results in omission of error detection. Therefore, it cannot be corrected correctly. On the other hand, the present invention utilizes the error detection flag and uses the inner code correction processing unit 101 shown in FIG.
In, correction is performed within the range of the formula (1). In the example of FIG. 5, since i = 3 and j = 2 and the equation 1 is satisfied, the error can be corrected. The operation of the inner code correction processing unit 101 will be described in more detail with reference to the flowchart of FIG.

First, the symbols 96 and error detection flags 140 of all inner codes are input to the inner code correction processing unit 101 (step 202). The input symbol is subjected to syndrome calculation in inner code units (step 20).
3) It is determined whether all the syndrome values that exist by the number of parities are 0 (step 204). When all the syndrome values are 0 and the number of error detection flags in the inner code is 0 in step 209, it is determined that there is no error, the correction processing in the inner code is not performed, and the symbol is directly processed in the outer code correction processing unit 102. (Step 21)
0). When the number of error detection flags is not 0 in step 209, it is determined that the error cannot be corrected (step 208), the correction is not performed, and the erasure flag 104 is sent to the outer code correction processing unit together with the output 103 of the inner code correction processing unit.
If any of the syndrome values is not 0 in step 204, it is determined in step 205 whether the number of error detection flags exceeds (dmin-1), and if it exceeds, it is determined that the error cannot be corrected (step 208),
Erasure flag 1 together with the inner code without correction
04 to the outer code correction processing unit, and the outer code correction processing unit 1
Erasure correction is performed at 02. If the number of error detection flags is (dmin-1) or less in step 205, 2i
It is determined whether or not + j + 1 ≦ dmin is satisfied (step 206). If the condition of step 206 is satisfied, the inner code correction processing unit 101 performs correction (step 2).
07). In the error case of FIG. 6, 3 random errors and 2 erasure errors are corrected. When the condition of step 206 is not satisfied, it is determined that the inner code cannot be corrected (step 208), the inner code is not corrected, and it is sent to the outer code correction processing unit 102 together with the erasure flag 104, and the outer code correction processing unit 102 erases it. Correction is made (step 208).

By using the above-described correction algorithm in which random correction and erasure correction are mixed, the correction can be efficiently performed according to the number of errors and the number of error detection flags. Further, since the replacement process is also performed in advance, the present invention has a correction capability beyond the range of the equation (1).

Although the correction processing including the replacement processing function has been described in the above embodiment, the recording / reproducing apparatus having only the replacement processing function, or the random and erasure mixed correction function using the error detection flag is provided. It goes without saying that a recording / reproducing apparatus can be configured.

In the error detection of the above-mentioned inverse conversion (nm conversion), detection is performed in codeword units, but the error detection unit 9
By adopting the configuration shown in FIG. 8 as 2, the error at the connection point of the code word shown in FIG. 7 can be detected. 2 shown in FIG.
Although the codewords normally exist as codewords, they violate the rule that the minimum run length in the 8-14 conversion code is 2 when viewed as a code sequence at the connection point. By configuring the code word error detector 922 and the connection error detector 923 shown in FIG. 8, an error as a code word and a run length error at a code word connection point can be detected at the same time. The connection error detector 92
The error detection flag 142 (t = T-1) according to No. 3 is D-
The FF 924 also outputs the error detection flag 143 (t = T), and sets an error detection flag for both two codewords. The code word error detector 922 is configured by a ROM (Read Only Memory) of 14-bit address-1 bit output that outputs "1" for a normal code word and "0" for a non-normal code word. realizable. The connection error detector 923 indicates time t
= The maximum number of consecutive 6 bits of the same bit at the end of the code word of T-1 and the maximum number of 5 consecutive bits of the same bit at the beginning of the code word at time t = T are monitored. It can be constituted by an 11-bit address-1 bit output ROM which outputs "1" for a sequence and "0" for a code sequence that cannot occur.

As a method of detecting a connection error, it is also possible to monitor the run length with serial data before S / P conversion of the reproduced signal. It goes without saying that the detection method including this connection error can be applied to all the above processes.

[0023]

According to the present invention, means for detecting an error in a reproduced codeword sequence and means for replacing an erroneous codeword with a normal codeword are provided in the nm conversion decoder, and the error detection flag is used as an erasure flag. By performing error correction decoding in which random correction and erasure correction are mixed, it is possible to obtain the effects of reducing the burden of error correction decoding and improving the error correction capability of the system.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a digital VTR using the present invention.

FIG. 2 is a diagram showing an nm conversion decoder and an error correction decoder of the present invention.

FIG. 3 is a diagram showing a configuration of a product code in an error correction code.

FIG. 4 is a diagram showing a codeword replacement method.

FIG. 5 is a diagram showing an example of an error case.

FIG. 6 is a flowchart showing a correction algorithm of error correction decoding.

FIG. 7 is a diagram showing an error in a code sequence.

FIG. 8 is a diagram showing an error detection unit of the present invention.

[Explanation of symbols]

10 ... Analog / digital converter, 20 ... Error correction encoder, 30 ... Synchronization adder, 40 ... Mn conversion encoder, 5
0 ... Parallel / serial converter, 60 ... Recording / reproducing system, 7
0 ... Synchronous detector, 80 ... Serial / parallel converter, 9
0 ... Nm conversion decoder, 91 ... Permutation processing unit, 92 ... Error detection unit, 93 ... Nm conversion processing unit, 100 ... Error correction decoder, 101 ... Inner code correction processing unit, 102 ... Outer code correction Processing unit, 110 ... Digital / analog converter, 120
... input terminal, 130 ... output terminal, 140 ... error detection flag, 921 ... 14-bit D flip-flop, 922 ...
Code word error detector, 923 ... Connection error detector, 924 ...
1-bit D flip-flop, 925 ... OR circuit.

Claims (3)

[Claims] 1. A magnetic recording medium in which a digital signal is recorded in a code sequence obtained by converting an m-bit data word into an n-bit code word, and means for sequentially detecting the digital signal at a predetermined timing. Means for converting the signal detected at the predetermined timing into an n-bit code word, an error detection unit for detecting an error in the n-bit code word and outputting an error detection signal, and the n-bit code word Which has the closest Hamming distance with respect to, and which outputs another code word that brings the DSV of the code sequence closer to 0, and either the n-bit code word or the other code word based on the error detection signal. And an error correction means for performing error correction on the m-bit data word, and an output of the error correction means is an analog signal. Strange A digital signal recording / reproducing apparatus for converting and reproducing information. 2. The error correction means according to claim 1,
2i + j, where i is the random error correction number, j is the erasure error correction number, and d is the minimum Hamming distance based on the m-bit data word and the error detection signal.
A digital signal recording / reproducing apparatus having inner code correcting means for correcting the m-bit data word when + 1 ≦ d is satisfied. 3. The error correction means according to claim 1, further comprising means for detecting a connection error between the input m-bit data word and the immediately previous input m-bit data word,
A recording / reproducing apparatus for a digital signal, wherein the error detection signal is output to all code words relating to the connection error.