JPH07162286A - Level conversion circuit - Google Patents

Abstract

PURPOSE:To obtain a stable output logic signal by reducing the number of constitutional elements in a level conversion circuit. CONSTITUTION:When an 'L' level input logic signal is inputted from an input terminal In, a PMOS 31 is turned on. At the time, the potential level of a node N4 is approximately reaches ground potential VSS and the potential VSS is outputted from an output terminal Out as an 'H' level output logic signal. When an 'H' level input signal is inputted, the PMOS 31 is turned off and current is allowed to flow into power supply potential VEE through a PN junction type diode 32 and a resistor 33. The potential of the node N4 is dropped from the ground potential VSS only by a voltage drop generated in the PN junction part of the diode 32. The potential of the node N4 is outputted from the output terminal Out as an 'L' level output logical signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit used in a semiconductor integrated circuit in a computer or the like and converting an input logic signal into an output logic signal having a desired logic level and a desired logic amplitude. .

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. Reference 1: Seiji Kubo, "BiCMOS Technology" The Institute of Electronics, Information and Communication Engineers, p.48-49 FIG. 2 shows a conventional level conversion circuit. The level conversion circuit shown in FIG. 2 converts a complementary MOS transistor (hereinafter referred to as CMOS) level signal to an ECL (Emitter Coupling).
led logic) is a circuit for converting to a level signal, and reference 1
It is described in. This level conversion circuit
An inverter 10 having an OS for inverting the logic level of an input logic signal from an input terminal In;
And an electric current switching type logic circuit 20 which generates an ECL level output logic signal according to the output signal from and outputs it from the output terminal Out. The inverter 10 inputs an input logic signal to each gate, and has a CMOS P-channel field effect transistor (hereinafter referred to as PMOS) 11 having drains connected to each other at a node N1, and an N-channel field effect transistor (hereinafter referred to as PMOS). And 12). Current switching type logic circuit 20
Is two potential setting resistors 2 connected to the ground potential VSS.
1, 22 and a collector connected to the resistor 21 at the node N2, and a bipolar transistor 23 controlled by the output of the inverter 10 from the node N1 to open and close between the ground potential VSS and the power supply potential VEE. Is connected to the power supply potential VEE via the constant current source 24. Current switching type logic circuit 20
In addition, the resistor 22 has a base and a collector connected to the node N.
A bipolar transistor 25 connected at 3 and a bipolar transistor 26 having a base and a collector connected to the emitter of the bipolar transistor 25,
The emitter of the bipolar transistor 26 is connected to the power supply potential VEE via the constant current source 24. The source of the PMOS 11 in the inverter 10 is connected to the node N2, and the source of the NMOS 12 is connected to the power supply potential VEE. The output terminal O of this current switching logic circuit 20
The potential of the node N3 is output from ut.

Next, the operation of the level conversion circuit shown in FIG. 2 will be described. When a CMOS-level “H” signal is input to the input terminal In, the NMOS 12 is turned on and the bipolar transistor 23 is turned off. Although the bipolar transistor 23 is in the off state, the current switching type logic circuit 20 includes the constant current source 24.
The current flows through the ground potential Vss, the resistor 22, and the routes of the bipolar transistors 25 and 26. At this time, the voltage drop amount in the resistor 22 is output from the output terminal Out as an ECL level “L” signal. C on input terminal In
When a signal of MOS level "L" is input, the PMOS
11 is turned on, and the bipolar transistor 23 is turned on. Since the bipolar transistor 23 is in the ON state, the current flows to the constant current source through the ground potential Vss, the resistor 21, and the route of the bipolar transistor 23. At this time, since no current flows through the resistor 22 and the routes of the bipolar transistors 25 and 26, there is no voltage drop in the resistor 22. Therefore, the ground potential Vss is output from the output terminal Out as “H” of the ECL level signal.

[0004]

However, the conventional level conversion circuit has the following problems.
The number of elements that make up the circuit is large and the cost is high. Further, when formed in a semiconductor integrated circuit, the resistance values of the two resistors 21 and 23 vary due to process variations, and as a result, the logic level and logic amplitude of the output logic signal also vary. Further, when outputting an "H" level signal as the output logic signal, the load capacitance included in the circuit at the next stage is charged through the resistor 22, so that the propagation delay of rising becomes large. The level of the present invention, which has been solved by the above-mentioned prior art, is that there are many elements that constitute a circuit, that they are easily affected by process variations, and that the propagation delay at the rising edge is large when outputting an "H" level. A conversion circuit is provided.

[0005]

In order to solve the above-mentioned problems, a first invention is formed in a semiconductor substrate and driven by a power supply to convert the level of an input logic signal into an output logic signal of a desired level. The following measures are taken in the level conversion circuit that operates. That is, the level conversion circuit of the present invention includes an input field effect transistor that is turned on / off based on the voltage of the input logic signal input to the gate electrode to open / close the first current path, and is connected in series to the power supply. A logic amplitude setting element that is provided in a second current path that is connected to the first current path and that is connected in parallel to the first current path, and that sets a logic amplitude for the output logic signal based on opening and closing of the first current path. Is equipped with. A second aspect of the invention comprises the logic amplitude setting element of the first aspect of the invention as a PN junction type diode connected in series to the second current path. Third
In the invention, the logic amplitude setting element in the first invention is composed of a bipolar transistor in which a base electrode and a collector electrode are connected and the collector electrode and an emitter are connected in series to the second current path. . A fourth invention is the amplitude setting electric field in which the gate electrode is connected to the second current path and the drain and the source are connected in series to the second current path, in the logical amplitude setting element in the first invention. It consists of an effect transistor. In a fifth invention, the first current path in the first, second, third, or fourth invention is provided with a level shift element for setting a logic level of the output logic signal. A sixth aspect of the invention comprises the level shift element of the fifth aspect of the invention as a PN junction type diode connected in series to the first current path. 7th
According to the invention of claim 5, the level shift element in the fifth invention is constituted by a bipolar transistor in which a base electrode and a collector electrode are connected and the collector electrode and an emitter are connected in series to the first current path. An eighth aspect of the present invention is the level shifting element according to the fifth aspect of the present invention, wherein the level conversion element has a gate electrode connected to a first current path and a drain and a source connected in series to the first current path. It is composed of transistors.

[0006]

According to the first aspect of the invention, since the level conversion circuit is configured as described above, the input field effect transistor is
On / off operation is performed based on the voltage of the input logic signal input to the gate electrode to open / close the first current path. This opening / closing changes the current flowing through the second current path. The logic amplitude setting element sets the logic amplitude for the output logic signal according to the change in the current. According to the second invention, the logic amplitude setting element in the first invention is configured by a PN junction type diode. In the PN junction type diode,
Less affected by process variations. According to the third invention, the logic amplitude setting element in the first invention is composed of a bipolar transistor. In the bipolar transistor, the influence of process variation is small. According to the fourth invention, the logic amplitude setting element in the first invention is constituted by an amplitude setting field effect transistor. In the amplitude setting field effect transistor, the influence of process variation is small. According to the fifth invention, the first, second, third, or fourth
In the first invention, the first current path is provided with a level shift element for setting the logic level of the output logic signal. The level shift element sets the level of the output logic signal according to the current flowing through the first current path. According to the sixth invention, the level shift element in the fifth invention is constituted by a PN junction type diode. The PN junction type diode is less affected by process variations. According to the seventh invention, the level shift element in the fifth invention is composed of a bipolar transistor. In the bipolar transistor, the influence of process variation is small. According to the eighth invention, the level shift element in the fifth invention is constituted by a level converting field effect transistor. In the level conversion field effect transistor, the influence of process variation is small. Therefore, the above problem can be solved.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a level conversion circuit according to a first embodiment of the present invention. The level conversion circuit is a circuit that converts the amplitude of the input logic signal input from the input terminal In and outputs the output logic signal from the output terminal Out, and inputs the input logic signal to the gate to output the first current path. A logic amplitude which is connected in series between the ground potential VSS and the power source potential VEE and is provided in the forward direction in the second current path parallel to the first current path and the PMOS31 which is an input field effect transistor for opening and closing A PN junction diode 32 which is a setting element, and an output potential setting resistor 33 in which one of the two terminals is connected to the cathode of the PN junction diode 32 at a node N4 and the other is connected to the power supply potential VEE. Is equipped with. The output terminal Out of this level conversion circuit is connected to the node N4. FIG. 3 is a diagram showing the relationship of the potentials at the input terminal and the output terminal of FIG. 1, with reference to FIG.
The operation of the level conversion circuit of FIG. 1 will be described. Input terminal In
When the “L” level of the input logic signal is input to
The OS 31 is turned on. As a result, the output terminal Ou
From t, a potential substantially equal to the ground potential VSS is output as "H", as shown in FIG. When the input logic signal level "H" is input to the input terminal In, the PMOS 31 is turned off. At this time, ground potential VSS and power supply potential VEE
Between the PN junction of the PN junction diode 32 and the resistor 33.
A current determined by the current flows, and the potential of the node N4 becomes a potential lower than the ground potential VSS by the voltage drop generated by the PN junction of the PN junction diode 32. The potential of the node N4 at this time is output from the output terminal Out as the output logic signal “L”. That is, the level conversion circuit of FIG. 1 converts an input logic signal and generates an output logic signal having a logic amplitude of a voltage drop caused by the PN junction of the PN junction diode 32. As described above, in this embodiment, the PN junction diode 32 for setting the logical amplitude is set.
On the other hand, since the PMOS 31 opens and closes the first current path, a level conversion circuit that converts the logical amplitude of the logical signal is realized with a configuration having a small number of elements. In addition, FIG.
Unlike PN, the element that sets the logic amplitude does not use a resistor.
Since it is the junction type diode 32, it is unlikely to be affected by process variations. Therefore, the logic amplitude of the output logic signal for each product is stable. Further, when the output signal is "H", the load capacitance of the next stage circuit is not charged through the resistor, so that the propagation delay can be reduced. Second Embodiment FIG. 4 is a circuit diagram showing a level conversion circuit according to a second embodiment of the present invention. This level conversion circuit is a circuit that converts the logic level and the logic amplitude of the input logic signal input from the input terminal In and outputs a desired output logic signal from the output terminal Out, and inputs the input logic signal to the gate. Then first
A field effect transistor PMOS 41 for opening and closing the current path, and a PN junction type diode 42, which is a level shift element provided in series in the first current path,
2 connected in series between the ground potential VSS and the power supply potential VEE and provided in series in a second current path parallel to the first current path
PN junction type diodes 43 and 44 for setting logic amplitudes
And an output potential setting resistor 45, one of the two terminals of which is connected to the cathode of the PN junction diode 44 at the node N5 and the other of which is connected to the power supply potential VEE. Three PN junction type diodes 42, 43, 44
Have the same characteristics, for example, and the PN junction diode 42
The anode of is connected to the drain of the PMOS 41, and the cathode is connected to the node N5. The anode of the PN junction diode 43 in series is connected to the ground potential VSS, and the cathode of the PN junction diode 44 is connected to the power supply potential VEE via the node N5 and the resistor 45. That is, the PN junction diode 42 is provided in the first current path of the level conversion circuit in the first embodiment, and the output terminal Out of this level conversion circuit is connected to the node N5.

Next, the operation of the level conversion circuit shown in FIG. 4 will be described. When the “L” level of the input logic signal is input to the input terminal In, the PMOS 41 is turned on, and the current has the first current path having the PN junction diode 42 and the PN junction diodes 43 and 44. Flows to the second current path. As a result, the potential of the node N5 becomes three PN junction type diodes 42, 4 with respect to the ground potential VSS.
The potential drops due to the combined voltage drop of the PN junctions 3, 44, and this potential is output as "H" from the output terminal Out. That is, by providing the PN junction type diode 42, the "H" level of the output logic signal is shifted. The input logic signal level "H" is input to the input terminal In.
Is input, the PMOS 41 is turned off. At this time, a current determined by the PN junctions of the PN junction diodes 43 and 44 and the resistor 45 flows between the ground potential VSS and the power supply potential VEE, and the potential of the node N5 is two PN junction diodes from the ground potential VSS. The potential becomes lower by the voltage drop caused by the PN junction of 43 and 44. The potential of the node N5 at this time is output from the output terminal Out as the output logic signal “L”. That is, the level conversion circuit of FIG. 4 converts the "H" logic level of the output logic signal, and the "H" level potential and the voltage drop of the PN junction of the PN junction type diodes 43 and 44 cause "." L "
The output logic signal is generated by setting the potential of and the logic amplitude. As described above, in the present embodiment, with respect to the PN junction type diodes 43 and 44 which set the logic amplitude, the PN junction type diode 42 which sets the logic level of "H" of the output logic signal in cooperation with them. Is provided. Therefore, in this embodiment, a level conversion circuit for converting the logic level and the logic amplitude of a logic signal is realized with a configuration having a small number of elements. Further, since the elements for setting the logic amplitude and the logic level are the PN junction type diodes 42, 43 and 44 without using the resistors, they are hardly affected by the process variation. for that reason,
The amplitude of the output logic signal for each product becomes stable. Further, when the output signal is "H", the load capacitance of the next-stage circuit is not charged through the resistor, so that a high-speed level conversion circuit can be obtained.

Third Embodiment FIG. 5 is a circuit diagram showing a level conversion circuit according to a third embodiment of the present invention. This level conversion circuit is a circuit for converting the logic amplitude of the input logic signal input from the input terminal In and outputting the output logic signal from the output terminal Out, as in the first embodiment. A PMOS 51, which is an input field effect transistor that opens and closes the first current path by inputting to the gate, and a second current path connected in series between the ground potential VSS and the power supply potential VEE and parallel to the first current path. And a bipolar transistor 52, which is a logical amplitude setting element, and an output potential setting resistor having one of two terminals connected to the emitter of the bipolar transistor 52 at a node N6 and the other connected to the power supply potential VEE. 53
And are equipped with. The base and collector of the bipolar transistor 52 are short-circuited, and the collector of the bipolar transistor 52 is connected to the ground potential VSS. The output terminal Out of this level conversion circuit is connected to the node N6.

Next, the operation of the level conversion circuit shown in FIG. 5 will be described. When the “L” level of the input logic signal is input to the input terminal In, the PMOS 51 is turned on. As a result, a potential substantially equal to the ground potential VSS is output as "H" from the output terminal Out. When the input logic signal level “H” is input to the input terminal In, the PMOS 51
Is turned off. At this time, a current determined by the base-emitter voltage VBE of the bipolar transistor 52 and the resistor 53 flows between the ground potential VSS and the power supply potential VEE, and the potential of the node N6 is lower than the ground potential VSS by the voltage VBE. Become. The potential of the node N6 at this time is output from the output terminal Out as "L" of the output logic signal. That is, the level conversion circuit of FIG. 5 converts the input logic signal and generates the output logic signal with the voltage VBE as the logic amplitude. As described above, in the present embodiment, the PMOS 51 opens and closes the first current path with respect to the base-emitter voltage VBE of the bipolar transistor 52 that sets the logic amplitude. A level conversion circuit that converts the logical amplitude of a signal is realized. Further, since the element for setting the logical amplitude is the bipolar transistor 52 without using the resistor as in the first embodiment,
Less susceptible to process variations. Therefore, the amplitude of the output logic signal for each product is stable. Further, when the output signal is "H", the load capacitance of the next-stage circuit is not charged through the resistor, so that a high-speed level conversion circuit can be obtained.

Fourth Embodiment FIG. 6 is a circuit diagram showing a level conversion circuit according to a fourth embodiment of the present invention. Similar to the first and third embodiments, this level conversion circuit is a circuit that converts the logic amplitude of the input logic signal input from the input terminal In and outputs a desired output logic signal from the output terminal Out. , A PMOS 61 which is an input field effect transistor for opening and closing the first current path by inputting an input logic signal to the gate, and is connected in series between the ground potential VSS and the power supply potential VEE and is parallel to the first current path. PM which is a logical amplitude setting element provided in the second current path
OS62 and one of the two terminals is PMOS62
Of the power supply potential V
And an output potential setting resistor 63 connected to EE. The gate and drain of the PMOS 62 are short-circuited, and the source of the PMOS 62 is connected to the ground potential VSS. The output terminal Out of this level conversion circuit is the node N
Connected to 7.

Next, the operation of the level conversion circuit shown in FIG. 6 will be described. When the “L” level of the input logic signal is input to the input terminal In, the PMOS 61 is turned on. As a result, a potential substantially equal to the ground potential VSS is output as "H" from the output terminal Out. When the input logic signal level "H" is input to the input terminal In, the PMOS 61 is turned off. At this time, the ground potential VSS and the power supply potential V
A current determined by the threshold voltage Vth of the PMOS 62 and the resistor 63 flows between EE, and the potential of the node N7 is the ground potential Vth.
The potential is lower than SS by the threshold voltage Vth. The potential of the node N7 at this time is output from the output terminal Out as "L" of the output logic signal. That is, the level conversion circuit of FIG. 6 converts the input logic signal and generates the output logic signal with the threshold voltage Vth as the logic amplitude. As described above, in the present embodiment, the PMOS 61 opens and closes the first current path with respect to the threshold voltage Vth of the PMOS 62 that sets the logical amplitude, so the logical amplitude of the logical signal is converted with a configuration having a small number of elements. It realizes a level conversion circuit that does. Further, the element for setting the logical amplitude does not use the resistor as in the first and third embodiments, and is the PMOS 62, so that it is hardly affected by the process variation. Therefore, the amplitude of the output logic signal for each product is stable. Further, when the output signal is "H", the load capacitance of the next-stage circuit is not charged through the resistor, so that a high-speed level conversion circuit can be obtained. The present invention is
The present invention is not limited to the above embodiment, and various modifications are possible. The following are examples of such modifications.

(1) Element PM for opening and closing the first current path
Even if the OSs 31, 41, 51, 61 are composed of, for example, NMOS, they open and close according to the potential of the input logic signal,
The same effect as the fourth embodiment is obtained. (2) The level shift element in the second embodiment is P
Not limited to the N-junction type diode 42, a bipolar transistor in which the base electrode and the collector electrode are connected and the collector electrode and the emitter are connected in series to the first current path, or the gate electrode is connected to the first current path And a drain and a source connected in series to the first current path may be a level converting field effect transistor. (3) PN junction type diode 4 in the second embodiment
The connection position of 2 is the source of the PMOS 41 and the ground potential VSS.
In between, it may be connected in the forward direction. (4) The number of the amplitude setting elements in the first to fourth embodiments can be freely selected according to the desired logical amplitude. (5) In the second embodiment, the number of level shift elements and the number of amplitude setting elements can be freely selected according to the desired level and amplitude of the output logic signal.

[0014]

As described in detail above, according to the first aspect of the invention, an input field effect transistor for opening and closing the first current path with the potential of the input logic signal, and the input field effect transistor connected in parallel to the first current path. Since the logic amplitude setting element provided in the second current path is provided, a level conversion circuit for converting the logic amplitude can be realized with a configuration having a small number of elements, and the cost can be reduced. Further, it is possible to reduce the delay time generated at the rising edge of the output logic signal of "H" level, and it is possible to realize a high-speed level conversion circuit. According to the second invention, the logic amplitude setting element in the first invention is constituted by a PN junction type diode. The PN junction type diode has less influence on the process variation at the time of manufacturing as compared with the resistor formed in the semiconductor substrate, for example. Therefore, it is possible to realize a level conversion circuit in which the logic amplitude of the output logic signal is stable. Third
According to the invention, since the logic amplitude setting element in the first invention is composed of the bipolar transistor, it is possible to realize a level conversion circuit in which the logic amplitude of the output logic signal is stable as in the second invention. According to the fourth invention, since the logic amplitude setting element in the first invention is composed of the amplitude setting field effect transistor, the logic amplitude of the output logic signal is stable as in the second and third inventions. A level conversion circuit can be realized. According to the fifth invention, first, second, third, fourth
Since the level shift element is provided in the first current path in the invention, the level conversion circuit for setting the logic amplitude of the output logic signal and the logic level can be realized with a simple configuration. According to the sixth invention, since the level shift element in the fifth invention is composed of the PN junction type diode, it is possible to realize a level conversion circuit having a stable logic level of the output logic signal. According to the seventh invention, since the level shift element in the fifth invention is composed of bipolar transistors, it is possible to realize a level conversion circuit in which the logic level of the output logic signal is stable, as in the sixth invention. According to the eighth invention, since the level shift element in the fifth invention is constituted by the level converting field effect transistor, a stable logic level of the output logic signal is obtained as in the sixth and seventh inventions. A conversion circuit can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a level conversion circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional level conversion circuit.

FIG. 3 is a diagram showing a potential relationship between an input terminal and an output terminal of FIG.

FIG. 4 is a circuit diagram showing a level conversion circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a level conversion circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a level conversion circuit according to a fourth embodiment of the present invention.

[Explanation of symbols]

31, 41, 51, 61 Input field effect transistor (PMOS) 32, 43, 44 Logic amplitude setting element (PN junction type diode) 42 Level shift element (PN junction type diode) 52 Logic amplitude setting element (bipolar transistor) 62 Logic amplitude setting element (field effect transistor) In Input terminal Out output terminal

Claims (8)

[Claims] 1. A level conversion circuit formed in a semiconductor substrate and driven by a power supply to convert the level of an input logic signal into an output logic signal of a desired level, the voltage of the input logic signal input to a gate electrode. An input field-effect transistor that is turned on and off based on the above, and that opens and closes the first current path, and a second current path that is connected in series to the power supply and that is connected in parallel to the first current path. And a logic amplitude setting element that sets a logic amplitude for the output logic signal based on opening and closing of the first current path. 2. The level conversion circuit according to claim 1, wherein the logic amplitude setting element is composed of a PN junction type diode connected in series to the second current path. 3. The logic amplitude setting element is composed of a bipolar transistor having a base electrode and a collector electrode connected to each other and a collector electrode and an emitter connected in series to the second current path. The level conversion circuit according to item 1. 4. The logic amplitude setting element is composed of an amplitude setting field effect transistor having a gate electrode connected to a second current path and a drain and a source connected in series to the second current path. The level conversion circuit according to claim 1, wherein 5. The level conversion circuit according to claim 1, 2, 3 or 4, wherein the first current path is provided with a level shift element for setting a logic level of the output logic signal. 6. The level conversion circuit according to claim 5, wherein the level shift element comprises a PN junction type diode connected in series to the first current path. 7. The level shift element is composed of a bipolar transistor in which a base electrode and a collector electrode are connected and a collector electrode and an emitter are connected in series to the first current path. 5. The level conversion circuit described in 5. 8. The level shift element comprises a level converting field effect transistor having a gate electrode connected to a first current path and a drain and a source connected in series to the first current path. 6. The level conversion circuit according to claim 5, which is characterized in that