JPH07162009A - Thin film transistor - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a thin film transistor having a long life by ensuring good electrical deterioration resistance. [Structure] NMOS thin film transistor 10 and PMOS
Thin film transistor 20 and each thin film transistor 10, 2
0 semiconductor thin films 12, 22 and gate insulating films 13, 23 formed between the gate electrodes 14, 24
In the OS field effect thin film transistor, the gate insulating films 14 and 24 are formed of silicon nitride layers 13b and 2 having high breakdown voltage.
3b and silicon oxide layers 13a and 13b formed above and below this layer and having a high barrier energy for carrier injection.
And a three-layer structure having 13c and 23c. Electrons are less likely to be accumulated in the vicinity of the gate electrode side surfaces of the gate insulating films 13 and 23 even after being used for a long time, and an electrically excellent deterioration resistance characteristic is secured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor such as a CMOS field effect thin film transistor.

[0002]

2. Description of the Related Art Conventionally, as a CMOS field effect type thin film transistor, for example, as shown in FIG. 4, an NMOS thin film transistor 110 and a PMOS are formed on a glass substrate 100.
The thin film transistor 120 is provided, and the gate insulating films 113 and 123 are provided between the semiconductor thin films 111 and 121 and the gate electrodes 112 and 122 of the thin film transistors 110 and 120, respectively.
Are formed, and the gate insulating films 113 and 123 are formed.
The silicon oxide layers 114 and 124 formed on the semiconductor thin films 111 and 121, and the silicon oxide layers 114 and 124.
A two-layer structure composed of silicon nitride layers 115 and 125 formed on 124 has been proposed by the present applicant (Japanese Patent Application No. 3-334596). In this conventional thin film transistor, the barrier energy against carrier inflow from the channel regions 111a and 121a of the semiconductor thin films 111 and 121 is high (the trap level is small), and a silicon oxide layer that forms a good interface with the semiconductor thin films 111 and 121. Since 114 and 124 are formed on the semiconductor thin films 111 and 121, and the silicon nitride layers 115 and 125 having a high breakdown voltage are formed on the silicon oxide layers 114 and 124, the gate insulating films 113 and 123 are formed on the semiconductor thin films 111 and 121.
A good interface with 121 can be formed, and the dielectric strength of the gate insulating films 113 and 123 can be increased.

[0003]

However, in the above conventional CMOS field effect type thin film transistor, for example, the initial characteristics of the NMOS thin film transistor 110 and the PMOS thin film transistor 120 of this thin film transistor are examined, and after that, the CMOS field effect type thin film transistor is shown in FIG. After holding the connection state shown in (a) for a long time to perform a use test, and further holding the CMOS electrolytic effect type thin film transistor in the connection state shown in FIG. Thin film transistor 11
When the characteristics of 0 and 120 are examined, the characteristics of the NMOS thin film transistor 110, which had the initial characteristics shown in FIG. 5A, deteriorate as a result of long-term use as shown in FIG. 5C. The characteristics of the PMOS thin film transistor 120 having the initial characteristics shown in FIG.
As shown in (d), there is a problem that it deteriorates due to long-term use. That is, FIGS. 5C and 5D
In the characteristic shown in (1), the threshold voltage V _G of the gate voltage V _G in each of the thin film transistors 110 and 120 is
_TH (here, V _TH is the gate voltage when the drain currents I _DN and I _DP are about 10 ⁻⁸ Å, respectively), but FIGS. 5 (a) and 5 (b) show deterioration due to long-term use. Compared with the initial characteristics shown in (1), the shift is largely in the + direction.
Such deterioration occurs because, when the conventional CMOS field effect thin film transistor is connected as shown in FIG. 6 (a), the gate electrode 12 from the channel region 121 a of the semiconductor thin film 121 inside the PMOS thin film transistor 120.
This is because an electric field is generated in two directions and if this connection state is maintained for a long time, electrons are accumulated in the vicinity of the surface of the silicon nitride layer 125 on the gate electrode 122 side. Similarly, when the conventional CMOS field effect thin film transistor is connected as shown in FIG. 6B, an electric field is generated in the NMOS thin film transistor 110 from the channel region 111a of the semiconductor thin film 111 toward the gate electrode 112. If the connection state is maintained for a long time, electrons are accumulated in the vicinity of the surface of the silicon nitride layer 115 on the gate electrode 112 side, and the above deterioration occurs. The present invention has been made in view of such a conventional problem, and an object thereof is to provide a thin film transistor having an electrically favorable deterioration resistance characteristic and a long life.

[0004]

To achieve the above object, the invention according to claim 1 is a thin film transistor comprising a gate insulating film formed between a conductor thin film and a gate electrode, wherein the gate insulating film is An intermediate layer with high pressure resistance,
A three-layer structure is formed above and below this intermediate layer and has an upper layer and a lower layer having high barrier energy against carrier injection. Preferably, the intermediate layer is a layer made of silicon nitride, and the upper layer and the lower layer are layers made of silicon oxide (claim 2). More preferably, the intermediate layer has a thickness larger than that of the upper and lower layers (the invention according to claim 3).

[0005]

According to the first aspect of the present invention, the gate insulating film formed between the semiconductor thin film and the gate electrode is formed on the intermediate layer having a high breakdown voltage and above and below this intermediate layer to prevent the barrier energy against carrier injection. Due to the three-layer structure having a high lower layer and a high upper layer, a layer having a high barrier energy for carrier injection, that is, a layer having a small trap level is arranged not only on the semiconductor thin film side but also on the gate electrode side. Electrons are less likely to be trapped (captured), and thus electrons are less likely to be accumulated in the vicinity of the surface of the gate insulating film on the gate electrode side even when used for a long time.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. In the description of each embodiment, the same parts are designated by the same reference numerals, and the duplicated description will be omitted. FIG. 1 shows a first embodiment in which the thin film transistor according to the present invention is applied to a CMOS field effect thin film transistor. As shown in FIG. 1, the CMOS field effect type thin film transistor according to the first embodiment includes an NMOS thin film transistor 10 and a PMOS thin film transistor 20 formed on the same glass substrate 1.

NMOS thin film transistor 10 and PMO
The S thin film transistors 20 respectively include base layers 11 and 21 made of silicon oxide formed on the glass substrate 1,
Semiconductor thin films 12 and 22 made of a polysilicon thin film patterned by crystallizing an amorphous silicon thin film at predetermined positions on the upper surfaces of the base layers 11 and 21, and the base layers 11 and 12.
1 and the gate insulating films 13 and 23 formed on the entire upper surfaces of the semiconductor thin films 12 and 21, and the gate insulating films 13 and 23.
Gate electrodes 14 and 24 made of chromium patterned at predetermined portions on the upper surfaces of the gate insulating films 13 and 23, and interlayer insulating films 15 and 25 made of silicon nitride formed on the entire upper surfaces of the gate electrodes 14 and 24. Is equipped with.

The semiconductor thin film 12 of the NMOS thin film transistor 10 has a channel region 12a formed in the central portion,
Source / drain regions 12b and 12b, which are n-type high-concentration impurity regions formed on both sides, and both regions 12b and
12D and n-type low-concentration impurity regions 12c and 12c formed between the channel regions 12a.
ty Doped Drain) structure. The gate electrode 1
Reference numeral 4 denotes the channel region 1 on the upper surface of the gate insulating film 13.
It is formed at a location corresponding to 2a. On the other hand, PMOS
The semiconductor thin film 22 of the thin film transistor 20 includes a channel region 22a formed in the center and source / drain regions 22 which are p-type high-concentration impurity regions formed on both sides.
b and 22b. The gate electrode 24 is formed on the upper surface of the gate insulating film 23 at a position corresponding to the channel region 22a.

The gate insulating films 13 and 23 and the interlayer insulating films 15 and 25 of the thin film transistors 10 and 20 have contact holes 16 and 16 which communicate with a part of the upper surfaces of the source / drain regions 12b and 12b and 22b and 22b, respectively. Two
6, 26 are formed. Each contact hole 16,
Source / drain electrodes 17 and 27 that are electrically connected to the source / drain regions 12b and 22b are formed by patterning in 26 and at predetermined positions on the upper surfaces of the interlayer insulating films 15 and 25.

The gate insulating films 13 and 23 of the thin film transistors 10 and 20 are composed of silicon nitride layers (intermediate layers) 13b and 23b having a high breakdown voltage and the silicon nitride layer 13 respectively.
b, 23b formed above and below the channel region 12
It has a three-layer structure including silicon oxide layers (lower layers) 13a and 23a having high barrier energy against carrier injection from a and 22a and silicon oxide layers (upper layers) 13c and 23c. That is, each gate insulating film 13, 2
3 denotes a silicon oxide layer (lower layer) 13a formed on the entire upper surfaces of the base layers 11 and 21 and the semiconductor thin films 12 and 21,
23a and silicon nitride layers (intermediate layers) 13b and 23 formed on the entire upper surfaces of the silicon oxide layers 13a and 23a.
b, and silicon oxide layers (upper layers) 13c and 23c formed on the entire upper surfaces of the silicon nitride layers 13b and 23b. The gate electrodes 14 and 24 are formed at predetermined locations on the upper surfaces of the silicon oxide layers 13c and 23c of the gate insulating films 13 and 23. Silicon oxide layer 13
The a, 23a and the silicon oxide layers 13c, 23c are formed to have a film thickness of about 200 Å by a sputtering method. This film thickness is too thick for the tunnel current to flow and is so thin as not to have a fatal effect on the gate capacitance.

The CMO according to the first embodiment having the above configuration
In order to investigate the deterioration of the S field effect type thin film transistor due to long-term use, first, as in the case of the above-mentioned conventional technique, the initial characteristics of the NMOS thin film transistor 10 and the PMOS thin film transistor 20 are investigated, and then the CMOS field effect type thin film transistor is examined. In the connected state shown in FIG. 6A, a usage test is performed by holding the connection state for a long time.
After the field effect type thin film transistor was held in the connected state shown in FIG. 6B for a long time and a usage test was performed, the characteristics of the thin film transistors 10 and 20 were examined again. As a result, regarding the NMOS thin film transistor 10, FIG.
The initial characteristics shown in (a) and the characteristics after long-time use shown in FIG. 2 (c) are obtained, and for the PMOS thin film transistor 20, the initial characteristics shown in FIG. 2 (b) and the long time shown in FIG. 2 (d). The properties after use were obtained.

As is apparent from FIGS. 2 (a) and 2 (c), the NMOS thin film transistor 10 is hardly deteriorated by long-term use. That is, in the characteristics after long-time use shown in FIG. 2C, the threshold voltage V _G of the gate voltage V _G in the thin film transistor 10 is used.
_TH is slightly shifted in the + direction (to the right) as compared with the initial characteristics shown in FIG. Comparing FIG. 2C with FIG. 5C, the NMOS thin film transistor 10 has a higher degree of deterioration than the NMOS thin film transistor 110 of the conventional CMOS field effect thin film transistor shown in FIG. (Ie,
The degree to which the threshold voltage V _TH of the gate voltage V _G shifts in the + direction) is much smaller. Also, FIG.
As is clear from (b) and (d), the PMOS thin film transistor 20 also shows little deterioration due to long-term use.
That is, in the characteristics after long-time use shown in FIG.
The threshold voltage V _TH of the gate voltage V _G in each thin film transistor 20 is slightly shifted in the + direction as compared with the initial characteristic shown in FIG. Then, comparing FIG. 2D and FIG. 5D, P
The MOS thin film transistor 10 is the conventional C shown in FIG.
Compared with the PMOS thin film transistor 120 of the MOS field effect thin film transistor, the degree of deterioration due to long-term use is much smaller.

Thus, each thin film transistor 10, 20
Of the gate insulating films 13 and 2 formed between the semiconductor thin films 12 and 22 and the gate electrodes 14 and 24 is small.
3 are silicon nitride layers 13b and 23b having a high breakdown voltage and silicon oxide layers 13a and 23 formed above and below the silicon nitride layer and having a high barrier energy against carrier injection.
With a three-layer structure having a and the silicon oxide layers 13c and 23c, the silicon oxide layer having a high barrier energy for carrier injection, that is, having a small trap level is provided not only on the semiconductor thin films 12 and 22 side but also the gate electrode
Electrons are less likely to be trapped (captured) because they are also disposed on the 3rd and 24th sides, which makes it difficult for electrons to accumulate near the gate electrode side surfaces of the silicon oxide layers 13a and 23a even when used for a long time. is there. As described above, according to the first embodiment, it is possible to secure the electrically excellent deterioration resistance characteristic of the CMOS field effect type thin film transistor, and thereby to prolong the life thereof.

The characteristics of the NMOS thin film transistor 10 shown in FIG. 2 (c) after long-term use and P shown in FIG. 2 (d).
Comparing the characteristics of the MOSO thin film transistor 20 after long-term use, the degree of deterioration of the NMOS thin film transistor 10 is smaller than that of the PMOS thin film transistor 20. The reason is that the semiconductor thin film 12 of the NMOS thin film transistor 10 has the above LDD structure,
This is because the semiconductor film 2 of the PMOS thin film transistor 20 does not have the LDD structure. That is, by using the LDD structure for the semiconductor thin film 12 of the NMOS thin film transistor 10, deterioration can be further prevented.

Next, a CMOS electrolytic effect type thin film transistor according to a second embodiment of the present invention will be described with reference to FIG. In the CMOS field effect thin film transistor of the first embodiment, the NMOS thin film transistor 10 and the PMOS thin film transistor are used.
While the gate electrodes 14 and 24 of the thin film transistor 20 are arranged above the semiconductor thin films 12 and 22,
In the CMOS field effect thin film transistor of the second embodiment, the gate electrodes 14 and 24 of the NMOS thin film transistor 10A and the PMOS thin film transistor 20A are arranged below the semiconductor thin films 12 and 22. That is,
The NMOS thin film transistor 10A and the PMOS thin film transistor 20A of the CMOS field effect thin film transistor according to the second embodiment respectively include the gate electrodes 14 and 24 formed at predetermined locations on the upper surface of the glass substrate 1 and the glass substrate 1 and the gate electrodes 14 and 24. Of the gate insulating films 13 and 23 formed on the entire upper surface of the
Semiconductor thin films 12 and 22 formed at predetermined locations on the upper surface of
And gate insulating films 13 and 23 and semiconductor thin films 12 and 22
And interlayer insulating films 15 and 25 formed on the entire upper surface of.

Further, each thin film transistor 10A, 20A
In the interlayer insulating films 15 and 25, contact holes 16 and 26 communicating with a part of the upper surfaces of the source / drain regions 12b and 22b are formed. Source / drain electrodes 17 and 27 electrically connected to the source / drain regions 12b and 22b are formed in the contact holes 16 and 26 and at predetermined positions on the upper surfaces of the interlayer insulating films 15 and 25. The gate insulating films 13 and 23 of the thin film transistors 10A and 20A have a three-layer structure as in the first embodiment. That is, each gate insulating film 13, 23
Silicon oxide layers (lower layers) 13a and 23a are formed on the entire upper surfaces of the glass substrate 1 and the gate electrodes 14 and 24,
Silicon nitride layers (intermediate layers) 13b and 23b are formed on the entire upper surfaces of the silicon oxide layers 13a and 23a, and the silicon oxide layer (upper layer) 1 is formed on the entire upper surfaces of the silicon nitride layers.
3c and 23c are formed. Each gate insulating film 13,
The semiconductor thin films 12 and 22 are formed at predetermined locations on the upper surfaces of the silicon oxide layers 13c and 23c of 23.

Also in the CMOS field effect type thin film transistor of the second embodiment, the deterioration of the thin film transistors 10A and 20A is reduced as in the case of the first embodiment.
Therefore, also according to the second embodiment, it is possible to secure the electrically excellent deterioration resistance characteristic of the CMOS electrolytic effect type thin film transistor, and thereby to prolong the life thereof.

The thin film transistor according to the present invention can be applied to thin film transistors other than the CMOS field effect type thin film transistor. Further, in each of the above embodiments, the intermediate layer having a high breakdown voltage among the gate insulating films 13 and 23 is the silicon nitride layers 13b and 23b. However, the intermediate layer is made of a substance having a high breakdown voltage other than silicon nitride. Good. In addition, in each of the above embodiments, each of the gate insulating films 13 and 2
3, the lower and upper layers formed above and below the silicon nitride layers 13b and 23b and having high barrier energy against carrier injection from the channel regions 12a and 22a are the silicon oxide layers 13a and 23a and the silicon oxide layers 13c, respectively. However, the lower layer and the upper layer may be made of a material having a high barrier energy other than silicon oxide.

[0019]

As described above, according to the present invention, the gate insulating film formed between the semiconductor thin film and the gate electrode is formed on the intermediate layer having a high breakdown voltage and above and below this intermediate layer. Due to the three-layer structure having the lower layer and the upper layer having high barrier energy for carrier injection,
Since the layer with high barrier energy for carrier injection, that is, the layer with few trap levels is arranged not only on the semiconductor thin film side but also on the gate electrode side, it becomes difficult for electrons to be trapped (trapped), which makes it difficult to use for a long time. However, it is difficult for electrons to accumulate near the surface of the gate insulating film on the side of the gate electrode. Therefore, it is possible to electrically secure good deterioration resistance characteristics, and thereby to prolong the life.

[Brief description of drawings]

FIG. 1 is a sectional view showing a main part of a CMOS field effect type thin film transistor according to a first embodiment of the present invention.

2A is a diagram showing initial characteristics of an NMOS thin film transistor of the CMOS field effect thin film transistor shown in FIG. 1. FIG. FIG. 1B is a diagram showing the characteristics of the same NMOS thin film transistor as in FIG. 1A after long-term use.
(C) is a figure which shows the initial characteristic of the PMOS thin film transistor of the CMOS field effect type thin film transistor shown in FIG. FIG. 1D is a diagram showing characteristics of the same PMOS thin film transistor as in FIG. 1C after long-term use.

FIG. 3 is a sectional view showing an essential part of a CMOS field effect thin film transistor according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a main part of a conventional CMOS field effect thin film transistor.

5A is a diagram showing initial characteristics of an NMOS thin film transistor of the conventional CMOS field effect type thin film transistor shown in FIG. (B) is the same NMOS as FIG. 5 (a)
It is a figure which shows the characteristic after long-time use of a thin film transistor. (C) is a figure which shows the initial characteristic of the PMOS thin film transistor of the conventional CMOS field effect type thin film transistor shown in FIG. 5D is a diagram showing the characteristics of the same PMOS thin film transistor as in FIG. 5C after long-term use.

FIG. 6A shows a circuit connection diagram for performing a use test of a PMOS thin film transistor of a CMOS field effect type thin film transistor. (B) shows a circuit connection diagram for performing a use test of an NMOS thin film transistor of a CMOS field effect type thin film transistor.

[Explanation of symbols]

 12, 22 semiconductor thin film 13, 23 gate insulating film 13a silicon oxide layer (lower layer) 13b silicon nitride layer (intermediate layer) 13c silicon oxide layer (upper layer) 14, 24 gate electrode

Claims (3)

[Claims] 1. A thin film transistor comprising a gate insulating film formed between a semiconductor thin film and a gate electrode, wherein the gate insulating film is formed on an intermediate layer having a high breakdown voltage, and formed on and under the intermediate layer to prevent carrier injection. A thin film transistor having a three-layer structure having an upper layer and a lower layer having high barrier energy. 2. The thin film transistor according to claim 1, wherein the intermediate layer is a layer made of silicon nitride, and the upper layer and the lower layer are layers made of silicon oxide. 3. The thin film transistor according to claim 1, wherein the intermediate layer has a thickness larger than that of the upper layer and the lower layer.