JPH07161824A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor device in a CMOS device, which realizes high integration, high reliability, and high speed operation by reducing the element area and the stress caused by the gate material. In a CMOS in which p-type / n-type polysilicon gates (5, 6) are directly connected, the gate on the active region (110) is titanium nitride (7) / silicon dioxide (8) / polysilicon (5). , 6), and the gate in the peripheral region has a titanium nitride / polysilicon double layer structure. [Effect] Silicon dioxide (8) acts as an intermediate buffer, reduces stress on the gate insulating film, and realizes high reliability and high speed operation. The titanium nitride (7) can suppress the fluctuation of the threshold voltage due to the diffusion of impurities, reduce the device area, and realize a high degree of integration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a semiconductor element of submicron level.

[0002]

2. Description of the Related Art (1) Tetsuo Ito et al., "Prototype of 20 ps 0.1 μm CMOS device operating at room temperature" TECHNICAL REPORT OF IEICE. SDM92-137 (1993-01) p.1-6 (2) JRPfiester et al "A TiN strapped polysilicon gate cobalt saliside CMOS process" IEDM (1990) p. 241-248. Si-MOS semiconductor devices are being advanced in speed and integration due to element miniaturization. Then, in order to increase the operating current of the sub-micron level CMOS circuit and further speed it up, both the n-channel and p-channel MOS transistors are of the surface channel type as shown in the above-mentioned reference 1, and the so-called A dual gate (n-type polysilicon is used for the gate electrode of the n-channel MOS transistor and p-type polysilicon is used for the gate electrode of the p-channel MOS transistor) is used. Further, in order to reduce the gate resistance, low resistance silicide is deposited on each gate polysilicon. In the layout design of such a gate structure, as shown in FIG.
The type polysilicon 6 and the p-type polysilicon 5 are separated, a low-resistance silicide 17 is deposited, and then electrically connected to each other via the metal layer 11. This is because when the n-type polysilicon 6 and the p-type polysilicon 5 are physically directly joined,
This is because the impurity interdiffusion occurs in the silicide and the desired threshold voltage cannot be realized. That is, the first conventional example (FIG. 2) has a problem that the element area cannot be reduced because the gates 5 and 6 are separated. On the other hand, in the above-mentioned reference 2, as shown in FIG. 3, in a dual gate CMOS, titanium nitride (TiN) 7 is deposited instead of silicide, and the n-type polysilicon 6 and the p-type polysilicon 5 are physically directly attached. It is designed to be joined. Since TiN7 has a low resistance and the diffusion rate of impurities is lower than that of silicide, mutual diffusion of impurities can be suppressed. That is, in the second conventional example (FIG. 3), the element area can be reduced. However,
Since TiN7 exerts stress on the gate insulating film during the manufacturing process, it has a problem of degrading the hot carrier characteristics.

[0003]

As shown in the above two conventional examples, the device structure using the dual gate is
There are two issues: (1) reduction of the device area and (2) improvement of reliability such as hot carrier characteristics due to gate insulating film stress. In the first conventional example (FIG. 2), the former element area problem remains unsolved, and in the second conventional example (FIG. 3), the latter problem of hot carrier characteristics due to gate insulating film stress remains unsolved. Thus, in order to suppress the fluctuation of the threshold voltage due to the impurity diffusion and reduce the element area, it is necessary to deposit a low resistance material other than silicide such as titanium nitride on the gate polysilicon. However, at this time, the reliability of the device characteristics such as the hot carrier characteristics deteriorates due to the stress due to the low resistance material. In order to reduce this stress, it is necessary to thicken the gate polysilicon, thin the low resistance material, and apply heat treatment at an appropriate temperature. However, if the polysilicon is thickened, the step difference of the element increases and the processing becomes difficult. Further, when the low resistance material is made thin, the gate resistance increases, and the operation speed becomes slow. Further, the addition of the heat treatment tends to cause thin film peeling and abnormal oxidation, leading to a decrease in reliability and yield. This becomes a particular problem when a logic circuit is constructed in which it is difficult to add a redundant circuit and high-speed operation is intended. Conversely, if a structure with low stress can be formed without thinning the low-resistance material, the gate resistance can be reduced, the reliability can be improved, and higher speed and integration can be achieved.

Therefore, it is an object of the present invention to directly connect two polysilicons having different impurities to reduce the device area and to reduce the stress applied to the gate insulating film with high integration and high reliability. -To provide a high-speed operation semiconductor device. Another object of the present invention is to provide a semiconductor device having a gate electrode that can improve the operating speed by substituting it for a wiring layer. Another object of the present invention is to provide a semiconductor device of high reliability and high speed operation which uses a low-concentration source / drain to further improve the withstand voltage of the element and prolong the life of the element. Another object of the present invention is to provide a semiconductor device which has a design using an existing cell library, which has a reduced design cost, is highly reliable, and can be manufactured quickly. Another object of the present invention is to provide a CMOS logic circuit with high integration, high reliability and high speed operation.

[0005]

In order to solve the above-mentioned problems, a typical embodiment of the present invention (see FIG. 1) is a gate electrode structure immediately above an activation region, which is an upper layer / intermediate layer / lower layer. A three-layer structure composed of a low resistance material (7) / a low coefficient of thermal expansion (8) / polysilicon (5, 6) is provided. That is, while suppressing the interdiffusion of impurities from titanium nitride (TiN) as the low resistance material (7) of the upper layer into the lower polysilicon (5, 6) by the low thermal expansion material (8) of the intermediate buffer layer, While reducing the resistance of the electrode structure, SiO ₂
By providing a low thermal expansion coefficient material (8) such as
By directly connecting (5, 6), the element area is reduced and the stress applied to the gate insulating film (4) is reduced. Silicon dioxide (SiO ₂ ) can be used as the low thermal expansion coefficient material of the intermediate buffer layer (8).

As a preferred embodiment of the present invention, the following specific embodiments can be adopted. For example, in order to improve the circuit operation speed of the integrated circuit, the above gate electrode structure is used as it is as a wiring layer of the integrated circuit. Further, in order to improve reliability, low impurity concentration source / drain is added to high impurity concentration source / drain. Further, in order to further reduce the stress, after processing the gate polysilicon, the intermediate buffer layer of the low thermal expansion coefficient material is wet-etched. Further, by using the above-mentioned element structure, a semiconductor integrated circuit device which can utilize the property of the cell library is configured to facilitate the design. A CMOS logic circuit is constructed using the above element structure.

[0007]

In a typical embodiment of the present invention (see FIG. 1), a low resistance material (7) such as titanium nitride (TiN) is used as polysilicon.
It is possible to realize a semiconductor device which is deposited on (5, 6) to reduce the gate resistance and operates at high speed. Also, a low coefficient of thermal expansion material such as silicon dioxide (SiO ₂ ) is inserted as an intermediate buffer layer (8) between the upper layer low resistance material (7) and the lower layer polysilicon (5, 6) on the activation region. It has a configuration.
With this configuration, the stress generated between the conventional low resistance material and polysilicon can be reduced, the gate breakdown voltage and the hot carrier resistance can be improved, and a highly reliable semiconductor device can be realized. In addition, titanium nitride (T
By using iN), mutual diffusion of impurities can be suppressed. As a result, the n-channel transistor and the p-channel transistor can be designed closer to each other than in the conventional case, so that the element area can be reduced and a high-speed and highly integrated semiconductor device can be realized. Furthermore, by using at least one of the above-mentioned two-layer structure and the above-mentioned three-layer structure as a wiring layer, it is possible to realize a semiconductor device that reduces the circuit area and operates at high speed. Further, by providing a low concentration source / drain, the electric field at the drain end can be relaxed, a highly reliable fine element can be realized, and an element capable of high-speed operation can be realized. After processing the gate polysilicon, the buffer layer can be wet-etched to effectively reduce the stress. In addition, since a semiconductor device that can utilize the cell library property can be configured, the design can be facilitated. Further, a high speed and highly reliable CMOS logic circuit can be constructed.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a CMOS inverter constructed by using the present invention, which includes a p-channel MOS transistor having a p-type polysilicon gate (5 in FIG. 1 (b)) and an n-type polysilicon gate (FIG. 1 (b)). 6) which is an n-channel MOS transistor. In FIG. 1, (a) is a layout diagram, and (b) and (c) are AA 'and B in the layout diagram (a).
It is sectional drawing in B '. Vcc is a high potential power source,
Vss is a low potential power supply, Vin is an input signal voltage, and Vout is an output signal voltage. The feature of this device structure lies in the gate,
The silicon substrate 1, the p-type well 2, the n-type well 3, the gate insulating film 4, the element isolation insulating film 9, the source / drain 10 and the like have the same structure as a normal element structure. The features of the device structure of the present invention will be described below by comparison with the conventional example. The difference between the first embodiment (FIG. 1) and the first conventional example (FIG. 2) is that two polysilicons 5 and 6 having different impurities are formed so as to be in direct contact with each other, and the cell area is reduced. Is what you are doing. In the first conventional example (FIG. 2), since the impurity diffusion in the silicide 17 on the gate polysilicons 5 and 6 is large, these polysilicons 5 and 6 cannot be directly contacted. On the other hand, in the present element structure of FIG. 1, titanium nitride TiN capable of suppressing impurity diffusion is used as the low resistance material 7 deposited on the gate polysilicons 5 and 6 to deal with this problem. The thickness of TiN as the low resistance material 7 is 100 nm. Some of the impurities in polysilicon are absorbed by titanium nitride,
Since the amount is small and does not re-diffuse into the polysilicon, direct connection between the two polysilicons 5 and 6 is possible. Further, in the present element structure, even if the distance between the connection interface between the two polysilicons 5 and 6 and the activation region 110 is reduced to 0.4 μm, fluctuations in the threshold voltage due to impurity diffusion can be suppressed. Incidentally, TiN can be replaced with a boron compound, a carbon compound, a nitrogen compound or the like of a transition metal such as Ta, Ti, Mo or the like in view of the requirements of process easiness, heat resistance and the like. This replacement is the same in the examples described later. Further, the difference between the first embodiment (FIG. 1) and the second conventional example (FIG. 3) is that the intermediate buffer layer 8 is provided between the upper layer low resistance material (TiN) 7 and the lower polysilicon layers 5 and 6. Is provided. In this embodiment, in addition to reducing the area,
The intermediate buffer layer 8 reduces the stress applied to the gate oxide film 4 in the channel region and enhances the reliability.
In the second conventional example (FIG. 3), the stress due to TiN of the low resistance material 7 is large, so that the gate breakdown voltage, hot carrier life, etc. are deteriorated and the reliability is lowered.

In the embodiment of FIG. 1, 50 nm silicon dioxide SiO ₂ was used as the intermediate buffer layer 8. Since the above-mentioned reliability deterioration is caused especially by the stress applied to the channel region, the intermediate buffer layer 8 should be provided at least on the gate on the channel region. On the other hand, in order to reduce the resistance of the gate, it is necessary to firmly adhere the low resistance material 7 and the lower polysilicon layers 5 and 6 except on the channel region. Further, since the final shape of the intermediate buffer layer 8 is determined by processing the gate polysilicon,
Since it is not necessary to consider the mask alignment accuracy regarding the position of the intermediate buffer layer 8, the cell area can be reduced. Another feature of this embodiment is the layout design of the region where the low resistance material 7 and the lower polysilicon layers 5 and 6 are in close contact, that is, 108 in FIG. 1 (a). This design facilitates gate processing and improves reliability for the following reasons. As will be described later in detail, just before the gate processing in the middle of the process, the upper layer of TiN7 is formed inside 108.
/ A lower layer polysilicon 5 and 6 has a two-layer structure, and an outer layer 108 has a multilayer structure of an upper layer TiN / intermediate buffer layer SiO ₂ 8 / lower layer polysilicon 5 and 6. At the time of processing the gate, the processing conditions of these two multi-layer structures are different, and the base material may be scraped. By using the layout structure of this embodiment, most of the wafer surface has the same multilayer structure as the vicinity of the channel and can be processed under the same conditions, so that the area where the element isolation insulating film or the substrate is shaved can be minimized.

Next, FIG. 4 shows an outline of a process flow for forming the element structure of the embodiment shown in FIG. First, as shown in FIG. 4A, a p-type well 2 and an n-type well 3 are formed on a semiconductor substrate 1 by ion implantation using a resist, and a device for element isolation is formed by a local oxidation method or a technique applying it. The insulating film 9 is formed. The element isolation insulating film 9 has a thickness of about 300 nm, and has a p-type well 2 and an n-type well 3
Both have an impurity concentration of the order of 10 ¹⁷ / cm ³ . Next, as shown in FIG. 4B, a gate insulating film 4 is formed on the surface of the semiconductor substrate by thermal oxidation, polysilicon is deposited, and then a region is limited by using a resist 12, and impurity ion implantation is performed. By doing so, p-type polysilicon 5 and n-type polysilicon 6 are formed. The gate insulating film 4 has a thickness of about 5 nm, and the polysilicon layers 5 and 6 contain boron and phosphorus, respectively.
It is about ²⁰ / cm ³ doped. Next, FIG. 4 (c)
After depositing the intermediate buffer layer 8 as in
2 is used to remove the intermediate buffer 8 in the inner region 108 of FIG. The intermediate buffer layer 8 relaxes the stress of the low resistance material to be deposited in the next step, and this time, SiO ₂ of 50 nm was used. Then, as shown in FIG. 4D, the low resistance material 7 is deposited. That is, TiN / polysilicon inside 108 and Ti outside 108.
A multilayer structure of N / SiO ₂ / polysilicon is formed.
As the low resistance material 7, 100 nm TiN is used.
After that, as shown in FIG. 4E, the resist 12 is used to process the low resistance material 7, the intermediate buffer 8, and the polysilicons 5 and 6 into a gate shape. Then, FIG. 4F shows that after the source and drain diffusion layers (not shown) are formed by ion implantation,
The interlayer insulating film 13 is deposited, the contact hole is processed, and then the wiring metal 14 is deposited and processed. Thus, the element structure of the embodiment of FIG. 1 is constituted. The heat treatment after processing the low-resistance material is likely to cause peeling of the gate and generation of thermal stress, so careful process design is necessary.

Referring to FIG. 5, the CM according to the second embodiment of the present invention.
An OS inverter is shown. This embodiment and the first embodiment (Fig. 1)
The difference is the layout design of the region where the low resistance material 7 and the polysilicons 5 and 6 are in close contact with each other. In this embodiment, the intermediate buffer layer 8 is left only inside 208 of FIG. 5A when the low resistance material is deposited. In other words, when processing the gate,
Inside 208, TiN / SiO ₂ / polysilicon,
Outside of 208, a TiN / polysilicon multilayer structure is created. That is, the polysilicon 5, 6 and the low resistance material 8 are directly deposited on most of the area of the wafer. Compared with the region sandwiching the buffer layer, this region is characterized in that the low-resistance material is less likely to peel off, and it is possible to suppress process defects and increase the yield. However, in this embodiment, since the base material may be scraped during the gate processing, it is necessary to use a dry etching technique having good selectivity. The process flow for forming this embodiment is the same as that of the first embodiment except for this dry etching technique.

Next, FIG. 6 shows a CMOS inverter according to a third embodiment of the present invention. The difference from the first embodiment is
The buffer layer 8 once formed is removed, and the low resistance material Ti
A void 15 is formed between N7 and the polysilicons 5 and 6. The void 15 is almost refilled with the interlayer film material 7. However, since the interlayer film such as BPSG (boron / phosphosilicate / silicate glass) has a small Young's modulus and poor adhesion, the stress of the low resistance material 7 is reduced. Is less likely to be directly transmitted to polysilicon, stress applied to the gate insulating film can be reduced, and reliability such as gate breakdown voltage and hot carrier breakdown voltage can be improved.

Next, FIG. 7 shows an outline of a process flow for forming the element structure of the third embodiment of FIG. Figure 7
(a) corresponds to the process flow chart 4 (e) of the first embodiment, and the steps up to this point are the same as in the first embodiment. In FIG. 7A, the resist 12 is used to process the gate using the low resistance material TiN 7 and the intermediate buffer layer 8. The point of the process of this embodiment is to use a material having a particularly high wet etching rate as the intermediate buffer layer material 8. In this embodiment, as the intermediate buffer layer material 8, a SiO ₂ vapor deposition film having a film thickness of 50 nm is used. Then, in FIG. 7B, the void 15 is formed by removing the intermediate buffer material 8 by etching using an HF aqueous solution. At this time, materials other than the buffer layer are also etched, but since their selection ratio with respect to the SiO ₂ vapor deposition film is large, their scraping is small and there is no problem in etching accuracy. For example, the low-resistance material TiN 7 and the gate polysilicons 5 and 6 are scarcely shaved, and the element isolation insulating film 9 is shaved to about 15 nm. Thereafter, in the step of FIG. 7C, the void 15 is refilled with an interlayer insulating film which is an insulating film made of glass having high fluidity such as BPSG. FIG. 7C shows a step of forming the interlayer insulating film 13 and the wiring layer 14. The interlayer film 13 is a 350 nm BPSG film having a small Young's modulus and poor adhesion. Although this interlayer film material is almost filled in the region of 15, the stress of the low resistance material is difficult to be directly transmitted to the polysilicon, so that the gate structure in which the stress is relaxed can be formed. On the other hand, this step (c)
If the interlayer film flattening technique using dry etching is used for the semiconductor device, it is possible to suppress a step and realize a semiconductor device with a higher yield.

Next, referring to FIG. 8, C of the fourth embodiment of the present invention.
A MOS inverter is shown. The difference between this embodiment and the first embodiment (FIG. 1) is that the low impurity concentration source / drain region 16
Is formed, and the insulating material side wall 19 is provided for the formation. The low-impurity-concentration drain region 16 of the present embodiment can alleviate the electric field near the drain junction, further improve the hot carrier resistance, and realize a highly reliable semiconductor device. In this embodiment, the low impurity concentration source / drain region 16 is provided in the first embodiment (FIG. 1), but it is needless to say that the same effect can be obtained by providing it in other embodiments. Yes.

Next, FIG. 9 shows an outline of a process flow for forming the device structure of FIG. FIG. 9A corresponds to the process flow chart 4E of the first embodiment, and the steps up to this point are the same as those in the first embodiment. In FIG. 9A, the resist 12 is used to process the gate using the low resistance material 7 and the intermediate buffer layer 8. Subsequently, as shown in FIG. 9B, after the low impurity concentration source and drain regions 16 are formed by ion implantation, SiO ₂ 200 nm is deposited as the sidewall forming insulating film 18. Figure 9 (c)
Processed SiO ₂ by anisotropic dry etching,
This is a step of forming the high-impurity source / drain region 10 by ion implantation after forming the insulator side wall 19, and thereafter, an interlayer insulating film and a metal wiring layer are provided to realize a semiconductor device.

As described above, the first to fourth embodiments of the present invention are as follows.
Although it is a CMOS inverter, the stress applied to the gate insulating film can be relaxed even if the present gate structure is applied to a single MOS transistor. Also, when applied to a circuit configuration other than a CMOS inverter having a layout design in which polysilicon containing impurities of different types or concentrations are directly connected, resistance reduction, stress relaxation, impurity diffusion suppression, etc.
It goes without saying that the same effect as that of the above embodiment can be obtained.

FIG. 10 is a cell layout of a two-input NAND gate circuit according to the fifth embodiment of the present invention, and the above effect can be obtained. In the figure, IN1 and IN2 are input signal voltages,
OUT is an output signal voltage. Further, in this embodiment, it is possible to reduce the area by narrowing the gate interval for the following reason. In a layout design in which a plurality of gates are arranged in parallel, such as a 2NAND gate, in the case of electrically connecting n-type and p-type polysilicon by a wiring layer by a conventional technique, a contact is formed. A mask alignment margin was needed. In this embodiment,
Since this mask margin is not required, the gates can be arranged at narrow intervals, and the area can be further reduced.

Next, the performance improvement according to the present invention will be described with reference to FIGS. 11 to 15. First, FIG. 11 shows the stress reduction effect of the intermediate buffer layer of the present invention. When a low resistance material such as TiN is used, the stress increases as in Conventional Example 2, but the stress can be reduced to the level of Conventional Example 1 by providing the intermediate buffer layer of the present invention. When SiO ₂ is used for the intermediate buffer layer, the required thickness of the buffer layer is about 50 nm.

Next, FIG. 12 shows the hot carrier life. When TiN was deposited on the gate polysilicon as in Conventional Example 2, the stress was large and the hot carrier life was short. Since the stress can be relaxed in the present invention, the hot carrier life can be extended to the level of Conventional Example 1 even though TiN is used.

Next, FIG. 13 shows the fluctuation of the threshold voltage due to the direct junction of polysilicon. In the device structure of Conventional Example 1, when polysilicon is directly connected, impurities are largely diffused through the silicide, and FIG.
As described above, the threshold voltage fluctuates greatly near the junction. On the other hand, in the case of the device structure of the present invention, the distance between the n-type / p-type polysilicon interface and the activation region is set to a minimum of 0.4 μm.
Even if they are brought close to each other, the fluctuation of the threshold voltage can be suppressed to 0.01 V or less.

Next, FIG. 14 shows the element area. As device miniaturization progresses to the submicron level, application of n / p type polysilicon gates becomes essential.
At this time, in Conventional Example 1, the area of the polysilicon junction cannot be reduced and the cell area becomes large. In the present invention, since a material having a low impurity diffusion rate and a low resistance is deposited on the gate polysilicon, as in Conventional Example 2,
The cell area can be reduced.

Next, referring to FIG. 15, the efficiency improvement of the design will be described with reference to the sixth embodiment. In the present embodiment, a large-scale logic circuit design is realized by slightly modifying and reusing past layout design data. That is, the layout cell using the element structure of the present invention is the same as the cell using no p-type polysilicon gate in the past.
It is almost similar. Therefore, it is possible to quickly perform a functional level layout using the slightly modified cell. Furthermore, if the function level layout that was performed before was the building block method, the data can be reused, and the design efficiency can be improved. In this way, the reliable design data accumulated once can be reused to rapidly manufacture a highly reliable chip with a reduced design cost. Further, a highly integrated computer system with high reliability can be configured by using a chip using such a design method. The buffer layer of the element structure of the present invention in the layout cell can automatically generate design data by calculation such as expansion of the active region.

Since the gate of the present invention has a low resistance, it can be directly used as a wiring layer.
An effect of speeding up is also obtained by reducing the wiring length.

[0024]

According to the present invention, high integration, high reliability and high speed can be achieved by directly connecting two polysilicons having different impurities to reduce the element area and reduce the stress applied to the gate insulating film. It is possible to provide an operating semiconductor device.

[Brief description of drawings]

FIG. 1 is a diagram showing a CMOS inverter element according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a CMOS inverter element of a first conventional example of the present invention.

FIG. 3 is a diagram showing a CMOS inverter element of a second conventional example of the present invention.

FIG. 4 is a diagram showing a process flow of the first embodiment of the present invention.

FIG. 5 is a diagram showing a CMOS inverter element according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a CMOS inverter device according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a process flow of a third embodiment of the present invention.

FIG. 8 is a diagram showing a CMOS inverter device according to a fourth embodiment of the present invention.

FIG. 9 is a diagram showing a process flow of a fourth embodiment of the present invention.

FIG. 10 is a CMOS-2 input N of the fifth embodiment of the present invention.
It is a figure which shows an AND element.

FIG. 11 is a diagram showing an effect of improving stress characteristics according to the present invention.

FIG. 12 is a diagram showing the improvement of hot carrier life according to the present invention.

FIG. 13 is a diagram showing improvement in threshold voltage fluctuation due to impurity diffusion according to the present invention.

FIG. 14 is a diagram showing a reduction in cell area according to the present invention.

FIG. 15 is a diagram showing a design using a cell library according to a sixth embodiment of the present invention.

[Explanation of symbols]

1 ... Semiconductor substrate, 2 ... P-type well, 3 ... N-type well, 4
... Gate insulating film, 5 ... P-type polysilicon for gate, 6 ...
N-type polysilicon for gate, 7 ... Low resistance material (TiN),
8 ... Buffer layer (SiO ₂ ), 9 ... Insulating film for element isolation, 1
0 ... Source / drain region, 11 ... Metal wiring layer, 12 ...
Resist, 13 ... Interlayer insulating film, 14 ... Wiring layer metal, 15
... Void region, 16 ... Low impurity concentration source / drain region, 17 ... Silicide, 18 ... Sidewall insulating film, 19 ... Sidewall by insulating film, 30 ... Cell, 31 ... Block, 32 ...
Wiring, 103 ... N-type well region (p-type well is an inversion region), 105 ... P-type gate electrode, 106 ... N-type gate electrode, 107 ... Gate electrode, 108 ... SiO ₂ removal region,
110 ... Reversal of activation area, 208 ... SiO ₂ removal area.

Front page continuation (72) Inventor Natsuki Yokoyama 1-280 Higashi Koigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (7)

[Claims] 1. A P-channel MOS transistor having a gate of P-type impurity-doped polysilicon and an N-channel MOS transistor having a gate of N-type impurity-doped polysilicon are provided on a semiconductor substrate. The polysilicon and the N-type impurity-doped polysilicon are physically directly connected, and the P-type impurity-doped polysilicon and the N-type impurity-doped polysilicon are directly connected to each other over the polysilicon at the connection portion. Is directly deposited with a low resistance material made of a metal compound, and the low resistance material is not directly deposited on the polysilicon over the active regions of the P-channel MOS transistor and the N-channel MOS transistor. A semiconductor device characterized by the above. 2. The low resistance material is formed on the polysilicon on the active region through a low expansion material having a thermal expansion coefficient smaller than that of silicon. Semiconductor device. 3. A gate electrode having a three-layer structure of the low resistance material / the low coefficient of thermal expansion / polysilicon is formed immediately above the activation region, and the low resistance material / the polysilicon above the connection portion. 3. The semiconductor device according to claim 1 or 2, wherein the gate electrode having a two-layer structure is formed. 4. The semiconductor device according to claim 1, wherein the metal compound as the low resistance material is a transition metal compound. 5. The semiconductor according to any one of claims 1 to 3, wherein the transition metal compound is any one of Ta, Ti and Mo, and a transition metal such as a boron compound, a carbon compound or a nitrogen compound. apparatus. 6. The semiconductor device according to claim 2, wherein silicon dioxide is used as the low thermal expansion coefficient material. 7. The semiconductor device according to claim 3, wherein at least one of the two-layer structure and the three-layer structure is used as a wiring layer. .