JPH07160479A - Division arithmetic unit - Google Patents

Abstract

PURPOSE:To perform division arithmetic operation while reducing the power consumption by predicting that the sign of the subtraction arithmetic result of subtraction is minus on the basis of dividend data and speedily determining a next process before the division arithmetic by a subtracter used for the division arithmetic unit ends. CONSTITUTION:As for selection by a partial residue selecting circuit S15 based upon the subtraction result sign B15 outputted by the subtracter J15, a partial residue selecting circuit S16 selects a subtraction arithmetic result A15 when the subtraction result sign B15 is 1 or dividend bit data X15 when it is 0. Thus, even when the subtraction result sign 15 is 1, a selection control signal becomes 0 on condition that divisor bit data X15 is 0, and the partial residue selecting circuit 815 selects the dividend bit data X15. Therefore, when the dividend bit data X15 is 0, it is predicted that the subtraction result sign S15 becomes 0 before the subtraction by the subtracter J15 ends, and the partial residue selecting circuit S15 can be selected and switched in an early stage.

Description

Detailed Description of the Invention

[0001]

The present invention relates to the LSB (least significant bi) of partial remainder data R (n + 1) up to that point.
t) side, MSB (most significa) of dividend data X
nt bit) The dividend bit data X sequentially fetched from the side
The data to which n is added is used as the partial dividend data Wn. As the partial division operation, first, the divisor data Y is subtracted from the partial dividend data Wn. If this subtraction operation result An is positive, the subtraction operation result An is The partial remainder data Rn of the partial division operation is set, and the bit data Qn of the quotient data Q corresponding to the partial division operation at this time is set to "1".
When the subtraction operation result An is negative, the partial dividend data Wn is set as the partial remainder data Rn of the partial division operation at this time, and the bit data Qn corresponding to the partial division operation of the quotient data Q at this time is set to " The present invention relates to a division operation device in which 0 "is repeated to obtain the quotient data Q by repeating such a partial division operation, and particularly, a division operation that can be performed by hardware while reducing power consumption. The present invention relates to a computing device.

[0002]

2. Description of the Related Art Conventionally, various algorithms for division operations have been known, and various types of division operation devices have been used. For division operations performed by software using a microcomputer, etc., and division operations performed by hardware using logic gates, etc., most division operations basically require digit shift or subtraction. Repeatedly, the operation result of the division, that is, the quotient and the remainder of the division are finally obtained.

As a device for performing such a division operation, there is conventionally a recovery type division device.

FIG. 9 is a block diagram showing the configuration of the main part of a conventionally used recovery type division device.

In FIG. 9, the dividend data is stored in the register X in advance. Further, the divisor data Y is similarly stored in advance in the register Y (not shown). Further, the recovery type division device includes a total of 16 partial dividers D15 to D0.

The recovery-type division device shown in FIG.
6-bit dividend data X is converted to 16-bit divisor data Y
It divides by and calculates the quotient and the remainder. Further, in such a recovery type division device, the final quotient is stored in the register Q when all the operations in the respective partial dividers D15 to D0 are completed. on the other hand,
For the final remainder, the partial dividers D15 to D0
When all the calculations performed in each of them are completed, the partial divider D0 outputs the remainder R0.

FIG. 10 is a block diagram showing a configuration of the partial divider used corresponding to 15 bits of the dividend data X of the recovery type division arithmetic unit.

In FIG. 10, the partial divider D15 shown in FIG. 9 is shown. The partial divider D
15 includes a subtractor J15 and a partial remainder selection circuit S15.

First, the subtractor J15 subtracts the total 16-bit divisor stored in the register Y from the 15th bit of the register X, that is, X15. The result of this subtraction operation is output as A15. Further, the subtractor J15 has a subtraction result code B15 indicating whether the value of the subtraction operation result A15 is positive or negative.
Is output. In the subtractor J15, the subtraction result code B15 becomes "1" when the subtraction operation result A15 is positive. On the other hand, when the subtraction operation result A15 is negative, the subtraction result code B15 is "0". In the partial divider D15, the subtraction result code B15 is written in the bit data Q15 of the quotient data Q and the bit data Q15 is updated.

The partial remainder selection circuit S15 uses a multiplexer that selects either the input 1 or the input 0 according to the input S and outputs the selected one to the output U. The partial remainder selection circuit S
Therefore, when the subtraction result code B15 is “1”, the reference numeral 15 selects the subtraction operation result A15 and outputs it as the partial remainder data R15. On the other hand, when the subtraction result code B15 is "0", the partial remainder selection circuit S15
The dividend bit data X15 is selected and output as the partial remainder data R15.

FIG. 11 is a block diagram showing the configuration of a partial divider used in correspondence with the 14th bit of the dividend data used in the conventional example of the above-mentioned division operation device.

FIG. 11 shows the configuration of the partial divider D14 shown in FIG. 9 corresponding to the dividend data X, particularly the 14th bit of the dividend bit data X14. The partial divider D14 is
It is mainly composed of a register T14, a subtractor J14, and a partial remainder selection circuit S14.

First, the register T14 has the partial remainder data R15 input from the partial divider D15.
And the dividend bit data X14 of the 14th bit of the dividend data X, the partial dividend data W14 corresponding to the partial divider D14 is obtained. Specifically, the dividend bit data X14 sequentially extracted from the MSB side of the dividend data X is added to the LSB side of the partial remainder R15.

The subtractor J14 subtracts the divisor data Y from the partial dividend data W14, outputs the subtraction operation result A14, and determines whether the subtraction operation result A14 is positive or negative. Subtraction result code B
14 is output. The subtraction result code B14 is written in the register Q as the 14th bit of the quotient data Q, that is, the quotient bit data Q14.

The partial remainder selection circuit S14 is a multiplexer that selects either the input 1 or the input 0 according to the input S and outputs it to the output U. When the subtraction result code B14 is "1", the partial remainder selection circuit S14 selects the subtraction operation result A14 and outputs it as the partial remainder R14. On the other hand, when the subtraction result code B14 is "0", the partial remainder selection circuit S14 outputs the partial dividend data W1.
4 is selected and is output as the partial remainder R14.

FIG. 12 is a block diagram showing the configuration of a partial divider used in correspondence with the 13th bit of the dividend data used in the conventional example of the division operation device.

As shown in FIG. 12, the partial divider D13 is composed of a register T13, a subtractor J13, and a partial remainder selection circuit S13.

First, the register T13 generates partial dividend data W13 from the partial remainder R14 output from the partial divider D14 and particularly the 13th bit of the dividend data X, that is, the dividend bit data X13. . Specifically, the partial dividend data W13 is generated by adding the dividend bit data X13 to the LSB side of the partial remainder R14.

The subtractor J13 subtracts the divisor data Y from the partial dividend data W13, outputs the subtraction operation result A13, and determines whether the subtraction operation result A13 is positive or negative. Subtraction result code B
13 is output. This subtraction result code B13 is the 13th bit of the quotient data Q, that is, the quotient bit data Q13,
It is written into the register Q.

The partial remainder selection circuit S13 is a multiplexer that selects either the input 1 or the input 0 according to the input S and outputs it to the output U. When the subtraction result code B13 is "1", the partial remainder selection circuit S13 outputs the subtraction operation result A
13 is selected and is output as the partial remainder R13.
On the other hand, when the subtraction result code B13 is "0", the partial remainder selection circuit S13 selects the partial dividend data W13 and outputs it as the partial remainder R13.

FIG. 13 is a block diagram showing the configuration of a partial divider used in the above-mentioned division operation device in the prior art example corresponding to the nth bit of the dividend data.

FIG. 13 shows any one of the partial dividers D14 to D0 shown in FIG. 9, and shows the configuration other than the partial divider D15 corresponding to the MSB of the dividend data X. It is a thing. The nth bit of the dividend data X, that is, the dividend bit data Xn
The partial divider Dn corresponding to is composed of a register Tn, a subtractor Jn, and a partial remainder selection circuit Sn.

First, the register Tn is a partial remainder R (n + 1) input from the preceding partial divider D (n + 1).
And the dividend bit data Xn, the partial dividend data Wn is generated. Specifically, the partial remainder R (n
The partial dividend data Wn is generated by adding the dividend bit data Xn to the LSB side of (+1).

The subtractor Jn subtracts the divisor data Y from the partial dividend data Wn, outputs the subtraction operation result An, and determines whether the subtraction operation result An is positive or negative. The subtraction result code Bn shown is output. The subtraction result code Bn is written in the register Q as the n-th quotient bit data Qn of the quotient data Q.

The partial remainder selection circuit Sn has its input S
According to that input 1 or its input 0
Is a multiplexer that selects one of the inputs to the output U and outputs it to its output U. When the subtraction result code Bn is "1", the partial remainder selection circuit Sn selects the subtraction operation result An and outputs it to the partial remainder R.
Output as n. On the other hand, the partial remainder selection circuit Sn is
When the subtraction result code Bn is "0", the partial dividend data Wn is selected and output as the partial remainder Rn. Regarding the partial remainder Rn output from the partial remainder selection circuit Sn, the next-stage partial divider D (n-1)
Is output to.

When the partial divider Dn corresponds to the MSB of the dividend data X, the partial remainder Rn output from the partial remainder selection circuit Sn is obtained by converting the dividend data X into the divisor data Y. It becomes the final remainder after division.

As described above, according to the conventional division arithmetic unit described with reference to FIGS.
It is possible to obtain the quotient data Q and the remainder R thereof obtained as a result of dividing the dividend data X by the divisor data Y. Further, the division operation performed by the hardware as described above can be executed at a remarkably high speed as compared with the case where it is performed by the software.

[0028]

However, in the case of the conventional division operation device as described above, in which the division operation is performed by hardware, a large number of logic gates are required, and the circuit scales are relatively small. It will become huge. For example, there are some that are quite large, such as about 3000 gates. Further, when paying attention to the respective logic gates used, there is a case where the logic state of the output changes many times during one division operation, which requires a lot of power consumption.
As described above, a division operation device configured to perform a division operation by hardware generally has a problem that its power consumption increases.

The present invention has been made to solve the above conventional problems, and an object of the present invention is to provide a division operation device capable of performing a division operation by hardware while reducing power consumption. And

[0030]

According to the present invention, the dividend bit data Xn sequentially fetched from the MSB side of the dividend data X is added to the LSB side of the partial remainder data R (n + 1) up to that point. The partial dividend data Wn is set as the partial division data Wn.
When the divisor data Y is subtracted from this and the subtraction operation result An is positive, the subtraction operation result An is used as the partial remainder data Rn of the partial division operation at this time and the quotient data Q is used as the partial division operation at this time. When the corresponding bit data Qn is "1" and the subtraction operation result An is negative, the partial dividend data Wn is used as the partial remainder data Rn of the partial division operation at this time, and the quotient data Q In the division operation device in which the bit data Qn corresponding to the partial division operation at time is set to "0" and the quotient data Q is obtained by repeating such partial division operation, the divisor data Y is converted from the partial dividend data Wn. A subtractor Jn for performing subtraction and outputting the subtraction operation result An, and for outputting a subtraction result code Bn indicating whether the subtraction operation result An is positive or negative; The operation before the end of the subtraction at Jn, the dividend based on the data X, and the operation result prediction circuit Fn said subtraction result code Bn by the subtraction predicted to become as indicating negative, the operation result prediction circuit Fn
When the subtraction result code Bn is predicted to be negative, the partial remainder selection circuit Sn for selecting the partial dividend data Wn as the partial remainder Rn of the partial division operation at this time is provided. The above problems have been achieved.

Further, in the division operation device, when the operation result prediction circuit Fn predicts that the subtraction result code Bn is negative, the subtraction by the subtractor Jn is performed. Before the end of the calculation, the quotient data Q
By setting the bit data Qn corresponding to the partial division operation at this time to "0", the above-mentioned problem can be achieved and
This is to reduce the time required for the division operation as much as possible.

Further, in the division operation device, the operation result prediction circuit Fn includes the dividend bit data Xn extracted corresponding to the partial division operation of the dividend data X for the target partial division operation, When all the bit data X _{MSB to} Xn on the MSB side than this are all "0", it is predicted that the subtraction result code Bn will be negative, thereby achieving the above object. The operation result prediction circuit is made simpler to reduce the circuit scale and power consumption.

[0033]

In a logic circuit composed of hardware, when the logic state of the output of the internal logic gate changes, the power consumption of the logic gate tends to increase.

For example, CMOS (complementary metal)
In the logic circuit by the oxide semiconductor) process, basically, the power consumption of the logic gate is 0 when the logic state of the output of the internal logic gate does not change.
Becomes On the other hand, in such a logic circuit based on the CMOS process, power consumption of the logic gate occurs when the logic state of the output of the logic gate inside the logic circuit changes.

This is because the charging current mainly flows from the output of the logic gate to the capacitive load when the logic state changes. Also, a P-channel MOS (metal oxide semicinductor) that drives the output
This is because a so-called through current flows from the power supply to the ground in the transistor and the N-channel MOS transistor.

Focusing on such a point, in the present invention, unnecessary operation in the division operation device is reduced, and unnecessary change in the output of the logic gate used therein is reduced. As a result, the overall or average power consumption is reduced.

Further, in particular, in the division operation as in the above-mentioned conventional division operation device or the like, a large number of subtraction operations are performed,
In the present invention, not only the subtraction operation result is used, but also the content of the processing to be performed next differs depending on whether the value of the obtained subtraction operation result is positive or negative. Is. It is possible to predict in advance whether the result of such subtraction operation is positive or negative. Furthermore, the next processing is performed by quickly determining the next processing based on such prediction. This is done by paying attention to the fact that unnecessary operations in processing can be reduced.

Therefore, the division operation device of the present invention is provided with the operation result prediction circuit Fn, in particular, as compared with the conventional device.

The calculation result predicting circuit Fn has the following operation before the end of the subtraction operation in the subtractor used in the division operation device.
Based on the dividend data X, it is predicted that the sign of the subtraction operation result by the subtraction will be negative. The reason why a negative value is predicted rather than a positive value is that it is not necessary to use the subtraction operation result in the next process when the negative value is obtained. On the other hand, if it is predicted that the result is positive by comparison, the subtraction operation result is necessary in the next process, and eventually the operation of the subtractor must be completed.

In this way, when the subtraction result sign is predicted to be negative by the operation result prediction circuit Fn, when the sign of the subtraction operation result is negative in the conventional subtractor, the following operation is performed. Perform processing. Specifically, the partial remainder selection circuit S15 shown in FIG. 10, the partial remainder selection circuit S14 shown in FIG. 11, the partial remainder selection circuit S13 shown in FIG. 12, and the partial remainder selection circuit shown in FIG. The partial remainder selection circuit Sn is selected by selecting the dividend bit data X15.
(Corresponding to the partial dividend data W15), the partial dividend data W14, the partial dividend data W13, and the partial dividend data Wn.

In the present invention, as described above, the operation result prediction circuit Fn can operate the partial remainder selection circuit Sn without waiting until the subtraction result is obtained by the subtracter, and the operation can be performed at an earlier stage. Thus, the logic state in the partial remainder selection circuit can be fixed, and power consumption can be reduced.

Although the present invention is not limited to this, the prediction result by the operation result prediction circuit Fn is
It may be used not only in the partial remainder selection circuit Sn but also for other purposes. For example, to set the bit data Qn of the quotient data Q obtained by dividing the dividend data X by the divisor data Y, which is determined by the subtraction result of the subtractor that performs the subtraction operation for prediction by the operation result prediction circuit Fn. You may That is, the calculation result prediction circuit F
If the subtraction result code Bn is predicted to be negative in n, before the subtraction operation in the corresponding subtractor is completed,
The bit data Qn corresponding to the quotient data Q, which is determined by the sign of the subtraction operation result, may be set to "0". This makes it possible to improve the calculation speed in the division calculation device.

The present invention does not specifically limit the operation result prediction circuit Fn used in the present invention. That is, it suffices to predict, based on the dividend data X that is the object of the division operation, that the sign of the subtraction operation result in the subtractor becomes negative as described above. For example, in the embodiment described later, in the partial division operation including the subtraction operation predicted by the operation result prediction circuit Fn, the dividend bit data Xn extracted corresponding to the partial division operation of the dividend data X is included, All bit data X _MSB on the MSB side from this
When all the Xn are "0", it is predicted that the sign of the subtraction operation result becomes negative. Further, it is possible to judge that all the bit data X _{MSB to} X n are all “0”, for example, by using only one AND logic gate, and it is possible to make a very simple circuit. is there. Moreover, the power consumption of such a simple circuit is relatively small. The dividend bit data X _MSB is the _MSB of the dividend data X.

[0044]

Embodiments of the present invention will be described in detail below with reference to the drawings.

First, both the first embodiment of the division arithmetic unit to which the present invention described below is applied and the second embodiment of the division arithmetic unit to which the present invention is applied next are both. The overall structure is the same as that of the conventional division operation device shown in FIG.

That is, the register X, the register Y,
Regarding the register Q and the partial dividers D15 to D0, the mutual connection relationship and the like are the same as those shown in FIG. Also, the number of bits of the register X, the register Y, and the register Q is the same as that of the division operation device of this conventional example.

The difference between the conventional division arithmetic unit and the division arithmetic unit of the first embodiment, and the difference between the division arithmetic unit of the conventional example and the division arithmetic unit of the second embodiment are as follows. Only the internal circuits of the partial dividers D15 to D0 used differ.

FIG. 1 shows the first embodiment used in the first embodiment.
3 is a block diagram showing the configuration of the partial divider of FIG.

In FIG. 1, reference numeral D1 in FIG.
Partial divider D in the first embodiment, which is used for part 5
Fifteen configurations are shown. The partial divider D15, like the conventional one shown in FIG.
15 and a partial remainder selection circuit S15. Further, the partial divider D15 of the first embodiment is further provided with a calculation result prediction circuit F15 as shown in FIG.

The calculation result prediction circuit F15 receives the subtraction result code Bn output from the subtractor J15 and outputs a selection control signal E15 used for controlling the selection of the partial remainder selection circuit S15. In addition, this operation prediction circuit F1
5 will be described later in detail with reference to FIG.

FIG. 2 shows a second embodiment used in the first embodiment.
3 is a block diagram showing the configuration of the partial divider of FIG.

The partial divider Dn shown in FIG. 2 is
It is used for each of the reference numerals D14 to D0 in the overall view of FIG. The partial divider Dn of the first embodiment, like the corresponding partial divider Dn of the related art shown in FIG.
A subtractor Jn and a partial remainder selection circuit Sn are provided. Further, the partial divider Dn of the first embodiment is provided with a calculation result prediction circuit Fn. The calculation result prediction circuit F
n is the subtraction result code Bn output from the subtractor Jn
To output a selection control signal En used for selection in the partial remainder selection circuit Sn. The circuit of the calculation result prediction circuit Fn will be described later in detail with reference to FIG.

FIG. 3 is a circuit diagram of the operation result prediction circuit F15 used in the partial divider D15 of the first embodiment.

As shown in FIG. 3, the operation result prediction circuit F15 shown in FIG.
It can be configured by the input OR logic gate GA15.

The two inputs of the OR logic gate GA15 are both negative logic. Further, the output of the OR logic gate GA15 is also negative logic. Therefore, the subtraction result code B15 is "1", and
When the dividend bit data X15 is "1", the output selection control signal E15 is "1". Other subtraction result code B15 or dividend bit data X1
In the combination of 5 logic states, the output selection control signal E15 is "0".

In the operation result prediction circuit F15 as described above, first, the selection of the partial remainder selection circuit S15 according to the subtraction result code B15 output from the subtractor J15 is the conventional selection shown in FIG. Is the same as. That is, when the subtraction result code B15 becomes "1", the partial remainder selection circuit S15 selects the subtraction operation result A15. On the other hand, when the subtraction result code B15 is "0", the dividend bit data X15 is selected.

In the first embodiment, even if the subtraction result code B15 is "1" as described above,
If the divisor bit data X15 is "0", the selection control signal En becomes "0", and the partial remainder selection circuit S15 selects the dividend bit data X15. Therefore, when the dividend bit data X15 is "0", it is predicted that the subtraction result code B15 will be "0" before the end of the subtraction operation in the subtractor J15, and the part is calculated at an earlier stage. Residue selection circuit S15
It is possible to selectively switch.

Therefore, the logical states of the partial remainder selection circuit S15 and its output can be fixed at an earlier stage, and power consumption can be reduced.

FIG. 4 shows the partial divider D1 of the first embodiment.
4 is a circuit diagram of a calculation result prediction circuit used in FIG.

In FIG. 4, "n" in FIG.
In the above-mentioned conventional example, the partial divider D1 of the first embodiment corresponding to the one shown in FIG.
4 is a circuit diagram of the calculation result prediction circuit F14 used in FIG. As shown in FIG. 4, the operation result prediction circuit F14 has only two logic gates, that is, two inputs O.
R logic gate GA14 and 2-input AND logic gate GB
It is possible to configure with 14 and.

First, with respect to the AND logic gate GB14, both of its two inputs are negative logic. The output is also negative logic. The A
The dividend data X15 and X14 are input to the two inputs of the ND logic gate GB14. Therefore, when the dividend bit data X15 and X14 are both "0", the AND logic gate GB14
Output "0". The output of "0" of the AND logic gate GB14 is a result of predicting that the subtraction operation result A14 becomes negative, and is a result of predicting that the subtraction result code B14 becomes "0".

Next, with respect to the OR logic gate GA14, both of its two inputs are negative logic.
The output is also negative logic. Therefore,
The OR logic gate GA14 receives the subtraction operation result A14.
Becomes negative, whereby the subtraction result code B14 becomes "0", or the AND logic gate GB
When it is predicted that the subtraction result code B14 is “0” at 14, the selection control signal E14 is
Output "0". Thus, the selection control signal E14
Becomes "0", the partial remainder selection circuit S14 selects the partial dividend data W14 and outputs it as the partial remainder R14.

FIG. 5 is a circuit diagram of the operation result prediction circuit of the partial divider D13 of the first embodiment.

In FIG. 5, in the partial divider D13 of the first embodiment corresponding to the partial divider D13 shown in FIG. 9 or the conventional partial divider D13 shown in FIG. A circuit diagram of the calculation result prediction circuit F13 used is shown. As shown in FIG. 5, the operation result prediction circuit F13 is composed of only two logic gates, that is, an OR logic gate GA13 and an AND logic gate GB13.

First, the AND logic gate GB13 is
All three inputs are negative logic. The output is also negative logic. Therefore, the AN
The D logic gate GB13 outputs the dividend bit data X1.
If 5, X14 and X13 are all "0", "0"
Is output. The output of "0" is the partial divider D1.
3, the subtraction operation result A13 by the subtractor J13
It is predicted that the subtraction result code B13 will be "0" when N is negative.

The two inputs of the OR logic gate GA13 are both negative logic. The output is also negative logic. Therefore, the operation result code B13 becomes "0", or the AND logic gate GB
When the output of 13 becomes "0", "0" is output as the selection control signal E13. When "0" is output as the selection control signal E13, the partial remainder selection circuit S13 of the partial divider D13 causes the partial dividend data W13.
Is selected and output as the partial remainder R13.

FIG. 6 is a circuit diagram of an operation result prediction circuit used in the partial divider of the first embodiment.

In FIG. 6, reference numeral D in FIG. 9 is used.
14 to D0, that is, the partial divider Dn shown in FIG. 2 and the partial divider Dn of the first embodiment corresponding to the conventional example shown in FIG. A circuit diagram of the operation result prediction circuit Fn is shown. As shown in FIG. 6, the calculation result prediction circuit Fn
Is only two logic gates, OR logic gate GAn
And an AND logic gate GBn.

First, the AND logic gate GBn has (16-n) inputs. Also, these (1
All inputs of 6-n) have negative logic. The output of the AND logic gate GBn is also negative logic. Therefore, for a given "n", the dividend bit data X15 to Xn of (16-
When all n) bits are "0", the AND logic gate GBn outputs "0". The output of "0" is the subtraction operation result An in the subtractor Jn of the partial divider Dn.
Is a result of predicting that the subtraction result code Bn becomes "0" when N is negative.

The two inputs of the OR logic gate GAn are both negative logic. The output is also negative logic. Therefore, the subtraction operation result An becomes negative and the subtraction result code Bn is "0".
Or if the AND logic gate GBn predicts that the subtraction result code Bn will be "0", the OR logic gate GAn outputs the selection control signal En.
"0" is output as. The selection control signal En is "0"
Then, the partial remainder selection circuit Sn of the partial divider Dn selects the partial dividend data Wn and outputs it as the partial remainder Rn.

As described above, in the first embodiment, the subtracters J15 to J0 included in the operation result prediction circuits F15 to F0 included in the partial dividers D15 to D0, respectively, subtract the respective subtractions. Predicting that the subtraction calculation results A15 to A0 in the converter will be negative, and at a earlier stage, the partial remainder selection circuits S1 included in each
5 to S0 can be switched and selected. Therefore, the logical states of the partial remainder selection circuits S15 to S0 are fixed at an earlier stage, and this makes it possible to reduce power consumption.

FIG. 7 is a block diagram showing the structure of the partial divider D15 used in the second embodiment.

The subtractor J15 and the partial remainder selection circuit S15 shown in FIG. 7 used in the partial divider D15 are shown.
The calculation result prediction circuit F15 is the same as that of the first embodiment shown in FIG.

In the partial divider D15 of the second embodiment, the data to be written in the 15th bit of the register Q is output by the operation result prediction circuit F15. That is, the selection control signal E of FIG.
At 15, the quotient bit data Q15 of the register Q is written. Accordingly, when the operation result prediction circuit F15 can predict that the subtraction result code B15 becomes negative at an early stage, the quotient bit data Q
15 can be updated at an earlier stage.

FIG. 8 is a block diagram showing the structure of the partial divider of the second embodiment.

In FIG. 8, there is shown the configuration of the partial divider used in the second embodiment, in particular, indicated by the symbols D14 to D0 in FIG. This Figure 8
The register Tn, the subtractor Jn, the partial remainder selection circuit Sn, and the operation result prediction circuit Fn shown in FIG.
It is the same as the one shown in.

In the partial divider Dn of the second embodiment, the quotient bit data Qn of the register Q is updated, in particular,
The calculation result prediction circuit Fn is used. That is, the quotient bit data Qn is updated by the selection control signal En of the operation result prediction circuit Fn shown in FIG. Therefore, in the second embodiment, when it is predicted that the subtraction operation result An of the subtractor Jn becomes negative and the subtraction result code Bn becomes "0" in the operation result prediction circuit Fn, the operation is performed at an earlier stage. It is possible to update the quotient bit data Qn.

As described above, in the second embodiment, not only the power consumption is reduced by speeding up the selection of the partial remainder selection circuit within the possible range as in the first embodiment, but also the register Q is used. It is possible to update the update as soon as possible.

In the first embodiment and the second embodiment described above, the dividend data X is 16 bits and the divisor data Y is 16 bits. However, it goes without saying that the division operation device of the present invention is not limited to such a number of bits. That is, it goes without saying that the present invention can be applied to any bits of the dividend data X and the divisor data Y by providing the partial divider with the operation result prediction circuit as described above.

It is not necessary to provide such a calculation result prediction circuit for all partial dividers used in the division calculation device. Since the plurality of partial dividers included in the division operation device operate substantially independently of each other, it does not matter in particular whether the operation result prediction circuit is built in or not. Even if only some of the partial dividers are provided with the calculation result prediction circuit, some kind of power consumption reduction effect should be obtained.

[0081]

As described above, according to the present invention,
It is possible to obtain an excellent effect that it is possible to provide a division operation device capable of performing a division operation by hardware while reducing power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first partial divider used in a first embodiment of a division operation device to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration of a second partial divider used in the first embodiment.

FIG. 3 is a circuit diagram of a calculation result prediction circuit used in the partial divider D15 of the first embodiment.

FIG. 4 is a circuit diagram of a calculation result prediction circuit used in the partial divider D14 of the first embodiment.

FIG. 5 is a circuit diagram of an operation result prediction circuit used in the partial divider D13 of the first embodiment.

FIG. 6 is a circuit diagram of an operation result prediction circuit used in the partial divider Dn of the first embodiment.

FIG. 7 is a block diagram of a first partial divider used in a second embodiment of a division operation device to which the present invention is applied.

FIG. 8 is a block diagram showing a configuration of a second partial divider used in the second embodiment.

FIG. 9 is a block diagram showing the overall configuration of a division operation device of the first embodiment, the second embodiment, or the conventional example.

FIG. 10 is a diagram showing a first example used in the division operation device of the conventional example.
Block diagram showing the configuration of the partial divider

FIG. 11 is a block diagram showing a configuration of a second partial divider used in the conventional example.

FIG. 12 is a block diagram showing a configuration of a third partial divider used in the conventional example.

FIG. 13 is a block diagram showing a configuration of a fourth partial divider used in the conventional example.

[Explanation of symbols]

 X ... Register (or dividend data) X15-X0 ... Dividend bit data Q ... Register (or quotient data) Q15-Q0 ... Quotient bit data D15-D0, Dn ... Partial divider T14-T0, Tn ... Register J15-J0, Jn ... Subtractor S15-S0, Sn ... Partial remainder selection circuit F15-F0, Fn ... Operation result prediction circuit W14-W0, Wn ... Dividend data A15-A0, An ... Subtraction operation result B15-B0, Bn ... Subtraction result sign E15-E0, En ... Selection control signals R15, R1, Rn ... Partial remainder R0 ... Final remainder of division GA15-GA0 ... OR logic gate GB14-GB0 ... AND logic gate

Claims (3)

[Claims] 1. Partial remainder data R (n +) up to that point
The partial dividend data Wn is obtained by adding the dividend bit data Xn sequentially fetched from the MSB side of the dividend data X to the LSB side of 1), and subtracting the divisor data Y from the partial dividend data Wn as a partial division operation. Then
When the subtraction operation result An is positive, the subtraction operation result An
Is the partial remainder data Rn of the partial division operation at this time, and the bit data Qn corresponding to the partial division operation at this time of the quotient data Q is "1", while the subtraction operation result An is negative, The partial dividend data Wn is used as the partial remainder data Rn of the partial division operation at this time, and the bit data Qn corresponding to the partial division operation of the quotient data Q at this time is set to "0" to perform such partial division operation. In the division operation device which repeatedly obtains the quotient data Q, subtracts the divisor data Y from the partial dividend data Wn, outputs the subtraction operation result An, and determines whether the subtraction operation result An is positive. Alternatively, a subtracter Jn that outputs a subtraction result code Bn indicating whether it is negative and a subtractor Jn that is based on the dividend data X before the subtraction operation is completed. The subtraction result code B
A calculation result prediction circuit Fn for predicting that n becomes negative, and when the calculation result prediction circuit Fn predicts that the subtraction result code Bn is negative, the partial dividend data Wn
And a partial remainder selection circuit Sn for selecting as the partial remainder Rn of the partial division operation at this time. 2. The operation result prediction circuit Fn according to claim 1, wherein
When the subtraction result code Bn is predicted to be negative in n, the bit data Qn corresponding to the partial division operation of the quotient data Q at this time is set to " A division operation device characterized by being 0 ". 3. The operand bit according to claim 1, wherein the operation result prediction circuit Fn extracts the target divisional operation corresponding to the partial division operation of the dividend data X with respect to the target divisional operation. All bit data X _MSB on the MSB side from this, including the data X _n
When all Xn are "0", the subtraction result code B
A division calculation device characterized by predicting that n is negative.