JPH07160217A - Color gradation display system and color gradation display device - Google Patents

Abstract

(57) [Abstract] [Purpose] When displaying more gradations than it has on a color LCD with few gradations, there is no color deviation within the frame and the area / frame is minimized. To obtain a color gradation display system and device which realize rate modulation. [Structure] Means 8 for generating a phase difference between each component signal while inputting a vertical synchronizing signal and keeping the brightness constant.
The offset value of each component signal is obtained by the following, and the offset of each component signal is added to the output value of the two-dimensional dither table 7 selected by the count value of the horizontal counter 5 and the count value of the vertical counter 6 for each component signal. Gets the dither value of. Frame memory 1
By adding the dither value for each component signal to the data of the lower bits which are not displayed, the carry of each component signal is generated and it is determined whether or not the gradation to be displayed is incremented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention makes it possible to display more gradations than a display device has by using a digital display device having a small number of gradations, for example, an LCD (liquid crystal display device). The present invention relates to a color gradation display system and a color gradation display device.

[0002]

2. Description of the Related Art In recent years, LCD (Liquid Crystal Display)
The technology has rapidly progressed, LCDs capable of multi-gradation display have been developed, and are expected to be applied to large-screen TVs and as output devices of multimedia computers. However, in order to realize full color, which requires 256 gradations for each component color (R, G, B), a high-speed and high-accuracy driver is required, resulting in high cost. Therefore, a method of displaying a large number of gradations on an LCD having a small number of gradations has been adopted.

Conventionally, in order to display more gradations on an LCD having less gradations, frame rate modulation and
A method that combines area modulation has been taken. For example,
As can be seen in JP-A-63-287828 and JP-A-2-993, when a two-dimensional pattern that changes in a frame period is used on the basis of a black and white LCD, when one pixel is focused, it is time-wise. By obtaining the halftone at the same time as obtaining the halftone, the display image with less flicker is obtained due to human visual characteristics.

FIG. 5 shows a conventional monochrome area / frame rate modulation system.

The dither pattern is a set of two-dimensionally different integer values. For example, in the case of a pattern of 2 rows and 2 columns, it has a numerical value of 0 to 3. The dither pattern generation means 90 has a plurality of two-dimensional dither patterns, for example, four types, and controls so that the dither pattern used in the frame is changed every time the frame is changed. In other words, it has a three-dimensional dither value.

The dither pattern generating means 90 includes a horizontal counter 5 which counts up according to a pixel clock, a horizontal coordinate X (a binary value of 0 or 1 in the example), and a vertical counter 6 which counts up according to a horizontal synchronizing signal.
From the frame counter 9 that counts up the vertical coordinate Y (binary value of 0 or 1 in the example) by the vertical synchronization signal from the frame counter 9 (4 in the example of 0 to 3).
Value) and select the dither value corresponding to the current pixel position.

On the other hand, the monochrome frame memory 71 is usually composed of a dual port memory, and the stored M-bit image information is adjusted by the display timing control means 4 in accordance with the display timing of the monochrome LCD 73 and its driver circuit 72. , Transmitted from the serial port. Of the M-bit data, the lower (MN) bits are added to the previously selected dither value, and if carry occurs, it is transferred to the LCD driver circuit 72 by the incrementer 30. 1 is added to the upper N bits of the image data.

This area / frame rate modulation is simply applied to color display data, and each component signal (R,
FIG. 6 shows an example in which G and B) are modulated by the same two-dimensional dither pattern.

The 2nd row and 2nd column dither pattern is added to the 2nd row and 2nd column input data, and carry to the upper digit occurs, and the upper bit of the pixel to be displayed changes to the brighter side. The ones are shown by □, and the ones that do not change are shown by ■. The luminance at the top is the sum of the luminance changes for each of the three components below it.

Focusing on a certain pixel, 0 to 3 can be obtained in a short cycle.
It can be seen that there is a full swing and the brightness changes drastically.

[0011]

However, the above method is basically intended for a monochrome LCD and is not suitable for a color LCD. This is because one black and white pixel is considered to correspond to each color component signal (R, G, B), and when the above method is applied, one component signal is emphasized at a certain fixed cycle and the The entire screen turns reddish or bluish. Further, when R, G, and B are collectively treated as one pixel and each component signal is changed in the same phase, the displacement of luminance is three times the displacement of each of R, G, and B. Flicker becomes noticeable.

In view of these drawbacks, it is an object of the present invention to provide a color gradation display system and a color gradation display device in which color deviation within a frame is eliminated and flicker is minimized.

[0013]

In the color gradation display system according to the present invention, each component signal (R, G, B) display data of M bits from the frame memory storing color image data is displayed as each component signal. To display on a color display device that inputs N bits each (has 2 ^N gradations), the dither pattern of K (= 2 ^MN ) gradations changed in the frame cycle is used. Area that controls the ON / OFF ratio by the frame rate and area for the data of MN bits that are not displayed.
In a color display device that performs a frame rate modulation method, three offset values corresponding to each component signal are generated each time a frame changes, these offset values are added to a common dither table value, and K modulo operation is performed. It is characterized in that each component signal produces a different dither pattern, and each component signal individually performs area modulation.

Further, the color gradation display device according to the present invention comprises a frame memory having M bits for each component signal, a display timing control means for controlling a serial port output of the frame memory and an LCD display timing, and the display. A horizontal counter that increments with the pixel clock that is the output of the timing control means, a vertical counter that increments with the horizontal synchronization signal that is the output of the display timing control means, and a vertical synchronization signal that is the output of the display timing control means. A component signal phase difference generating means for generating offsets of (M−N) bits having different phases in G and B in R, G, and B respectively, an output m bits of the horizontal counter and an output n bits of the vertical counter. As input (2
^m ) × (2 ⁿ ) common dither pattern generating means for selecting one from the dither table, the output of the common dither pattern generating means, and the R signal output of the component signal phase difference generating means are added (MN) An R signal dither pattern generating means for generating a bit R signal dither pattern, an output of the common dither pattern generating means and a G signal output of the component signal phase difference generating means are added (MN).
G signal dither pattern generating means for generating a G signal dither pattern of bits, the output of the common dither pattern generating means and the B signal output of the component signal phase difference generating means are added to generate a (M−N) bit B signal dither pattern. B signal dither pattern generating means, an R adder for adding the (MN) bit output of the R signal dither pattern generating means and the lower (MN) bit of the R output data of the frame memory, and the G signal dither pattern. A (G-N) bit output of the generation means and a G adder for adding the lower (M-N) bits of the G output data of the frame memory, an (M-N) bit output of the B signal dither pattern generation means and the Lower order of B output data of frame memory (M-N)
A B adder for adding bits, a carry from the R adder, an N-bit R incrementer receiving the upper N bits of the R output data of the frame memory as an input, a carry from the G adder and the frame memory An N-bit G incrementer that inputs the upper N bits of the G output data, a carry from the B adder, and a B of the frame memory.
An N-bit B incrementer that inputs the upper N bits of output data, an output N bit of the R incrementer, an output N bit of the G incrementer, and an output N bit of the B incrementer are input to the driver. It is characterized by having a display device of 2 ^N gradation.

[0015]

The above-mentioned object is to keep the sum of the three component signals substantially constant in the frame period and generate offsets having different phases, and to add the dither pattern (area modulation pattern) to the phase of each component signal. Of different dither patterns and thereby subjecting the display data to area modulation.

In this case, sinusoidal function generators or tables that are 120 degrees out of phase with each other are used to obtain offsets with different phases while keeping the sum of the three component signals constant.

When one pixel on the display screen is focused by modulating the display data by the area / frame rate modulation of the above method, the component signals (R, G,
Since the brightness obtained by combining B) is kept substantially constant, the occurrence of flicker can be minimized due to the characteristics of the human eye, which is more sensitive to brightness than hue.

Further, by changing the input to the sine function generator or the table close to 180 ° each time the frame changes, the frequency of hue change can be maximized (close to half the frame frequency), and further, the flicker can be suppressed. Occurrence can be suppressed.

Further, due to the effect of the dither pattern, the two-dimensional color phase difference is canceled out by the neighboring pixels, so that the color deviation in the frame is eliminated and the two-dimensional flicker becomes inconspicuous.

With the above three effects, it is possible to display a color multi-gradation that is more natural to the human eye.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the arrangement of a color liquid crystal display device including the color gradation display device according to the embodiment.

In FIG. 1, reference numeral 1 is a frame memory for storing color image data, each of which outputs display data of component signals (R, G, B) of M bits.

Reference numerals 2 and 3 denote an LCD driver circuit and an LCD capable of color-displaying N-bit gradation (2 ^N gradations).
(Liquid crystal display device).

Reference numeral 4 is a display timing control means for displaying the output timing of the serial port of the frame memory 1 on the LCD 3.
It is controlled in synchronization with the display timing control of.

Reference numeral 5 is a horizontal counter which is incremented by a pixel clock which is an output of the display timing control means 4, 6 is a vertical counter which is incremented by a horizontal synchronizing signal which is an output of the display timing control means 4, and 7 is an output m of the horizontal counter 5. Bit and the output n bits of the vertical counter 6 are input, a K (= 2 ^MN ) gradation is generated from a (2 ^m ) × (2 ⁿ ) dither pattern table and one gradation is selected (common dither table Dither pattern generation means),
Reference numeral 8 is different from each other for each of the component signals (R, G, B) according to the vertical synchronizing signal from the display timing control means 4, that is, every time the frame changes.
It is a component signal phase difference generating means for generating in the state of an integer of (M−N) bits with one phase difference as an offset.

Reference numerals 10, 11, and 12 are adders for adding two (M-N) -bit integers to obtain (M-N) bits. That is, the adder 10 uses the dither table 7
The dither pattern value of one gradation output from the R signal is added to the R offset value output from the component signal phase difference generating means 8 to generate an (M−N) -bit R signal dither pattern value. The adder 11 adds the dither pattern value of one gradation output from the dither table 7 and the G offset value output from the component signal phase difference generating means 8 to obtain a (M−N) -bit G signal dither pattern value. Is generated. And the adder 12
Adds the dither pattern value of one gradation output from the dither table 7 and the B offset value output from the component signal phase difference generating means 8 to generate a (M−N) -bit B signal dither pattern value. It is a thing.

Reference numerals 20, 21, and 22 are R, G, and B adders for adding two (M−N) -bit integers to generate a 1-bit carry. That is, R adder 2
0 is for adding the R signal dither pattern value from the adder 10 at the previous stage and the lower (MN) bits not displayed among the M bits of R data output from the frame memory 1 to generate an R carry. Is. The G adder 21 adds the G signal dither pattern value from the adder 11 at the previous stage and the lower (MN) bits of the M bits of G data output from the frame memory 1 that are not displayed to obtain a G carry. It occurs. The B adder 22 uses the B signal dither pattern value from the previous stage adder 12 and the frame memory 1
B carry is generated by adding the lower (MN) bits that are not displayed among the M bits of B data output from.

Reference numerals 30, 31, and 32 respectively input N-bit data and a carry, output the input data as it is when the carry is 0, and add 1 to the input data when the carry is 1 and output it. It is That is, the R incrementer 30 includes the R data of the upper N bits from the frame memory 1 and the R adder 20.
The above process is performed by using the R carry from the input. The G incrementer 31 receives the G data of the upper N bits from the frame memory 1 and the G carry from the G adder 21 and performs the above process. The B incrementer 32 receives the B data of the upper N bits from the frame memory 1 and the B carry from the B adder 22, and performs the above process.

The LCD driver circuit 2 includes the N-bit R data from the R incrementer 30 and the G incrementer 3.
Input the N-bit G data from 1 and the N-bit B data from the B incrementer 32, and input 2 ^N to the LCD 3.
Color display of gradation is performed.

With the above configuration, based on the dither pattern value of K (= 2 ^MN ) gradation changed in the frame period,
An area / frame rate modulation method is realized in which the ON / OFF ratio is controlled by the frame rate and area for the lower (MN) bits that are not displayed in the M-bit data from the frame memory 1.

The component signal phase difference generating means 8 in FIG. 1 is constructed as shown in FIG. 2 (a) or 2 (b).

In FIG. 2A, 40 is a flip-flop for storing a phase difference, 41 is a J addition for performing addition of J (= 3 × K / 2 + 1 or 3 × K / 2−1) and 3 × K modulo operation. The device 43 is a vertical sync assert detection means for detecting that the vertical sync signal is asserted and generating a pulse shorter than the vertical sync signal. The flip-flop 40, the J adder 41, and the vertical synchronization assert detection means 43.
And are three component signals with a phase of 120
In order to generate a phase difference shifted from each other, minimize the time variation rate of the brightness of one pixel, and maximize the frequency of hue change, 3 × K / 2 + 1 or 3 × K / 2 in the vertical sync signal.
That is, −1, that is, a K × ternary counter that is not 180 degrees in phase but counts up with a discrete value closest to it is configured.

Reference numerals 44, 45, and 46 denote (M-N) in a state where the phase, which is the count value input from the K × ternary counter, is normalized so that one cycle is K × 3 steps. ) Sine function generating means or sine function table (here, sine function generating means) for generating a sine function value as an integer value of bits. That is, the sine function generating means 44 for R outputs the R signal offset each time the frame changes, the sine function generating means 45 for G outputs the G signal offset each time the frame changes, and the sine function generating for B is generated. Means 46 outputs the B signal offset each time the frame changes.

In FIG. 2B, 40 is a flip-flop for storing the phase difference, 41 is J addition for performing J (= 3 × K / 2 + 1 or 3 × K / 2−1) addition and 3 × K modulo operation. And 42 is K for performing K addition and 3 × K modulo operation.
An adder, 43, detects vertical assertion of the vertical sync signal, and generates vertical pulse shorter than the vertical sync signal, and 44 indicates vertical sync assert detection means. 44 designates (M-N) bit alignment for the input phase. A sine function generating means or a sine function table (herein referred to as a sine function generating means) for generating a sine function value as a numerical value, and 47 selects the result of the J adder 41 and the K adder 42 according to the signal of the timing generating means 48. Selectors 50, 51 and 52 are latch means.

Reference numeral 48 changes the phase difference three times after detecting the assertion of the vertical synchronizing signal so as to latch the sine function values having different phase differences of R, G and B, and stores the same in the flip-flop 40 to generate the sine function. It is a timing generating means for controlling the value of the means 44 so as to be correctly latched by the three latch means 50, 51, 52.

An example of four gradation sine function table values used in FIG. 2A is shown below.

[0038]

[Table 1]

Similarly, an example of 16 gradation sine function table values is shown below.

[0040]

[Table 2]

It should be noted here that the average table value of each component signal is (K-1) / 2.
It is necessary to modify so that By configuring as shown in FIG. 2B, one table may be read three times while changing the phase, and latched each time.

The operation of the color liquid crystal display device configured as described above will be described with reference to the flowchart of FIG.

After the reset is input, the phase difference Fn stored in the flip-flop 40, the value Vcnt stored in the vertical counter 6 and the value Hcnt stored in the horizontal counter 5 are cleared to 0 in step S1.

Next, in step S2, the component signal phase difference generating means 8 sets J (fstep in the flowchart) to the previous phase difference Fn stored in the flip-flop 40.
3 × K (in the flow chart, ste
p) modulo operation is performed to update the value of the flip-flop 40. Phase angle J at this time (in the flowchart,
fstep) is not 180 °, but the closest discrete value is selected. That is, when it is 3 × K steps, 3
Select xK / 2 + 1 or 3xK / 2-1.

At the same time, with respect to the new phase difference Fn, the signals of the phase difference Fn are inputted to the three sine function generating means 44, 45, 46 having a mutual correlation with the component signals, and the offset values of the respective component signals are inputted. (In the flowchart, r_offset, g_offset, b_offs
et).

Incidentally, as these functions, 360 °
(3 × K steps), the sum of the component signals is a substantially constant value, and the output value is from 0 to (K−
Any function can be selected as long as it is a function that is normalized so as to be 1). In this example,
A sine function that is easy to make the sum of the three functions constant is used. Note that 44, 45, and 46 are sine function generating means having a phase difference of 120 ° different from each other, which may be obtained by referring to a table by some memory means or by a function generating calculator. Further, as shown in FIG. 2B, the sine function generating means to be prepared is only one shown by reference numeral 44, and three function values are obtained by shifting the phase K steps three times during the vertical blanking period. May be.

Next, in step S3, from one common two-dimensional dither table 7 selected by the horizontal counter 5 incremented for each pixel clock and the vertical counter 6 incremented for each horizontal synchronizing signal, One gradation dp of the dither pattern is selected, and the offset (r_offset, g_of of each component signal is selected.
fset, b_offset) and the dither pattern value for each adder 10,
11 and 12, the dither pattern value (rdp, corresponding to each component signal in the frame and the pixel).
gdp, bdp) is calculated.

The same effect can be obtained by a method in which the dither pattern for such a series of three component signals is not calculated in real time each time but is calculated in advance and stored in a table.

Next, in step S4, the frame memory 1
The pixel data (rdata, gdata, bdata) of M bits corresponding to each component signal is received from.

Next, in step S5, the dither pattern value rdp of the component signal R obtained in step S3 and the lower (MN) bits of rdata input in step S4 are converted by the (M-N) -bit R adder 20. When a carry is generated by addition, the R incrementer 30 increments the upper N bits of rdata by 1 to obtain rddata. Similarly, the lower (MN) bits of gdata and the lower (MN) bits of gdp and bdata.
Each of the bits and bdp is added by the (M−N) -bit G adder 21 and the B adder 22, and the carry of each is propagated by the G incrementer 31 and the B incrementer 32, and the upper N bits gddata and bddata are transmitted. obtain.

Then, in step S6, the upper N bits of rddata, gddata, and bddata obtained in step S5 are set to the LCD.
Send to the driver circuit 2.

Next, in step S7, the horizontal counter 5 is incremented in synchronization with the pixel clock.

In step S8, it is determined whether or not it is during the horizontal synchronization period, and the horizontal synchronization signal indicates the display timing control means 4
If not output from step S3, the process returns to step S3.

When the horizontal synchronizing signal is being output,
In step S9, the vertical counter 6 is incremented and the horizontal counter 5 is cleared to 0.

In step S10, it is determined whether or not the vertical synchronizing period is reached. If the vertical synchronizing signal is not output from the display timing control means 4, the process returns to step S3.
When the vertical synchronizing signal is output, step S1
The vertical counter 6 is cleared to 0 by 1 and the process returns to step S2.

FIG. 4 shows an example in which the area / frame rate modulation method of the present invention is applied to a 4-gradation dither pattern. It can be seen that the variance of the luminance change in each pixel is smaller than the result of the conventional configuration in FIG. 6 for the luminance which is the total of each component signal. 2 × 2
The total brightness of a block of pixels is 5-7 in the conventional method.
However, in the present invention, it is as small as 5 to 6. That is, according to the present invention, an LC having a small number of gradations
It is possible to display a large number of color gradations on a color display device such as D with the occurrence of flicker minimized and without color deviation within a frame.

[0057]

According to the present invention, an LC having a small number of gradations
It is possible to display a large number of color gradations on a color display device such as D with the occurrence of flicker minimized and without color deviation within a frame.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a color gradation display device according to an embodiment of the present invention.

2A and 2B show a specific configuration of a component signal phase difference generating means in an embodiment, FIG. 2A is a configuration diagram when three sine function generators or sine function tables are used, and FIG. Sine function generator or sine function table 1
It is a block diagram when two are used.

FIG. 3 is a flowchart showing a control procedure of the embodiment.

FIG. 4 is a schematic diagram of a display example according to the area / frame rate modulation method of the embodiment.

FIG. 5 is a block diagram showing a configuration of a display device according to a conventional area / frame rate modulation method.

FIG. 6 is a schematic diagram of a display example according to a conventional area / frame rate modulation method.

[Explanation of symbols]

1 ... Frame memory 2 ... LCD driver circuit 3 ... LCD 4 ... Display timing control means 5 ... Horizontal counter 6 ... Vertical counter 7 ... Dither table (common dither pattern generating means) 8 ... Component signal phase difference Generating means 10, 11, 12 ... Adder 20 ... R adder 21 ... G adder 22 ... B adder 30 ... R incrementer 31 ... G incrementer 32 ... B incrementer 40. Flip-flop 41 ... J adder for J (= 3K / 2 ± 1) addition and (3 × K) modulo operation 42 ... K adder for K addition and (3 × K) modulo operation 43 ... Vertical Synchronous assert detecting means 44, 45, 46 ... Sine function generating means or sine function table 48 ... Timing generating means 50, 51, 52 ... Latch means

Claims (4)

[Claims] 1. Color of input (having 2 ^N gradations) of display data of M bits each of component signals (R, G, B) from a frame memory storing color image data and input of N bits of each component signal. To display on the display device, a dither pattern of K (= 2 ^MN ) gradations changed in the frame period is used, and in the display data from the frame memory, the data of MN bits which are not displayed are displayed in the frame rate and the area. In a color display device that performs an area / frame rate modulation method that controls an on / off ratio, three offset values corresponding to each component signal are generated each time a frame changes, and these offset values are used as a common dither table value. And add K and modulo K to create separate dither patterns for each component signal, Color gradation display method, characterized by separately modulating area on the component signal. 2. A method for generating an offset for each component signal of the area / frame rate modulation method according to claim 1 is such that the period is discretized in 3 × K steps, and the total sum of each component signal is a substantially constant value. Next to
The color gradation display method according to claim 1, wherein each output value is normalized so as to be a discrete value of 0 to (K-1). 3. A frame memory having M bits for each component signal, display timing control means for controlling the serial port output of the frame memory and LCD display timing, and incrementing with a pixel clock output from the display timing control means. A horizontal counter, a vertical counter that increments with a horizontal sync signal output from the display timing control unit, and a vertical sync signal output from the display timing control unit that have different phases in R, G, and B (M− N) A component signal phase difference generating means for generating an offset of R, G, B respectively, and (2 ^m ) × (2 ⁿ ) with m bits of output of the horizontal counter and n bits of output of the vertical counter as inputs. Common dither that selects one from the dither table in And Tan generating means adds the R signal outputs of said component signal phase difference generating means of the common Dizapatan generating means (M-
(N) R signal dither pattern generating means for generating an R signal dither pattern, the output of the common dither pattern generating means and the G signal output of the component signal phase difference generating means are added (M−
G signal dither pattern generating means for generating N) bit G signal dither patterns, the output of the common dither pattern generating means and the B signal output of the component signal phase difference generating means are added (M−
B signal dither pattern generating means for generating N) bit B signal dither patterns, (M-N) bit outputs of the R signal dither pattern generating means and lower (M-) bits of the R output data of the frame memory.
R adder for adding N) bits, (M−N) bit output of the G signal dither pattern generating means and lower (M−) of the G output data of the frame memory.
G adder for adding N) bits, (M-N) bit output of the B signal dither pattern generating means and lower (M-) of B output data of the frame memory.
N) B adder for adding bits, a carry from the R adder and an N-bit R incrementer having the upper N bits of the R output data of the frame memory as an input, and a carry from the G adder and the frame An N-bit G incrementer that receives the upper N bits of the G output data of the memory, a carry from the B adder, and an N-bit B incrementer that inputs the upper N bits of the B output data of the frame memory. , The output N bit of the R incrementer, the output N bit of the G incrementer, and the output N of the B incrementer
A color gradation display device, comprising: a 2 ^N gradation display device in which bits are input to a driver. 4. When the component signal phase difference generating means sets the generated dither gradation to K (= 2 ^MN ), three component signals generate a phase difference of 120 ° out of phase with each other, and A vertical sync signal which is the output of the serial port control means so as to minimize the temporal rate of change of the brightness of the pixel and maximize the frequency of the hue change,
K × 3/2 + 1 or K × 3 / 2-1, that is, a K × ternary counter that is not 180 ° as a phase but counts up with a discrete value closest to it, and the count value of the K × ternary counter is input to 1 A sine function generator normalized to have a period of K × 3 steps or a table storing sine function values and generating an offset of each component signal every frame change. Item 3. A color gradation display device according to item 3.