JPH07169909A - Highly integrated circuit - Google Patents

Abstract

(57) [Summary] (Correction) [Object] To realize a suitable LSI mounting method in an information processing apparatus, in particular, in order to suppress the influence of timing delay, which is a problem when operating logic at high speed. [Configuration] In an LSI, a connection socket for the same signal is provided on the lower part of the signal pin, and a common bus signal such as a CPU bus and a system bus is assigned to the signal of the LSI, and a plurality of the LSI
Are mounted by stacking, or a common bus signal is transmitted to a plurality of L
A high-speed signal is connected in the shortest distance by being configured by SI, mounted according to the pin arrangement of the LSI having the common bus signal, and mounted on these LSIs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI mounting method suitable for a logic circuit board such as an information processing device, and particularly for suppressing the influence of a timing delay which is a problem when operating at high speed such as a data bus and a clock. .

[0002]

2. Description of the Related Art In a conventional logic circuit board, QFP, PL
By using small-sized surface mount components such as CCs and mounting them on a substrate at a high density, the signal pattern between the components is shortened, the inductance component of the pattern is reduced, and the signal timing delay is suppressed. Further, with regard to a single component, the speed has been increased by further miniaturizing each module and highly integrating a plurality of modules such as a VLSI or a multi-chip module. These technologies have been mainly used for high-speed logic such as CPU peripherals and cache memory, but also speed up the system bus configured by signals for memory, I / O control, etc. for function expansion in the information processing apparatus. However, optimization of signal patterns is required even when connecting option boards to the system bus.

Known examples of these conventional techniques include Japanese Patent Laid-Open No. 4-58587.

[0004]

SUMMARY OF THE INVENTION The present invention realizes mounting of an LSI that shortens a signal pattern length in satisfying high-speed operation in a logic circuit board, and a signal timing delay when designing a pattern on the board. It is to simplify the calculation (analog simulation). Also, LS
It is to realize a design method that is not affected by the board mounting method when using I.

Further, the function pattern of the system bus for function expansion is also shortened to reduce the timing constraint at the time of function expansion and to easily enhance the product.

[0006]

In order to realize a high-speed operation of a logic circuit, in order to connect a bus signal to an LSI in the shortest distance, the following means for directly connecting a plurality of LSIs without a substrate pattern. To provide.

In a highly integrated circuit (LSI) sealed with a mold or ceramic, a pin socket to which the same signal is connected is arranged on the surface opposite to the signal pin. Bus signals such as data and addresses are internally connected to the pin sockets. These LSIs are stacked and bus signals are connected at the shortest distance.

Further, in order to realize a design method which is not affected by the mounting method of the board when using the LSI, the LSI is arranged in accordance with the pin arrangement of the LSI in the logic circuit composed of the plurality of the LSI. The problem can be solved by mounting an LSI on it.

Further, the connection pins of the LSI are configured by a system bus for function expansion and the I / F signal of the device, the adapter of the expansion device is built in the LSI, and the I / F signal of the device is taken out to the outside. Function expansion can be easily realized.

[0010]

In the mounting method of the LSI of the present invention, the connection distance between the LSIs is determined by the connection pins and the internal pattern of the LSI, and the timing delay and signal interference are not affected by the pattern on the substrate.

Therefore, the simulation for high-speed operation may be carried out mainly by the LSI.

By configuring the connection pins of this LSI with the system bus and the device connection signal, one extended function can be realized on the LSI. Furthermore, even if a plurality of LSIs are stacked and mounted, the function is extended. Easy to implement.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of claims 1 to 4 of the present invention is shown in FIG.
It will be described with reference to FIG. FIG. 1 is an external view of the present LSI, FIGS. 2 and 3 are mounting diagrams using the present LSI, FIG. 4 is a mounting diagram of a system device, and FIG. 5 is a circuit block diagram. LSI1
The semiconductor chip 1b is mounted on the wafer 1a, the signal line of the semiconductor chip 1b is connected to the signal pin 2 by the bonding wire 1c, and these are sealed with a mold or ceramic. The signal pin 2 is a connection pin 2a for connecting to a substrate at the bottom of the LSI 1 and a connection socket 2b at the top.
Composed of. The connection socket 2b is arranged so that the LSI 5 can be connected. With respect to the structure, a known example is a piggyback type CPU or the like, but the one connected to the upper part is a ROM or the like, which is mainly intended for debugging, and is intended for high-speed operation of the logic circuit in the present invention. It wasn't what was said. The signals of the LSI are composed of addresses, data, control signals and the like, and these signals are connected to the signal pin 2. In the present invention, the connection socket 2b is mainly described as a PGA type, but the socket can be mounted in other forms in the same manner by adapting the shape of the socket to an imposition type PLCC, QFP, or the like. .

In the information processing apparatus 10, as shown in FIG. 5, an LSI for controlling memory and I / O, such as a memory controller 12, an interrupt controller 13, a timer controller 14, and a DMA controller 15, is provided around the CPU 11 due to the circuit configuration. It is connected to the common CPU bus 20. FIG. 2 shows an embodiment in which these LSIs are arranged at the shortest distance in order to operate at high speed. CPU1 for LSI1
1 and a memory controller 12 are built in, and the LSI 5 has an interrupt controller 13, a timer controller 14, and a D controller.
The MA controller 15 and the like are incorporated. By configuring the signals of the LSI with the signals of the bus 20, the memory 21, the I / O 22 and the like, the LSI 5 can be mounted on the LSI 1. By defining the common bus in this way, a plurality of LSIs can be mounted in the shortest distance. However, the number of pins is limited due to the structure of the LSI, and the current PGA type has a limit of about 200 pins.

FIG. 3 shows an embodiment. By using the plurality of LSIs according to claim 1 and arranging the connection pins 2 so as to match the pins of the LSI 30, it becomes possible to configure a common bus with a plurality of LSIs, and the constraint on the number of pins according to claim 2 Can be resolved. The LSI 30 is a normal PGA
You can also use the type.

In the circuit block diagram of FIG. 5, the system bus 23 includes a memory controller 12, an interrupt controller 13, a timer controller 14, and a DMA controller 1.
5, such as a plurality of adapters 40 to 4n configured from control signals from the LSI and having a memory and I / O on the bus.
Are connected. The adapters 40 to 4n are individually connected to devices 50 to 5n such as a file device, a display device, and a power supply device via connection I / F signals 60 to 6n.

The LSIs 90 to 9n are the adapters 40 to 4n.
And the connection pins connect to the system bus 21.
The / F signals 60 to 6n are used to stack the LSIs and connect the signals at the shortest distance.

The connection I / F signals 60 to 6n can be connected to the devices 50 to 5n via the connection connectors 80 to 8n on the substrate 70 and mounted on the apparatus. The board 70 can be mounted at an arbitrary position of the LSI by applying an FPC. In addition,
The lowermost LSI 90 may not require a lower connection pin.

As described above, according to the present invention, the optional function can be easily expanded on the system bus operating at a high speed, and the mounting space can be effectively utilized.

[0020]

According to the present invention, it is possible to connect a pattern of a logic circuit to the shortest and mount it on a board which is not affected by a timing delay, and realize a high speed operation of an LSI.
(RISC chip 50 MHz or higher, 100 Mips or higher) By applying the present invention to the high-speed logic section, the pattern design of the PK can be shortened.

Further, by applying it to the system bus, it is possible to provide an information processing apparatus whose function can be easily expanded.

Further, in mounting the device, when the height on the substrate has a margin, by stacking the LSIs, the substrate area can be reduced and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is an external view of an LSI that is an embodiment of the present invention.

FIG. 2 is a mounting diagram of an LSI that is an embodiment of the present invention.

FIG. 3 is a mounting diagram of an LSI that is an embodiment of the present invention.

FIG. 4 is a mounting diagram of a system device of the present invention.

FIG. 5 is a circuit block diagram of a system device of the present invention.

[Explanation of symbols]

 1, 5, 30, 90 to 9n ... LSI, 2 ... Signal pin, 10 ... System device, 11 ... CPU, 12 ... Memory controller, 13 ... Interrupt controller, 14 ... Timer controller, 15 ... DMA controller, 20 ... CPU bus , 21 ... Memory, 22 ... I / O, 23 ... System bus, 40-4n ... Adapter, 50-5n ... Device, 60-6n ... I / F signal, 80-8n ... Connection connector, 70 ... Board.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical display location H05K 1/18 U 7128-4E S 7128-4E (72) Inventor Hideyuki Nagasawa Haruoka Town, Owariasahi City, Aichi Prefecture Ikegami No. 1 Hitachi Asahi Electronics Co., Ltd.

Claims (4)

[Claims] 1. In a highly integrated circuit (LSI) in which an IC, a diode, etc. are mounted on a wafer and sealed with a mold or a ceramic, a signal connection pin is arranged at the bottom and a pin socket for connecting the signal is arranged at the top. Highly integrated circuit characterized by. 2. A mounting system characterized in that a plurality of highly integrated circuits according to claim 1 are stacked to connect the signal lines at the shortest distance. 3. The mounting method according to claim 2, wherein a plurality of integrated circuits are arranged so as to match the pin arrangement of the highly integrated circuit, and the highly integrated circuit is mounted thereon. 4. The high-integrated circuit according to claim 3, wherein the connection pins are composed of a control signal of the system bus and an I / F signal of the device, and the I / F signal of the device is stacked from the high-integrated circuit by a cable or the like. An information processing device characterized by being connected.