JPH07152811A - LSI design support system - Google Patents

Abstract

(57) [Abstract] [Purpose] Assemble and design LSI chips and LSI packages to meet the assembly conditions and electrical attributes. Further, the inspection jig design for performing the functional inspection of the chip, the test pattern data generation data, and the LSI layout data are automatically created. [Structure] With respect to the chip and the LSI package input by the chip data input unit 11 and the LSI package data input unit 12, the external pin electrical attribute designation unit 13 sets L
While designating the electrical attributes of the external pins of the SI package and designating the connection between the external pins and the pads by means of the pin connection means, the assembly checking means 15 checks whether the assembly conditions in the assembly process are satisfied, and the electrical attribute checking means 16 externally. Interactively perform assembly design while checking whether the pad connected to the pin can be connected to the electrical attribute of the external pin.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI design support system, and more particularly to a system for realizing individual functions by first determining the LSI chip outline such as a gate array, pad coordinates, etc., and then laying out the inside of the chip. L
A jig for designing a part for incorporating an SI chip (hereinafter, referred to as an "ASIC chip" before the internal circuit is incorporated) into various LSI packages, a circuit layout design of the chip ((hereinafter referred to as a probe card Design) and an LSI design support system for designing a test pattern for inspecting the chip.

[0002]

2. Description of the Related Art A conventional LSI design support system is LS
When deciding the electrical connection between the I chip and the external pins of the LSI package, it was done manually whether or not actual assembly with a wire bonder was possible, but with the recent increase in the number of pins of the LSI chip and microfabrication, for example, JP-A-2-236
As shown in Japanese Patent Laid-Open No. 675, when a computer is used to electrically connect an LSI chip to an external pin of an LSI package, the LSI is interactively checked while checking whether or not it can be assembled by a wire bonder used in actual assembly. The connection relationship between the chip and the external pins of the LSI package is determined.

FIG. 5 is a block diagram showing an example of a conventional LSI design support system. The processing device 1 inputs data and gives an instruction for processing by the keyboard 3, the mouse 2, and the magnetic storage device 5 via the interface unit 22. In addition, a chip is stored in the storage unit 23 via the interface unit 22,
Data such as the LSI package, wires, and errors are output to the display 4, and the processing result is stored in the magnetic storage device 5,
Output to the printer 6 and plotter 7. The chip data input means 11 registers data regarding the chip, such as the chip outer shape and pad coordinates, in the storage unit 23 via the interface unit 22. Further, the contents of the chip data registered in the storage unit 23 can be changed by the chip data input means 11. LSI package data input means 1
2, the interface unit 22 registers data relating to the LSI package, such as the internal lead shape of the LSI package data and the external pin number connected to the internal lead, in the storage unit 23. The pin-connection means 14 is
The pads of the chip registered in the storage unit 23 and the bonding points on the internal leads of the LSI package are specified, and the position where the wire of the wire bonder is stretched is specified to specify the electrical connection between the external pin of the LSI package and the pad. . The assembly check means 15 uses the data on the position of the wire and the chip registered in the storage unit 23 and the data on the LSI package to determine the chip and the LSI.
When assembling the package by wire bonding, check if the wires are short-circuited or if they are short-circuited with other internal leads that are electrically independent of the wires. If an error is detected by the assembly checking means 15, the chip data input section 11 changes the pad position. Finally, the bonder data editing means 18 edits the drawing showing the assembled state of the LSI package and the chip by the wire, and outputs it through the interface section 22.

[0004]

DISCLOSURE OF THE INVENTION The conventional LSI described above
The design support system only checks whether the actual assembly conditions with a wire bonder or the like are satisfied when deciding the electrical connection between the pad and the external pin. In the ASIC chip in which the electrical attribute of the pad is not determined, the electrical attribute of the external pin of the LSI package is first determined, and then the pad electrically connected to the external pin is the electrical attribute of the external pin. Also, the pads of the ASIC chip cannot be made to have any electrical attributes, and there are restrictions on the electrical attributes that each pad can have, for example, No. 1 pad cannot be a 5 volt power supply. Therefore, it is not possible to check whether the pad connected to the external pin can be the electrical attribute of the external pin,
It is necessary to manually check again whether the pad connected to the external pin can be the electrical attribute of the connected external pin, which is troublesome and apt to cause mistakes.

In the ASIC chip, when the pads connected to the external pins and the electrical attributes of the pads are determined, it is necessary to design the internal circuit so that the pads connected to the external pins have the desired electrical attributes. L designing a circuit
It is necessary to prepare and input pad data to be connected to an external pin and data describing its attribute to the SI layout system. However, in the conventional technique, since the data does not have the electric attribute of the pad and the data is manually created, there is a problem that it takes time and error is likely to occur.

Further, in order to perform a functional test of the ASIC chip incorporating the internal circuit at the time of its completion, it is necessary to prepare a probe card as an inspection jig for connecting a needle to the pad and connecting it to the LSI tester. Don't
In its design, the position of the pad that is connected to the external pin must be set so that the terminals of the tester and the needle connected to the power supply that match the electrical attribute of the pad are set up. The probe card could not be designed on the system because I did not have attribute data. Therefore, since the probe card is designed by manually determining the position where the needle is raised, the electrical attribute, the terminal of the tester to be connected, or the power supply, there is a problem that it takes a lot of time and error is likely to occur.

In order to create an LSI test pattern to be used for a functional test of a chip performed by the probe card, which LSI tester is to be used in an actual test after designing a test pattern to be input / output from a pad of the chip. It is necessary to decide which test pattern should be output from the terminal, but in that case, conventionally, the connection relationship between the terminal and the pad of the LSI tester was manually input, which was troublesome and error-prone. .

[0008]

An LSI assembly design support system according to the first invention is a chip data input for inputting data such as an LSI chip outer shape, pad coordinates, electrical attribute conditions (signals, power supplies, etc.) that can be a pad. Means, an LSI package data input means for inputting data relating to the LSI package into which the chip is to be incorporated, input by the chip data input means, and an electrical attribute (signal, power supply, etc.) of the external pin of the LSI package input by the LSI package data input means are specified. External pin electrical attribute designation means, chip data input means, pin connection means for designating electrical connection between the chip pad input by the LSI package data input means and the external pin of the LSI package, and electrical connection designated by the pin connection means are chips. And the LSI package are actually assembled (die bond Assembly check means to check if the assembly conditions for wiring, wire bonding, etc.) are satisfied, and the chip pads have the same electrical attributes as the external attributes of the external pins of the LSI package connected by the electrical connection specified by the pin connection means. It is composed of electrical attribute checking means for checking whether or not it can be changed.

The ASIC layout design support system according to the second aspect of the invention provides a pad connected to an external pin determined by the first aspect of the invention and the electrical attribute of the pad for a system for designing a circuit on the chip. It is composed of a layout data editing means for editing data and each means of the first invention.

The chip inspection jig design system of the third invention specifies the connection of the LSI tester and the power source for inspecting the chip to the pad connected to the external pin determined by the first invention. It comprises a tester pin designating means and each means of the first invention.

The LSI test pattern design support system of the fourth invention is used for a test pattern creation system for inspecting a circuit of a chip, which is determined by the first and third inventions, regarding a connection relationship between a pad and a tester pin. It comprises test pattern data editing means for editing data, each means of the first invention, and tester pin designating means of the third invention.

[0012]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the LSI design support system of the present invention.

In the LSI design support system of this embodiment, as shown in FIG.
A keyboard 3, a mouse 2, and a magnetic storage device 5 are used to input data and instruct processing. Further, the data of the chip, the LSI package, the wire, the error, etc. of the storage unit 23 is output to the display 4 via the interface unit 22, and the processing result is output to the magnetic storage device 5, the printer 6, and the plotter 7. Chip data input means 1
1 registers the data relating to the ASIC chip in the storage unit 23, such as the chip outer shape, the pad coordinates, and the electrical attribute conditions of the pad via the interface unit 22. The LSI package data input means 12 receives the LS of the internal lead shape of the LSI package data and the external pin number connected to the internal lead via the interface section 22.
Data regarding the I package is registered in the storage unit 23.
The external pin electrical attribute designating means 13 is a plus power source for the external pins of the LSI package registered in the storage unit 23, and GN.
Designate electrical attributes such as D and signal. Pin connection means 14
Specifies the pad of the ASIC chip registered in the storage unit 23 and the bonding point on the internal lead of the LSI package, and indicates the position where the wire of the wire bonder is stretched to electrically connect the external pin of the LSI package to the pad. Is specified. The assembly checking means 15 does not short-circuit the wires when assembling the ASIC chip and the LSI package by wire bonding, based on the position of the wire registered in the storage unit 23, the data about the ASIC chip, and the data about the LSI package, or Check that it is not short-circuited with other internal leads that are electrically independent. The electrical attribute check unit 16 checks whether the pad connected to the external pin of the LSI package designated by the pin connection unit 14 can have the electrical attribute if the attribute of the external pin is designated. The tester pin designating means 17, for a pin-connected pad, has an LS that matches the attribute of the external pin connected to that pad.
The terminals of the I tester and the connection of the power supply are automatically specified.
It can also be manually specified by the operator. The bonder data editing unit 18 indicates the model of the wire bonder that actually assembles the ASIC chip and the LSI package registered in the storage unit 23, and all the wires registered in the storage unit 23 in the data format suitable for the model. The data of both end coordinates, that is, the pad coordinates, the bonding point coordinates on the inner lead, and the assembly drawing are automatically edited and the data is output through the interface unit 22.
The layout data editing means 19 specifies a CAD system that incorporates a circuit on the ASIC chip registered in the storage unit 23, and is connected to the outside of the LSI package registered in the storage unit 23 in a format suitable for the system. The pad number, the electrical attribute data of the external pin, and the drawing are automatically edited and the data is output via the interface unit 22. Test pattern data editing means 2
0 designates a system for creating a lick test pattern for performing a functional test of a chip in which a circuit is incorporated on the ASIC chip registered in the storage unit 23, and is registered in the storage unit 23 in a format suitable for the system. The pad number connected to the external pin, the terminal number data of the LSI tester designated to be connected to the pad, and the drawing are automatically edited and the data is output via the interface unit 22. Probe card design data editing means 21
Automatically prepares data and drawings for manufacturing the probe card from the pad coordinates of the pad connected to the external pin registered in the storage unit 23, the tester power supply specified for the pad, and the LSI tester terminal data. And edit the data to output the data via the interface unit 22.

FIG. 2 is a diagram for explaining the data output in the LSI design support system of this embodiment. External pin number 50, internal lead bonding point coordinate 51,
External pin attribute 52, pad number 53, pad coordinates 54,
The pad attribute condition 55, the tester power supply 56, and the tester terminal number 57 are registered in the storage unit 23 of FIG. The external pin number 50 represents the external pin number of the LSI package. The bonding point coordinates 51 on the internal lead represent the bonding point coordinates of the wire bonded on the internal lead connected to the external pin number on the left. The external pin attribute 52 represents the electrical attribute of the left external pin.
The pad number 53 represents the pad number of the chip electrically connected to the external pin shown on the left via a wire. The pad attribute condition 55 represents the electrical attribute condition of the pad on the left.
The tester power supply 56 represents a power supply connected to the pad on the left. The tester terminal number 57 represents an LSI tester terminal connected to the pad on the left. The bonder data 60 is data for a wire bonder that actually assembles a chip and an LSI package, and is generated from the bonding point coordinates 51 on the internal leads and the pad coordinates 54. The layout data 61 is data given to a CAD system that designs a circuit on an ASIC chip, and is generated from an external pin number 50, an external pin attribute 52, and a pad number 53. The probe card data 62 is specification data of the probe card, and is generated from the pad coordinates 54, the tester power supply 56, and the tester terminal number 57. Test pattern data 63
Is data for instructing from which LSI tester terminal the test pattern is to be output when the function test of the chip is performed by the probe card.
It is generated by the pad number 53 and the tester terminal number 57.

FIG. 3 is a diagram for explaining the assembly of the chip and the LSI package by the wire bonder. Chip 3
1 indicates that the pad 30 on the wiring 1 and the bonding point 35 on the internal lead 33 on the internal lead 33 connected to the external pin 34 of the LSI package are electrically connected by the wire 32.

FIG. 4 is a diagram for explaining the ASIC chip. Since the ASIC chip usually has the pad coordinates determined in advance, it has more pads than the number of external pins of the LSI package to be incorporated. In order to satisfy the assembly condition and the electrical attribute condition, the optimum pad is selected from among the many pads. Choose and use it. Also, when the selected pad incorporates an actual circuit, it becomes a pad for inputting / outputting a power source and a signal, and electrically connects the internal circuit and the external pin.
Also, the pads that were not used become dummy pads,
It has no electrical meaning.

Next, the operation will be described mainly with reference to FIG. 1 and supplementarily with reference to FIGS. 2, 3, and 4. The operator can graphically refer to the data in the storage unit 23, the error, and the like via the interface unit 22 via the display 4, and interactively perform the following operations. Chip data input means 11
The pad coordinates 54, the pad attribute conditions 55, etc. of the ASIC chip to be designed are input to the storage unit 23 by the
The LSI package data input means 12 registers the shape data of the LSI package in which the IC chip is to be incorporated into the storage unit 23. With respect to the external pins 34 of the registered LSI package, the external pin electrical attribute designating means 13 designates the external pins 34 to be GND. In addition, the pad 3 registered in the storage unit 23 by the pin connection means 14
0 and bonding point 3 on the internal lead of the LSI package
5 is designated to electrically connect the pad and the external pin 34 of the LSI package. In the assembly checking means 15, the wire 32 connecting the pad 30 registered in the storage unit 23 and the bonding point 35 on the inner lead is connected to the other inner lead 3.
If there is an error by checking whether it can be actually assembled by the wire bonder such as whether it is short-circuited with 3 or is far from the manufacturing error, the operator is immediately notified through the interface unit 22. Further, the pad 30 that is electrically connected to the pad 30 registered in the storage unit 23 by the electrical attribute check unit 16 and the external pin 34 of the LSI package is connected to the external pin 34 of the LSI package to which the electrical attribute of the external pin 34 can be set.
That is, it is checked whether or not the pad 30 connected to the external pin 34 having the electric attribute of GND has the electric attribute condition that can be the GND, and if there is an error, the operator is notified via the interface unit 22. While checking with the assembly check means 15 and the electrical attribute check means 16, the pin connection means 14 is repeatedly used to assemble the pad 30 as shown in FIG. The connection relationship with the external pin 34 is determined. Further, the determined connection relation is registered in the storage unit 23. From the completed data so far, the bonder data editing means 18 is instructed of a specific wire bonder model for assembling the chip 31 and the LSI package, and the wire bonder data of a format suitable for the model is automatically edited. Then, the data is output via the interface unit 22. With this data, the wire bonder can know the coordinate value of the wire 32.

Further, from the data completed up to this point, the layout data editing means 19 is instructed of the model of the LSI layout system for laying out individual circuits on this ASIC chip, and the layout data of the format suitable for the model is specified. Is automatically edited and output via the interface unit 22. This data allows the LSI layout system to know which pad 30 the terminal of the external pin 34 shown in the circuit diagram is connected to, and which pad 30 the GND and the power supply are connected to.
The circuit can be laid out on the IC chip.

Further, each pad (electrically meaningful pad when a circuit is later incorporated on an ASIC chip) 30 connected to the external pin 34 stored in the storage section 23 by the tester pin designating means 17 The power supply and the terminals of the LSI tester that match the electrical attributes are automatically assigned, and the tester power supply 56 and the tester terminal number 57 are completed on the storage unit 23. Further, it is possible to change the connection relation of the power source and the terminals of the LSI tester which are automatically assigned by the tester pin designating means 17.

Up to this point, the completed data in the storage unit 23, the pad coordinates 54 of the pad 30 connected to the external pin 34, the tester power supply 56 connected to the pad 30, and the tester terminal number 57 are stored in the probe card. The design data and the drawing are automatically edited by using the design data editing means 21 and output through the interface unit 22. With this data, it is possible to manufacture a probe card in which a probe card needle is raised at each pad coordinate and the needle is connected to each power source or an LSI tester terminal.

Further, from the data completed in the storage unit 23 up to this point, the external pin number 50 of the LSI package, the pad number 53 pin-connected to the external pin 34, the tester power supply 56 connected to the pad, and the tester terminal number. 57 to the test pattern data editing means 20.
And a chip 31 in which a circuit is incorporated in the ASIC chip.
The model of the system for creating the test pattern for inspecting is specified, the data and the drawing are automatically edited in the format suitable for the system for creating the test pattern, and the data and the drawing are output via the interface unit 22. This data makes it possible to know which terminal of the LSI tester should be used for input / output when actually testing the test pattern input / output from the circuit diagram terminal.

[0023]

As described above, the LSI design support system of the present invention is more accurate when determining the connection between the chip and the LSI package, in addition to checking the assembly conditions with a wire bonder, etc., it is more accurate. It is possible to determine the connection relation, to eliminate the need to check electrical attributes after design, to eliminate designing again, to reduce human error, to improve design accuracy, and to reduce time.

ASIC without adding new data
When designing an internal circuit in a later process such as a chip, LSI
Since design data for the layout system can be automatically generated, human error can be reduced and design time can be reduced.

A system for automatically designing an inspection jig (probe card) for connecting a chip and an LSI tester by a functional inspection performed after the chip diffusion process is completed, and for generating a test pattern used in the inspection. By automatically generating the auxiliary data for, there are the effects of reducing human error and design time.

Since checking, design, data, and drawings are almost automated, there is an effect that even an unskilled person can create designs, data, and drawings.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an LSI design support system of the present invention.

FIG. 2 is a diagram illustrating data output in the LSI design support system of the present embodiment.

FIG. 3 is a diagram illustrating assembly of a chip and an LSI package by a wire bonder.

FIG. 4 is a diagram illustrating an ASIC chip.

FIG. 5 is a block diagram showing a conventional LSI design support system.

[Explanation of symbols]

 1 Processing Device 2 Mouse 3 Keyboard 4 Display 5 Magnetic Storage Device 6 Printer 7 Plotter 11 Chip Data Input Means 12 LSI Package Data Input Means 13 External Pin Electrical Attribute Designating Means 14 Pin-Connecting Means 15 Assembly Checking Means 17 Electrical Attribute Checking Means 17 Tester Pins Designating means 18 Bonder data editing means 19 Layout data editing means 20 Test pattern data editing means 21 Probe card design data editing means 22 Interface section 23 Storage section 30 Pads 31 Chips 32 Wires 33 Internal leads 34 External pins 35 Bonding points on internal leads 50 External pin number 51 Bonding point coordinates on internal lead 52 External pin attribute 53 Pad number 54 Pad coordinate 55 Pad attribute condition 56 Tester power supply 5 Tester terminal number 60 bonder data 61 layout data 62 probe card data 63 test pattern data

Claims (4)

[Claims] 1. (A) LSI chip outline, pad coordinates,
Chip data input means for inputting data of electrical attribute conditions that can be pads, (B) LSI package data input means for inputting data on an LSI package in which the chip input in (A) is to be incorporated, (C) the (B) ), External pin electrical attribute designating means for designating the electrical attributes of the external pins of the LSI package, (D) the electrical connection between the chip pads input in (A) and (B) and the external pins of the LSI package. Pin connection means for designating, (E) Assembly checking means for checking whether the electrical connection designated in (D) above satisfies the assembly condition of the chip and the LSI package in the actual assembly work, (F) The pad of the chip is It may have the same electrical attribute as the external pin electrical attributes of the LSI package connected by the electrical connection specified in (D). Or electrical attributes checking means for checking, pad comprising: a city and LSI
LS that determines the electrical connection of the package and embeds the chip
An LSI assembly design support system that determines a pad electrically connected to an external pin of the LSI package for each I package. 2. The (A), (B), and
(C), (D), (E), for the system connected to the external pin determined by each means described in (F) and the electrical attribute of the pad, the system for designing a circuit on the chip Layout data editing means for editing data in
(A), (B), (C), (D),
An ASIC layout design support system comprising: each means described in (E) and (F). 3. (A), (B), and
(C), (D), (E), (F) The pads connected to the external pins determined by the respective means are designated to connect the LSI tester and the power supply for inspecting the chip. Tester pin designating means, (A) of claim 1
A chip inspection jig design system comprising: (B), (C), (D), (E), and (F). 4. (A), (B), and
(C), (D), (E), (F) each means, and the tester pin designating means according to claim 3 determines the connection relationship between the pad and the tester pin, the circuit of the chip is inspected. A test pattern data editing means for editing data for a test pattern creating system, and (A), (B), (C), (D), (E),
An LSI test pattern design support system comprising: each means described in (F); and the tester pin designating means according to claim 3.