JPH07152339A - Display controller - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a display control device capable of simplifying wiring with a display device regardless of a mounting direction or a mounting form with respect to a liquid crystal display device. [Configuration] Display R in which the character code is rewritably stored
AM4, a pattern memory 5 that generates a character pattern based on the code read from the display RAM, a drive circuit 10 that outputs a drive signal based on the character pattern generated from the pattern memory, and the CPU 1 accesses the display memory. The display control ROM 6 stores a correspondence relationship between the address to be read and the address for sequentially reading the display memory for displaying, and the information stored in the ROM 6 is changed as desired to display the display control device 2 and the liquid crystal display device. It is possible to simplify the wiring between 3 and.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control technique and further to a liquid crystal drive control technique, for example, to a technique effectively applied to a display control circuit of a dot matrix type character display liquid crystal drive device having a built-in character generator. .

[0002]

2. Description of the Related Art In a conventional liquid crystal display control device for displaying a dot matrix type character, a display memory for storing a character code, a character generator memory for storing a character font pattern, and a display memory are sequentially read out for display. It is composed of a display address counter for generating an address and a plurality of driver circuits for driving the liquid crystal. The CPU (Central Processing Unit) stores the character code to be displayed at the address of the display memory corresponding to the display position of the liquid crystal screen. The display address counter sequentially generates addresses in the display memory in synchronism with the actual display position, reads the character code, and uses this character code as part of the address to generate character font pattern data (character font data) from the character generator memory. ) Is read. The sequentially read character font data is sequentially sent to the shift register in the liquid crystal drive driver circuit as lighting / non-lighting data of the liquid crystal, and when the data for one line is accumulated, all the liquid crystal driver circuits simultaneously perform liquid crystal display. Drive the display panel.

Therefore, the correspondence between the address position of the display memory storing the character code and the liquid crystal driver output assigned from the plurality of liquid crystal driver outputs for displaying the character is fixed. For example, when the liquid crystal display panel displays a font pattern with 8 columns and 4 lines, the memory can store character codes for 8 columns and 4 lines. When the scanning signal lines such as the common electrodes of the liquid crystal display panel are sequentially driven downward from the upper edge of the liquid crystal display panel, the reading of the display memory is performed corresponding to the display position by the scanning signal lines. The order is uniquely determined by the increment / decrement direction of the value output by the increment or decrement operation of the address counter.

[0004]

However, when the number of outputs of the liquid crystal driver circuit increases, the wiring between the semiconductor integrated circuit incorporating the liquid crystal driver circuit and the liquid crystal display panel becomes dense, and the mounting of the integrated circuit becomes complicated. Will end up. For example, in the case of displaying 5 × 8 dot characters in 20 digits and 2 lines by 1/16 duty driving, 116 (20 × 5 + 8 × 2) wirings are required. For this reason, cross wiring may have to be complicated depending on which direction the liquid crystal display control device is mounted on the display surface of the liquid crystal display panel. May be restricted.

In order to simplify the wiring between the semiconductor integrated circuit which constitutes the liquid crystal display control device and the liquid crystal display panel, when the mounting wiring pattern of the semiconductor integrated circuit is exchanged, the CPU responds to this wiring exchange. It is necessary to write the character code according to the address allocation of the display memory. If this method is adopted, it becomes necessary to change the software for each mounting wiring pattern in the liquid crystal module including the liquid crystal display control device and the liquid crystal display panel.

Depending on how the display memory addresses are assigned, when the characters are displayed by scrolling in the horizontal direction, the display memory addresses for the left and right display characters adjacent to each display character position may become discontinuous. This makes it impossible to perform scroll control by hardware. For example, a drive terminal of a liquid crystal display control device equipped with a driver circuit having a display capacity of 4 digits and 2 lines can be connected to a drive electrode of a liquid crystal display panel by arranging wiring to form an 8 digit 1 line display liquid crystal display module. .
This state is the display mode shown in FIG. Usually, the display RAM of the liquid crystal display device has a storage area having a display capacity or more, and for example, the display RAM has a storage area capable of storing character codes of 8 digits and 2 lines. At this time, if the address of the display RAM is directly generated by the display address counter, the correspondence between the output address of the display address counter (displayed in hexadecimal number) and the font is as shown in FIG. In this state, when the characters are scrolled in the left horizontal direction by hardware as shown in FIG. 12C, the code of the character “F” designated by the output “10” of the display address counter is at the address “04”. It cannot be acquired and the hardware scroll cannot be performed.

It is an object of the present invention to provide a display control device capable of simplifying the wiring with the display device regardless of the mounting direction or mounting form of the dot matrix type display device. Another object of the present invention is to provide a display control device capable of recognizing a read address mapping different from a write address mapping for a display RAM without depending on an external address control and performing display control. Especially. Still another object of the present invention is to provide a display control circuit capable of continuously assigning addresses of a display memory to adjacent left and right display patterns. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

[1] First, the display control device according to the present invention controls the display of a pattern by supplying a drive signal to the drive electrodes of a dot matrix type display device in which a plurality of drive electrodes are arranged in parallel. A display RAM (4) rewritably storing a plurality of code data indicating a pattern to be displayed, and a pattern for generating display pattern data based on the code data read from the display RAM. An address generation procedure for accessing the display RAM is applied to a configuration including a data memory (5) and a drive circuit (10) that outputs a drive signal based on display pattern data generated from the pattern data memory. A non-volatile control memory (6, 60) for storing is provided. This control memory can be arranged on either the write address generation side or the read address generation side of the display RAM.

[2] Secondly, a display control device according to the present invention, which grasps the nonvolatile control memory from another viewpoint,
A drive signal is supplied to the drive electrodes of a dot matrix type display device in which a plurality of drive electrodes are arranged in parallel to control display of a pattern, and a plurality of code data indicating a pattern to be displayed is stored. First storage means (4)
And write address generation means (14, 15, 1) for writing code data to the first storage means.
6), and read address generation means (6, 12, 13) for reading code data from the first storage means,
Second storage means (5) for generating display pattern data based on the code data read from the first storage means, and a drive signal based on the display pattern data generated from the second storage means. Output drive circuit (1
0) and the read address generation means includes a third storage means (6) for storing a correspondence relationship between the write address mapping and the read address mapping for the first storage means, The read address is generated based on the information read from the third storage means.

[3] When the third storage means is arranged in the write address generation system, the write address generation means sets the correspondence relationship between the write address mapping and the read address mapping with respect to the first storage means. A third storage means (60) for storing is provided, and a write address is generated based on the information read from the third storage means.

[4] Third, in the display control device according to the present invention, which is obtained by grasping the third storage means from a different point of view, when the third storage means is arranged in the read address generation system, The write address generation means for the storage means includes a write address counter (14) that defines the write address order of the plurality of code data for the first storage means, and according to the write address order sequentially output from the write address counter. The read address generating means for generating the write address, the read address generating means for the first storing means stores the information for defining the read address order of the plurality of code data from the first storing means. (6) and read-out for sequentially reading the definition information of the read-out address order from the third storage means And a dress counter (12),
The read addresses are generated in an order according to the read address order definition information read from the third storage means.

[5] When the third storage means is arranged in the write address generation system from the same viewpoint as the above [4],
The read address generation means for the first storage means is a read address counter (1 which defines the read address order of the plurality of code data from the first storage means.
2), and is configured to generate a read address according to a read address sequence sequentially output from the read address counter, and the write address generation means for the first storage means is a plurality of write addresses for the first storage means. Storage means (60) for storing information that defines the write address order of the code data, and a write address counter for sequentially reading the write address order definition information from the third storage means. (14)
And is configured to generate the write addresses in an order according to the write address order definition information read from the third storage means.

[6] To increase the versatility of the display control device,
The third storage means (6, 60) may be constituted by an electrically writable or rewritable nonvolatile storage device.

[0015]

[Action]

[1] The control memory stores an address generation procedure for writing and accessing the display memory by an external CPU or the like, or an address generation procedure for sequentially reading the display memory for displaying. Therefore, the reading order of the plurality of code data read from the display memory is changed in accordance with the address generating procedure for reading and the reading order is changed according to the address generating procedure for writing. This is because the storage contents of the control memory are determined according to the arrangement of the drive electrodes of the display device, the arrangement of the drive signal output terminals, and the mounting direction of the display control device with respect to the display device. In addition, it is possible to change the mode of the wiring connecting the drive signal output terminals of the display control device as desired. This contributes to simplification of those wiring patterns. This further enables access to the display RAM for storing the code data without depending on the wiring pattern. Therefore, the code data to be displayed is displayed in the display RAM.
It is possible to eliminate the need to change the software for writing by an external device such as a CPU that supplies the writing instruction to the CPU, depending on the wiring mode. [2] The third storage means has a mapping of addresses to which the external CPU or the like writes and accesses the display memory,
The correspondence with the mapping of the read address for sequentially reading the display memory for displaying is stored. Therefore, the read order of the plurality of code data read from the display memory is changed according to the read address mapping with respect to the write address mapping. This means that the storage contents of the third storage means are determined according to the arrangement of the drive electrodes of the display device, the arrangement of the drive signal output terminals, and the mounting direction of the display control device with respect to the display device. It is allowed to change the mode of the wiring connecting the drive signal output terminal of the display control device to the drive electrode as desired. This contributes to simplification of those wiring patterns. This also means that the display R that stores the code data
It enables access to AM without depending on the above wiring pattern. Therefore, it is not necessary to change the software for writing by the external device such as the CPU which supplies the display RAM with the code data to be displayed and gives the writing instruction, depending on the wiring mode. [3] When the third storage means included in the read address generation means holds the information that defines the read address order of the code data, and the third storage means included in the write address generation means includes the write address of the code data. In any case where the information that defines the order is held, the wiring is formed by allowing the wiring mode for connecting the drive signal output terminal of the display control device to the drive electrode of the display device as desired in the same manner as described above. Contributing to simplification of the pattern, and changing the software for writing by an external device such as a CPU that supplies code data to be displayed to the display RAM and gives a writing instruction depending on the above wiring mode. Can be unnecessary. Furthermore, the read address order for the first storage means according to the information read from the third storage means can be determined without burdening the address assignment of the third storage means itself, which means that the horizontal hardware As in the case of the wear scroll, the addresses of the first storage means can be continuously assigned to the adjacent left and right display patterns on the display device, and the horizontal hardware scroll can be easily realized.

[0016]

1 is a block diagram of a liquid crystal display system according to an embodiment of the present invention. This system is not particularly limited, but includes a liquid crystal display control device 2, a CPU 1 (central processing unit) that controls the operation of the liquid crystal display control device 2, and a liquid crystal display panel (LCD).
It is also referred to as the panel) 3. The liquid crystal display control device 2 is
A display RAM 4 (random access memory) that stores the character code of the character that is actually displayed on the liquid crystal screen, and a character generator ROM 5 (read-out memory) that develops a dot matrix character font pattern from the specified character code. (Only memory), and a display control ROM 6 for storing order information for reading the display RAM 4 when performing liquid crystal display.

Although not particularly limited, the liquid crystal display panel 3 is of a dot matrix type, and the common electrodes as scanning electrodes and the segment electrodes as signal electrodes are X and Y.
Liquid crystal display elements for one dot are formed at the respective intersecting positions. When the common electrodes are sequentially driven, lighting or non-lighting of the display element corresponding to the driven common electrode is determined by the display signal given to the segment electrode. According to the present embodiment, the liquid crystal display panel 3 has a maximum of 8 digits 4 although not particularly limited.
It has a display area where characters can be displayed in lines, and the number of dots (the number of display elements) per displayed character is horizontal × vertical = 5 × 8 dots. According to this, the liquid crystal display panel 3 has 32 common electrodes (C1 to C32) and 40 segment electrodes (S1 to S40).

The CPU 1 writes a character code of a character to be displayed in the display RAM 4 to display an arbitrary character at an arbitrary position. Writing to the display RAM 4 is done by the CPU
It is performed for the address designated by the address counter 14. The CPU 1 can preset an arbitrary initial address value to the CPU address counter 14,
Every time a write instruction is given to the display RAM 4, the CPU address counter 14 is incremented in synchronization with it to internally generate a necessary address. The output of the CPU address counter 14 is supplied to the CPU address generation circuit 16, whereby the physical write address of the display RAM 4 is generated, and the display RAM is supplied via the selection circuit 17.
4 is supplied. The display character code as the write data at this time is sent to the CPU via the CPU interface 15.
It is given from 1 and so on. CP is used to exchange data between the CPU 1 and the CPU address counter 14 and the display RAM 4.
This is done via the U interface 15.

In the present embodiment, the display control ROM 6 has information for generating a read address of the display RAM 4, and this information is read by using the output of the display address counter 12 as an access address. The display address counter 12 performs, for example, a sequential increment operation in synchronization with the display operation and outputs the value. The data read from the display control ROM 6 in accordance with the liquid crystal display position is supplied to the display address generation circuit 13, whereby the display RAM 4
A physical read address is generated and is supplied to the display RAM 4 via the selection circuit 17, whereby the display character code is read from the display RAM 4.
Although not particularly limited, according to the present embodiment, the display character code is 8 bits.

Here, the character generator ROM
5 is alphanumeric, alphabet, katakana, hiragana,
And, the font pattern data of each character such as kanji is stored. Although not particularly limited, a character code is assigned to each character. Although not particularly limited, each character is composed of 5 dots horizontally and 8 dots vertically as shown in FIG. For example, it has a standard orientation as shown in FIG.

The character generator ROM 5 stores the font data of one character designated by the character code in units of 5 dots (in units of 5 bits according to this embodiment).
It is made readable by one read operation. That is, the character generator ROM 5 displays the display R
The character code read from the AM4 is used as the upper 8 bits of the address, and the output of the line address counter 20 is used as the lower 3 bits of the address for read access.
The upper 8-bit character code of the address is regarded as a signal for designating a character, and the line address counter 20
The 3-bit output is regarded as a signal for sequentially designating the vertical 8 lines of one character font designated by the character code, one line at a time.

Character font pattern data read from the character generator ROM 5 (reading of such character font pattern data is also referred to as expansion of character font pattern) is converted into serial data by the parallel-serial converter 7 and shifted. Register 8 (4
When the data for one line (one scanning line or the common electrode of the liquid crystal display panel 3) is completely stored in the shift register 8, the latch circuit 9 latches the data. And supplies it to the segment liquid crystal driver 10. The segment liquid crystal driver 10 supplies a voltage of a selection (lighting) or a non-selection (non-lighting) level of each display element, that is, each pixel of the liquid crystal display panel to the latch circuit 9.
And the segment electrodes of the liquid crystal display panel 3 are driven. The common electrode of each line is cyclically driven by the common liquid crystal driver 18 sequentially and in a time division manner. For example, the common electrodes C1 to C32 are sequentially driven.

In FIG. 1, reference numeral 21 is a timing generation circuit, which generates various internal timing signals in synchronization with a clock signal CLK supplied from the outside. In the figure, φ1 to φ3 are representatively shown. Although not particularly limited, the display operation is a CP via the CPU interface 15.
It is started by the instruction signal φ0 from U1, and in synchronization with this, the timing signal φ1 is clock-changed once in every five cycles of the clock signal as shown in FIG. Timing signal φ2 is line address counter 2
The increment timing of 0 is specified. The timing signal φ3 is the clock signal CLK as shown in FIG.
In the first half of the five-cycle period, the level is changed to the high level, and in the latter half, the level is changed to the low level to change the clock. The selection circuit 17 which receives the timing signal φ3 receives CP during the high level period.
The output of the U address generation circuit 16 is selected, and the output of the display address generation circuit 13 is selected and supplied to the display RAM 4 during the low level period. In other words, display RAM
The table access by the CPU 1 and the read access for the display operation with respect to 4 are enabled in a time division manner in synchronization with the timing signal φ3. Although not shown in particular, the operation timing of the common liquid crystal driver 18 and the segment liquid crystal driver 10 is synchronized with the operation of the display address counter 12 and the line address counter 20 by a timing signal (not shown) output from the timing generation circuit 21, and the common electrode The sequential drive and the drive timing of the segment electrodes are set so that the data sequentially read from the character generator ROM 5 can be displayed at the position where it should be displayed.

FIG. 2 shows a detailed example of the display control ROM 6. This is an example in which a character font of 5 × 8 dots is displayed in 8 digits in the horizontal direction and 4 lines in the vertical direction. According to this example, the display control ROM 6 is "00".
~ "07", "10" ~ "17", "20" ~ "2"
A total of 32 types of information, 7 "and" 30 "to" 37 ", are stored. These information are not particularly limited, but are values displayed in hexadecimal for generating the address of the display RAM 4. , For example, "00" means liquid crystal display panel 3
, Which indicates the storage address of the character code to be displayed in the first digit from the left of the first line when viewed from the front, "
02 "is information for indicating the storage address of the character code to be displayed in the second digit from the left of the first line when the liquid crystal display panel 3 is viewed from the front, and" 12 "is the front surface of the liquid crystal display panel 3. , "3 for indicating the storage address of the character code to be displayed in the second digit from the left of the second line when viewed from
7 "is information for indicating the storage address of the character code to be displayed at the eighth digit from the left of the fourth line when the liquid crystal display panel 3 is viewed from the front, and the other information is the same. Such information is stored in an address on the display ROM 6 which is defined by a lower address and a higher address represented by hexadecimal numbers. According to this embodiment, the information stored by the display control ROM 6 is a physical address of the display RAM 4. The display address generation circuit 13 which receives the output of the display control ROM 6 instead of the information itself converts the input into the physical address and supplies it to the display RAM 4.
It is also possible for M6 to directly hold the physical address of the display RAM 4. In that case, although it is expected that the number of storage elements of the display control ROM 6 will increase, the display address generation circuit 13 is unnecessary. As is clear from the above description, the information held by the display control ROM 6 is the display RA.
It has significance as information that defines an address generation procedure for reading and accessing M4, and also as information that indicates the correspondence between the mapping of the write address and the mapping of the read address on the display RAM 4.

The display address counter 12 displays "000" H (hexadecimal) to "007" H when displaying the first line.
It is sequentially incremented to (hexadecimal) and the display control ROM 6 is read. Similarly, when displaying the second line, "010" H (hexadecimal) to "017" H (hexadecimal)
Up to "020" H (16
Hex) to "027" H (hexadecimal), or "030" H (hexadecimal) to "037" H when displaying the 4th line
It is sequentially incremented to (hexadecimal) and the display control ROM 6 is read.

The operation of the display address counter 12 will be described in more detail together with the operation of the line address counter 20. The liquid crystal display panel 3 is sequentially driven row by row. In other words,
The common liquid crystal driver 18 sequentially drives the common electrodes from one to the other. Therefore, the common electrodes for 8 lines are sequentially driven during the period of displaying characters for one line on the liquid crystal display panel 3, and the character code required for the driving period of each line is It is the same for each drive period. In other words, the display RA
From M4, the same character code must be output for each line eight times during the period of the eight lines. In order to deal with this, the display address counter 12 has the lower address "0" to "" of the display control ROM 6 shown in FIG.
It is operated so that the upper address is incremented every time the 7 "increment operation is repeated eight times. For example, 8
When the display address counter 12 is constituted by a binary counter of bits, the least significant bit to the third bit of the counter are used as the lower 3 bits for accessing the display control ROM 6, and the 7th of the binary counter is used.
The bit and the eighth bit may be adopted as the upper 2 bits for accessing the display control ROM 6. According to this example, the line address counter 20 can be configured by a 3-bit binary counter that is sequentially incremented by the timing signal φ2 that is clock-changed every 40 cycles of the clock signal CLK.

The write address formed via the CPU address counter 14 is uniquely defined by the increment operation of the counter 14,
A value that is sequentially incremented with a preset value from 1 as an initial value is one in which various values included in the information described as being stored in the display control ROM 6 of FIG. 2 are changed from a smaller value to a larger value. And Therefore, the display mode of the font corresponding to the arrangement of the character codes written in the display RAM 4 by the CPU 1 is the display control ROM 6
It will be understood that this is determined by the information in. The mode of FIG. 2 is a case where the font display mode is the same for the character code array written in the display RAM 4 by the CPU 1, and the data stored in the display control ROM 6 at this time is referred to as a basic pattern.

FIG. 3 shows a case where the address data in the display control ROM 6 shown in FIG. 2 is horizontally reversed within each row, and further vertically reversed in units of rows, and a display mode corresponding thereto.
FIG. 4 shows a case where the address data in the display control ROM 6 of FIG. 2 is horizontally reversed in each row, and a display mode corresponding to the case.

FIG. 10 is a side view showing two types of mounting states of the liquid crystal display control device 2 on the liquid crystal display panel 3. In the same figure, (A) is the rear mounting, and (B) is the front mounting. The liquid crystal display panel 3 includes two glass substrates 30,
A liquid crystal 32 is formed between 31 and a circuit board 34 on which the liquid crystal display control device 2 is mounted is provided on the opposite side of the glass substrate 31 via a spacer 33 or the like.
The liquid crystal display control device 2 shown in the figure is not particularly limited, but it is a QFP (Quad Flat Packg).
e), PLCC (Plastic Laeded Ch)
ip Carrier) and the like. Terminals (not shown) used as segment electrodes or common electrodes on the edge of the glass substrate 31.
And the wiring pattern of the circuit board 34 (not shown)
Connected with. The display surface of the liquid crystal display panel 3 is on the glass substrate 30 side. The mounting form of the liquid crystal display control device 2 is not limited to the mounting on the circuit board 34 as described above, and a wiring pattern is formed on the back surface of the glass substrate 31 and, for example, T
It is also possible to directly mount the liquid crystal display control device 2 sealed in the CP (Tape Carrier Package) format.

FIG. 5 shows a wiring example when the liquid crystal display control device 2 employing the display control ROM 6 for outputting the basic display pattern of FIG. 2 is mounted on the liquid crystal display panel 3. The mounting form of FIG. 5 is the rear mounting shown in FIG. 10A, in which the liquid crystal display control device 2 is arranged on the rear surface side of the circuit board 34 in the liquid crystal display panel 3, and the liquid crystal display control device is arranged above the display screen. The output of the second segment liquid crystal driver 10 is connected. Further, the output of the common liquid crystal driver 16 of the liquid crystal display control device 2 is connected to the right side from the front of the display screen. That is, the segment electrodes S1 to S40 are provided on the upper edge side of the liquid crystal display panel 3 from the front side as the base point, and the common electrodes C1 to C32 are provided on the right edge side from the front side as the base point from the upper side. ing. The liquid crystal display control device 2 outputs 1 to the output of the segment liquid crystal driver 10.
Segment terminals Seg1 to Seg connected in a one-to-one correspondence
40 and common terminals Com1 to Com32 which are coupled to the output of the common liquid crystal driver 18 in a one-to-one correspondence.
As shown in FIG. 5, the segment terminals Seg1 to Se
g40 is sequentially coupled to the segment electrodes S1 to S40, and the common terminals Com1 to Com32 are sequentially coupled to the common electrodes C1 to C32.

If a display control ROM 6 having the stored contents shown in FIG. 3 is adopted when a display corresponding to the display pattern shown in FIG. 3 is performed, the display shown in FIG. You can get the pattern. On the other hand, the display control R for outputting the basic display pattern of FIG.
When using the liquid crystal display control device 2 employing the OM6, complicated wiring as shown in FIG. 6 described below must be performed. This state is equivalent to the case where a liquid crystal display control device having no display control ROM 6 is used as in the conventional case.

FIG. 6 shows an example of connection of mounting type for performing display corresponding to the display pattern of FIG. 3 by using the liquid crystal display control device 2 adopting the display control ROM 6 for outputting the basic display pattern of FIG. Be done. This example is also mounted on the back surface, but the liquid crystal display control device 2 is mounted so that the top, bottom, left, and right of FIG. 5 are interchanged. That is, the common terminal is Com
1 to Com8 are wired in such a manner that they are coupled to the common electrodes C32 to C25, and the segment terminals are Seg.
1 to Seg5 are wired in such a relationship that they are coupled to the segment electrodes S36 to S40.

When a display corresponding to the display pattern as shown in FIG. 4 is performed and the display control ROM 6 having the stored contents shown in FIG. 4 is adopted, the display shown in FIG. You can get the pattern. On the other hand, the display control R for outputting the basic display pattern of FIG.
When the liquid crystal display control device 2 adopting the OM6 is used, relatively complicated wiring as shown in FIG. 7 described below must be performed. This state is the same as the conventional display control ROM.
This is equivalent to a case where a liquid crystal display control device without 6 is used to obtain a display mode as shown in FIG.

FIG. 7 shows an example of connection of mounting type for performing display corresponding to the display pattern of FIG. 4 by using the liquid crystal display control device 2 which employs the display control ROM 6 for outputting the basic display pattern of FIG. Be done. This example is front mounted,
Common electrodes C1 to C32 and common terminals Com1 to Com
The connection with 32 is the same as in the case of FIG. 5, but the segment terminals Seg1 to Seg5 are the segment electrodes S36 to S.
Wired in such a relationship as to be coupled to 40.

FIG. 9C shows a pattern obtained by reversing the direction of the character generator ROM 5 vertically and horizontally with respect to the basic pattern shown in FIG. 9B, and in FIG. 9D, horizontally reversing the basic pattern. The resulting pattern is shown. When the information in the display control ROM 6 of the liquid crystal display control device 2 is in the form of FIG. 2 and the direction of the font pattern held by the character generator ROM 5 has the direction shown in FIG. The display mode of FIG. 3 can be obtained by the simple wiring mode of FIG. 5 without using a complicated wiring mode. Further, when the information in the display control ROM 6 of the liquid crystal display control device 2 is in the mode of FIG.
If the direction of the font pattern held by the character generator ROM 5 has the direction shown in FIG. 9D, the simple wiring form of FIG. 5 can be used without using the relatively complicated wiring mode of FIG. Thus, the display mode of FIG. 4 can be obtained. As is clear from the example of FIG. 9, the contents stored in the display control ROM 6 and the character generator R
By properly combining the font direction of OM5, it is possible to further simplify the wiring mode.

Next, an example in which a horizontal hardware scroll is realized by using the display control ROM 6 will be described with reference to FIGS. 12 and 13. For example, a drive terminal of a liquid crystal display control device having a driver circuit having a display capacity of 4 digits and 2 lines is connected to a drive electrode of a liquid crystal display panel by arranging wiring to use an 8 digit and 1 row display liquid crystal display module. I shall. This state is the display mode shown in FIG. Display RAM of liquid crystal display device
Has a storage area having a display capacity or higher, and for example, the display RAM has a storage area capable of storing character codes of 8 digits and 2 lines. At this time, (D) in FIG. 13 is provided between the display address generation circuit and the display address counter.
A display control ROM 61 having an information storage area for 8 columns and 2 lines as shown in FIG. The information stored in the display control ROM 61 is information represented by a hexadecimal number for designating the address of the display RAM. The display address counter for accessing this is such that when the font has the same 5 × 8 dot configuration as described above, the upper address is incremented each time the initial value is incremented four times. Further, in consideration of hardware scrolling, the initial value of the lower address can be preset. Therefore, in the normal display without horizontal scrolling, the display control ROM 61 outputs the lower address "0" H to "3" H according to the output of the display address counter.
Range (“00” H to “03” H, “10” H to 13 ”
Accessed by (H), 8-line font "AH" is displayed in one line as shown in FIG. Display control ROM 61 for horizontal scrolling of one digit
Has a lower address in the range of "1" H to "4" H ("0"
1 "H to" 04 "H," 11 "H to" 14 "H), the 8-digit font" BI "is displayed in one line as shown in FIG. 13 (F). . As is clear from (F) in the figure, the addresses of the display RAM in the fourth and fifth digits are continuous. This enables hardware scrolling, which was impossible in FIG. 12C.

FIG. 8 shows another embodiment of the present invention.
The above embodiment is an example in which the display control ROM 6 is inserted between the display address counter 12 and the display address generation circuit 13 to make the correspondence between the display address of the display RAM 4 and the CPU address variable. The correspondence between these two addresses can be realized even by converting the CPU address. The embodiment shown in FIG. 8 focuses on this point.
The display control ROM 60 is read from U1 with the CPU address initially set in the CPU address counter 14, and the CPU address generation circuit 16 generates an address for accessing the display RAM 4 from the read data. In the display, the display RAM 4 is sequentially read by the addresses generated by the display address counter 12 and the display address generation circuit 13. Since other configurations are the same as those described with reference to FIG. 1, circuit blocks having the same function are designated by the same reference numerals, and detailed description thereof will be omitted. The information stored in the display control ROM 60 is positioned as information indicating an address generation procedure for writing and accessing the display RAM 4, and information indicating a correspondence relationship between a write address mapping and a read address mapping on the display RAM 4. When the display mode as shown in FIG. 8 is obtained, the information stored in the display control ROM 60 is the same as that in the case of FIG. 2, and can be obtained by the wiring of FIG. 3 and 4
The contents of the display control ROM 6 shown in FIG.
By applying 0, it is possible to obtain the same display mode as when the display control ROM 6 is used.

The display control ROMs 6, 60, 61 may be constituted by a mask ROM, an ultraviolet erasable writable ROM such as EPROM, or an electrically rewritable ROM such as EEPROM or flash memory. The writing operation may be performed by using a writing device such as an EPROM writer, or an electrically rewritable one may be controlled by CPU on the system.

According to each of the above-mentioned embodiments, there are the following operational effects. [1] As shown in FIGS. 1 and 2, the display control R
The OM 6 is a display RA for performing mapping and address mapping for the CPU 1 to write and access the display RAM 4.
The correspondence with the mapping of the read address for sequentially reading M4 is stored. In other words, the display control ROM
6 holds information defining the read address order of the character code. Therefore, the reading order of the plurality of character codes read from the display RAM 4 is changed according to the read address mapping with respect to the write address mapping. Due to this, the common electrode C1 of the liquid crystal display panel 3
To C32 and the arrangement of the segment electrodes S1 to S40, the arrangement of the common terminals Com1 to Com32 and the segment terminals Seg1 to Seg40 of the liquid crystal display control device 2, and the mounting form of the liquid crystal display control device 2 integrated into the liquid crystal display panel 3. Accordingly, by determining the contents stored in the display control ROM 6, the common electrodes C1 to C32 and the segment electrodes S1 to S40 of the liquid crystal display panel 3,
Common terminals Com1 to Com32 of the liquid crystal display control device 2
It is possible to change the mode of the wiring that connects the segment terminals Seg1 to Seg40, as desired. In other words, since the memory in which the correspondence relationship between the address for the CPU to access the display memory and the address for sequentially reading the display memory for displaying is stored is used, the configuration in the display control device can be changed. In addition, the wiring between the display control device and the display device can be simplified.

[2] As described with reference to FIG. 8, C
The display control ROM 60 that stores the correspondence between the mapping of addresses for the PU1 to write access to the display RAM 4 and the mapping of the read addresses for sequentially reading the display RAM 4 for displaying, in other words, the order of writing addresses of character codes is defined. Similarly, when the display control ROM 6 holding the information to be stored is adopted, the common electrodes C1 to C32 and the segment electrodes S1 to S40 of the liquid crystal display panel 3 are also selected according to the stored contents of the display control ROM 60.
And the common terminals Com1 to Com of the liquid crystal display control device 2.
The mode of the wiring connecting the 32 and the segment terminals Seg1 to Seg40 can be changed as desired.

[3] Due to the above [1] and [2], an extremely simple wiring pattern as shown in FIG. 5 can be adopted regardless of the arrangement of the electrodes and terminals and the mounting form of the liquid crystal display control device. Like

[4] The above [1] and [2] enable access to the display RAM for storing code data without depending on the wiring pattern. Therefore, it is not necessary to change the software for writing by the external device such as the CPU which supplies the display RAM with the code data to be displayed and gives the writing instruction, depending on the wiring mode. That is, in order to simplify the wiring between the liquid crystal display control device 2 and the liquid crystal display panel 3, it is not necessary to change the software of the CPU 1 that controls the writing of the character code even when the mounting wiring pattern is replaced. Like In other words, the access control software for the display RAM 4 storing the character code does not have to depend on the change of the wiring pattern in the liquid crystal module.

[5] The control ROMs 6, 60 whose stored contents are changed also in the change of the display mode as shown in FIGS. 3 and 4.
It can be easily realized by properly using.

[6] Character generator ROM in which the font direction is changed as described with reference to FIG.
By using 5 in combination, it is possible to further increase the degree of freedom of the display mode and the wiring pattern.

[7] As described with reference to FIG.
Display R according to the information read from the display control ROM 61
The read address sequence for AM4 is the display control ROM
61 It can be determined without depending on the address allocation of itself, and this is to continuously allocate the addresses of the display RAM 4 to the adjacent left and right display patterns on the liquid crystal display panel 3 as in the case of horizontal hardware scrolling. And enables horizontal hardware scrolling easily.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, the display address counter 12 is not limited to be incremented according to the display position, and may be decremented. Display control R
The data in the OM is not limited to the configuration for storing the information for generating the address for reading the display RAM as in the above embodiment, but may store the direct address information for reading the display RAM. Further, the reading of the display control ROM is not limited to the above-mentioned one using the display address counter, and it should be in a chain form by a pointer that stores the address of the display control ROM itself to be read next in the display control ROM. Display control R
It is possible to control the reading order of the OM.

In the above description, the case where the invention made by the present inventor is mainly applied to the liquid crystal display technology which is the field of application which is the background of the invention has been described, but the present invention is not limited thereto and plasma is used. The present invention can be applied to those that drive and control various display devices such as a display.

[0049]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by adopting a control memory that stores an address generation procedure for an external CPU or the like to write and access the display memory, or an address generation procedure for sequentially reading the display memory for displaying, , External CPU etc. is the first such as display memory
Since the third storage means for storing the correspondence between the mapping of the address for writing access to the storage means and the mapping of the read address for sequentially reading the first storage means for displaying is employed, the display device Of the display control device to the drive electrodes of the display device by determining the stored contents of the control memory according to the arrangement of the drive electrodes, the arrangement of the drive signal output terminals, and the mounting direction of the display control device with respect to the display device. The mode of wiring for connecting the signal output terminals can be changed as desired. Therefore, the wiring patterns can be simplified. Further, it is possible to access the display RAM for storing the code data or the first storage means without depending on the wiring pattern. Therefore, it is not necessary to change the software for writing by the external device such as the CPU which supplies the display RAM with the code data to be displayed and gives the writing instruction, depending on the wiring mode. Also,
In the case of horizontal hardware scrolling, the read address order for the first storage means according to the information read from the third storage means can be determined without burdening the address allocation of the third storage means itself. As described above, the addresses of the first storage means can be continuously assigned to the adjacent left and right display patterns on the display device, and horizontal hardware scrolling can be easily realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a liquid crystal display system according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a detailed example of a display control ROM.

FIG. 3 is an explanatory diagram showing a case where the address data in the display control ROM of FIG. 2 is horizontally inverted in each row and vertically inverted row by row, and a display mode corresponding thereto.

FIG. 4 is an explanatory diagram showing a case where address data in the display control ROM of FIG. 2 is horizontally reversed in each row and a display mode corresponding to the case.

FIG. 5 is a display control R for outputting the basic display pattern of FIG.
FIG. 11 is a plan view showing an example of connection when a liquid crystal display control device adopting OM is mounted on a liquid crystal display panel.

FIG. 6 is a display control R for outputting the basic display pattern of FIG.
It is explanatory drawing which shows the example of connection of the mounting form for performing the display corresponding to the display pattern of FIG. 3 using the liquid crystal display control device which adopted OM.

FIG. 7 is a display control R for outputting the basic display pattern of FIG.
It is explanatory drawing which shows the example of connection of the mounting form for performing the display corresponding to the display pattern of FIG. 4 using the liquid crystal display control device which adopted OM.

FIG. 8 is a block diagram of a liquid crystal display system according to another embodiment of the present invention.

FIG. 9 is a pattern explanatory diagram for explaining a dot configuration and a direction of a font.

FIG. 10 is a side view showing two mounting states of the liquid crystal display control device on the liquid crystal display panel.

FIG. 11 is an explanatory diagram of an example waveform showing a timing signal output from the timing generation circuit.

FIG. 12 is an explanatory diagram showing that hardware scroll cannot be realized when the display control ROM is not used.

FIG. 13 is an explanatory diagram of a case where hardware scroll is realized by using a display control ROM.

[Explanation of symbols]

 1 CPU 2 Liquid crystal display control device 3 Liquid crystal display panel 4 Display RAM 5 Character generator ROM 6 Display control ROM 60 Display control ROM 61 Display control ROM 10 Segment liquid crystal driver 12 Display address counter 13 Display address generation circuit 14 CPU address counter 16 CPU address Generation circuit 18 Common liquid crystal driver 20 Line address counter C1 to C32 Common electrode S1 to S40 Segment electrode Com1 to Com32 Common terminal Seg1 to Seg40 Segment terminal

Claims (7)

[Claims] 1. A display device of a dot matrix type in which a plurality of drive electrodes are arranged in parallel to each other for supplying a drive signal to the drive electrodes to control display of a pattern, and a plurality of patterns for indicating a pattern to be displayed. The rewritable display RAM, the pattern data memory that generates display pattern data based on the code data read from the display RAM, and the display pattern data generated from the pattern data memory. A display control device comprising: a drive circuit that outputs a drive signal based on the above; and a non-volatile control memory that stores an address generation procedure for accessing the display RAM. 2. A dot matrix type display device in which a plurality of drive electrodes are arranged in parallel to each other, wherein a drive signal is supplied to the drive electrodes to control display of a pattern, and a plurality of patterns are used to indicate a pattern to be displayed. First storing means for storing the code data, write address generating means for writing the code data to the first storing means, and read code data from the first storing means. Read address generating means, second storage means for generating display pattern data based on the code data read from the first storage means, and display pattern data generated from the second storage means And a read circuit for outputting a drive signal, wherein the read address generating means is configured to map a write address to the first storage means and read address. A display control device, comprising: a third storage means for storing a correspondence relationship with a mapping of a memory, and generating a read address based on information read from the third storage means. 3. A dot matrix type display device in which a plurality of drive electrodes are arranged in parallel to each other for supplying a drive signal to the drive electrodes to control display of a pattern, and a plurality of patterns for indicating a pattern to be displayed. First storing means for storing the code data, write address generating means for writing the code data to the first storing means, and read code data from the first storing means. Read address generating means, second storage means for generating display pattern data based on the code data read from the first storage means, and display pattern data generated from the second storage means A write circuit for outputting a drive signal, wherein the write address generation means is a write address mapping and read address mapping for the first storage means. A display control device comprising: a third storage means for storing a correspondence relationship with a mapping of a memory, and generating a write address based on information read from the third storage means. 4. A dot-matrix display device having a plurality of drive electrodes arranged in parallel to each other for supplying a drive signal to the drive electrodes to control display of a pattern, and a plurality of patterns for indicating a pattern to be displayed. First storing means for storing the code data, write address generating means for writing the code data to the first storing means, and read code data from the first storing means. Read address generating means, second storage means for generating display pattern data based on the code data read from the first storage means, and display pattern data generated from the second storage means And a drive circuit for outputting a drive signal, wherein the write address generation means defines a write address order of a plurality of code data to the first storage means. And a write address counter for generating write addresses according to a write address sequence sequentially output from the write address counter, wherein the read address generation means is a plurality of code data from the first storage means. And a read address counter for sequentially reading the read address order definition information from the third storage means. A display controller, wherein the read addresses are generated in an order according to the read address order definition information read from the storage means. 5. A dot matrix type display device in which a plurality of drive electrodes are arranged in parallel, wherein a drive signal is supplied to the drive electrodes to control display of a pattern, and a plurality of patterns indicating a pattern to be displayed are provided. First storing means for storing the code data, write address generating means for writing the code data to the first storing means, and read code data from the first storing means. Read address generating means, second storage means for generating display pattern data based on the code data read from the first storage means, and display pattern data generated from the second storage means And a drive circuit for outputting a drive signal, wherein the read address generation means defines a read address order of the plurality of code data from the first storage means. A read address counter for generating a read address in accordance with a read address sequence sequentially output from the read address counter, wherein the write address generation means includes a plurality of code data for the first storage means. The third storage means for storing information defining the write address order, and the write address counter for sequentially reading the write address order definition information from the third storage means are provided. The display control device is characterized in that the write addresses are generated in an order in accordance with the write address order definition information read from the storage means. 6. The display control device according to claim 1, wherein the third storage means is an electrically writable or rewritable nonvolatile storage device. 7. The display control device according to claim 1, wherein the display control device is formed on a single semiconductor substrate.