JPH071491B2 - Virtual computer system - Google Patents

Description

[Detailed Description of the Invention] [Detailed Description of the Invention] The present invention relates to a virtual computer system, and more particularly to a virtual computer system suitable for deleting an overhead related to a main memory access associated with address translation.

[Background of the Invention]

The virtual computer system operates by operating a plurality of operating systems on a single real computer to control as if there were a plurality of computer systems. A virtual computer realized on a real computer system is distinguished from a real computer by a virtual computer (VM: Virtu
al machine). The program for controlling this VM is called a virtual machine monitor (VMM: VM Monitor). VMM allocates hardware resources of real computer system to each VM
A virtual computer system is realized by temporally and spatially allocating partitions.

The hardware resources allocated to each VM include an instruction processing device, main memory, input / output device, etc. Conventionally, the instruction processing device is a time-division system, and the main memory is space or space using a virtual memory system of a real computer. In the time-sharing method, input / output devices are dedicated (space-divided) or shared (time-divided) for each VM to allocate VMs of actual hardware resources.
Functions of the VMM include allocation of instruction processing units and input / output units to VMs, management of main memory of real and virtual computers, simulation of instructions and interrupts that could not be directly executed by VMs. Explaining the points related to the management of the main memory, the VMM itself allocates the virtual memory address space of the real computer as the real memory address space of the VM by using the virtual memory method. Two-stage address conversion is required to convert the address. This two-stage address translation is first done by VM
In the above, the address translation is performed using the address translation table to obtain the real address in the VM, that is, the virtual address in the VMM, and then the real address is obtained using the address translation table in the real computer, that is, the VMM. By the way, in order to access the address translation table in the VM, the address translation table itself in the VM exists in the virtual address space of the VMM, and the conventional real computer system has only one-step address translation function. This two-stage address translation must be performed by the VMM, which causes a complicated and large address translation overhead.
In order to simplify this two-step address translation and enable the use of address translation by a real computer, VMM uses VM
A table is created to directly convert the virtual address in the VMM to the real address in the VMM so that the address conversion from the virtual address in the VM to the real address of the real computer can be done in one step. The address translation table created by this operation of VMM is called a shadow table.

The major overhead in the virtual machine system is shadowing, which is a function of the above VMM.
There is overhead associated with table management, that is, address translation, and overhead due to VMM simulation of instructions and interrupts that cannot be directly executed by VM.

Traditionally, VMs have been the only way to eliminate this kind of overhead.
A method that eliminates the overhead associated with instruction and interrupt simulation by allowing VMs to execute directly without interrupting the VMM by firmwareizing VM instructions that frequently generate M simulations.
In addition, some areas of real main memory are fixedly allocated to VMs,
There is a method in which the virtual real memory and the real memory of the real computer directly correspond to each other in a fixed relationship to eliminate the need for the shadow table.

JP-A-57-40584 discloses that the overhead related to the main memory access associated with the address translation is deleted.
By allocating a real main memory area for each, holding the start address and end address of that area, and adding the above start address to the virtual real memory address of the VM when the VM accesses the main memory. A method is disclosed in which the shadow table is not required by obtaining the real main memory address, the overhead associated with the address conversion is deleted, and the real memory is protected by comparing with the end address. However, if the command processor is running
Generally, it is not possible to guarantee that the VM and the VM running on the I / O processor match. Japanese Patent Publication No. 57-40584 does not disclose how to perform address conversion in such an input / output processing operation.
Since the VMM is forced to do so, in the case of input / output processing, the overhead of main memory access due to address translation still occurs.

[Object of the Invention]

An object of the present invention is to provide a method of eliminating the overhead related to main memory access associated with address translation in a virtual computer system including I / O processing.

[Outline of Invention]

The present invention divides the real main memory into a plurality of areas, and allocates each of the divided areas to each of the plurality of operating systems as a virtual real memory of the operating system (VM). In a virtual computer system in which the plurality of operating systems are respectively operated by an instruction processing device and an input / output processing device including a plurality of sub-channels, the instruction processing device is assigned to the operating system operating on the instruction processing device. Means for setting a start address and an end address of the real main memory area, and calculating (adding an address constant) the start address of the real main memory area set to the virtual real memory address issued by the instruction processing device. Means, the calculated address and the end address of the set actual main storage area In addition to providing a means for comparing, the input / output processing device is also provided with the start address and end address of the real main storage area allocated to the operating system using the subchannels for each of the subchannels. Means for setting, means for calculating (adding an address constant) the start address of the set real main storage area of the sub-channel to the virtual real storage address issued by the sub-channel, the calculated address and the sub-address And means for comparing the end address of the set actual main storage area of the channel. This allows the VM
It is possible to perform address translation on the input / output processor side independently of the VM operation in the instruction processor without the intervention of M, and the input / output processing of the main memory access overhead associated with address translation in the virtual computer system is performed. It can be deleted including. In addition, if a subchannel is dedicated to a particular operating system, that operating system
Holds system identification information
When the system accesses a subchannel, the instruction processor causes the operating system identification information to be compared with the retained identification information.
As a result, in addition to the protection of the main memory, it is possible to protect the sub-channel from being unnecessarily accessed by another VM.

Example of Invention

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows the configuration of the real computer system in the virtual computer system. In the figure, 1 is a main storage device, 2 is a storage control device, 3 is an instruction processing device, 4 is an input / output processing device, and 5 is an input / output device group. The number of each of the processing devices 3 and 4 may be one or may be more than one, but in the present embodiment,
Each case is shown as one. The address translation mechanism related to the virtual memory control computer exists in the instruction processing device 3.
The storage control device 2 controls the access of the instruction processing device 3 and the input / output processing device 4 to the main storage device 1, and is between the instruction processing device 3 and the input / output device 4 to execute and input / output the input / output instructions. Controls the interface related to the interrupt.

FIG. 3 shows a case where a VM monitor (VMM) dispatches a VM to a real computer and the dispatched VM operates on the real computer. VMM issues a VM dispatch instruction when dispatching a VM to a real computer, but before issuing this instruction, dispatches to the VM state description block on the main memory that is the operand of the VM dispatch instruction.
Set the information about VM execution. This information includes
It is necessary to restart the processing of VM, at least like the conventional VM system such as processing status word (PSW) including the first instruction address to be executed by the dispatching VM, general-purpose register, floating point register, control register, prefix register, etc. In addition to the following information, the identification information of the VM added by the present invention and the information about the real main storage area allocated to this VM are included. The information about the real main memory area includes the start address and end address of the real main memory allocated to the VM to be dispatched, and these pieces of information are set with the values related to the area previously allocated by the VM monitor. .

When a VM dispatch instruction is issued, the instruction processing unit
The above information in the VM state description block is fetched into a predetermined register inside the processing device, and the VM mode is entered to execute the VM instruction processing. The VM instruction execution process is interrupted by any of the following. One is when the VM itself encounters an instruction or situation that cannot be directly executed, at which time control is transferred to the instruction following the VM dispatch instruction, simulation is performed by the VM monitor, and then the VM dispatch instruction is issued again. It The other is when an interrupt that cannot be directly processed by the VM is issued while the VM is running, control is passed to the interrupt processing routine of the VM monitor, and the interrupt processing is performed by the VM monitor. In any of the above cases, before the control is passed to the VM monitor, all the information necessary for restarting the processing of the VM being executed by the instruction processing device 3 may be saved in the above-mentioned VM state description block to prepare for the restart. Done. The VM mode is released when control is passed to the VM monitor.

FIG. 1 shows the relationship between the area division of the real main memory, the area allocation to the VM, and the main memory area information in the VM state description block in the virtual computer system of the present invention. The VM state description block corresponding to each VM holds the start address and end address of the real main memory area allocated to that VM (virtual real memory). In the example of FIG. 1, since VMm and VMn share the same area in the real main memory, both VMs hold the same value for the start address and end address in the VM state description block.

FIG. 4 shows a part of the address translation mechanism in the instruction processing device 3 relating to the present invention. The address translation in the instruction processing device 3 in the present invention will be described with reference to this drawing.

In FIG. 4, 10 is a register (FDR) for holding the data read from the main memory 1, 11 is a register (STOR) for holding the starting address of the segment table, and 12 is an instruction address sent from the instruction unit. Alternatively, the register that holds the address of the operand (LAR), 13 that holds the VM identification information (VMIDR), 14 that holds the start address of the allocated real main memory area (SAR), and 15 that also ends It is a register (EAR) that holds an address. 16 is a translation lookaside buffer (TLB) to hold address pairs before and after translation, 1
Reference numeral 7 is a TLB entry control circuit (TLBC) for determining the address of the entry in the TLB 16 from the address of the LAR 12. 18 and 19 are address adders, and 20 to 22 and 26 to 28 are comparators. 23 is a register that holds the prefix address used in VM mode (GPFX), 24 is a register that holds the prefix address used when not in VM mode (HPFX), 25 is a prefix circuit, and 27 is the actual address after address translation. This is a register (AARR) that holds the absolute address to the main memory.

When the instruction processing device 3 decodes the VM dispatch instruction during the processing of the VMM instruction string, the instruction processing device 3 reads the VM state description block described above, and enters the setup operation required for processing the dispatched VM. In the setup operation, the segment table starting point address in the VM state description block (this is in the control register field in the block), VM identification information, the start and end addresses of the real main storage area, and the prefix are stored in STOR11, VMIDR1
3, set to SAR15, GPFX23. The method of generating the main memory address used at this time is no different from the conventional technique. When the above setup operation is completed, the instruction processing unit 3 (not shown) also sets the PSW read from the VM state description block to a predetermined place in the instruction processing unit and enters the VM mode to dispatch the PSW. VMs
Command processing is started.

The address conversion in FIG. 4 is performed as follows. The virtual address generated by processing the instruction sequence is set in LAR12 by the instruction unit. This address is composed of a segment number (SX), a page number (PX), and an in-page address (DX). The segment number and page number portions and the contents of VMIDR13 are input to TLBC17 to select an entry in TLB16, and the corresponding entry is read. The read TLB entry has VM identification information (VMI
D), segment table origin address (STO), segment / page number (LA), and absolute address section (PA) on the actual main memory of the corresponding page. Read VM identification information and VMIDR13 contents, segment table start address and STOR11 contents, segment / page number and LAR1
2 segment / page number part is comparator 20,2 respectively
Compared with 1,22. If all the comparators 20, 21, 22 detect a match, it means that the corresponding entry is registered in the TLB16, and the absolute address part of the read entry and the in-page address part of the LAR12 are combined. It is set to AAR27 and becomes the absolute address when accessing the main memory.

When any of the comparators 20, 21, and 22 detects a mismatch, the entry read from the TLB 16 has a different virtual address, and the address conversion is performed as follows.

First, in order to read the segment table entry in the actual main memory using the segment table starting address in STOR11, the contents of STOR11 and the segment number part of LAR12 are added by adder 18, and the addition result is passed through prefix circuit 25. Perform prefix conversion. The contents of GPFX23 prepared for VM mode are used for the prefix conversion at this time. Address after prefix conversion is adder
The contents of SAR14 are added by 19 and set in AAR27 to become the absolute address for real main memory access.
At the same time, the output of the adder 19 is input to the comparator 26 and compared with the content of the EAR15. As a result of the comparison, the adder 19
If the output of is larger than the contents of EAR15, an address translation exception will occur and further address translation will be aborted.
When out-of-address translation is not detected, the address in the AAR 27 indicates the entry address of the segment table on the main memory 1, and the entry is read from the actual main memory.

The entry read from the real main memory is set in FDR10. This includes the starting point address part of the page table, is input to the adder 18, is added with the page number part of the LAR12, and is subjected to prefix conversion as in the reading of the segment table entry described above. The contents are added, set to AAR27, and compared with the contents of EAR15. When the output of the adder 19 is larger than the content of the EAR15 by the comparator 26, an address translation exception occurs and the subsequent address translation is stopped. If no address translation exception is detected, the address in the AAR 27 indicates the entry address of the page table in the real main memory, the entry is read from the real main memory, and the FDR 10 is set.

The read entry includes the real address (virtual real memory address of VM) in the virtual main memory of the page to be sought. This entry is allowed to pass through the adder 18 as it is, and the prefix circuit 25 performs prefix conversion, and then the adder 19 performs addition with the contents of SAR 14 and comparison with the contents of EAR 15 by the comparator 26. If no address translation exception is detected, the output of the adder 19 is the absolute address (real main memory address) of the page to be obtained on the real main memory, so this content is combined with the in-page address part of the LAR12. As a result, the in-page absolute address in the real main memory can be obtained. The origin address part of the page of the obtained address is STOR11, VMDR13, LA
A series of address conversion is completed by storing the contents in the corresponding entry in TLB16 together with the contents of each segment / page number part of R12.

After that, when the same page of the instruction processing device 3 is accessed, the entry in the TLB 16 is selected and used, so that the above address translation is not necessary.

The above is the address conversion according to the present invention in the instruction processing device 3. Next, the input / output operation will be described.

FIG. 5 shows the arrangement of control information relating to input / output operations in the absolute address space on the real main memory. In the figure,
The system area is an area that can be accessed by the program, and the program and the data handled by the program are stored in this area. The hardware area is an area that cannot be accessed by the program and is used by the hardware of the real computer system. In this hardware area, an area called an input / output control block (hereinafter referred to as IOCB) used for communication between the instruction processing device 3 and the input / output processing device 4 and control information of the input / output device are stored and the IOCB is stored. Similarly, a plurality of sub-channel control words (hereinafter referred to as SCCW) used for communication between the instruction processing device 3 and the input / output processing device 4 are placed. Figures 6 and 7 show IOCB and SCCW respectively.
Of the information therein, the portion related to the present invention is shown.

The sub-channel change instruction (hereinafter referred to as a sub-channel change instruction) for the program to access the sub-channel
MSCH instruction), a sub-channel operation start instruction group (hereinafter SS
CH command)) and so on. The MSCH instruction is used to set the subchannel to a specified operation mode according to the characteristics of the input / output device controlled by each subchannel for each subchannel provided corresponding to the input / output device. used. Further, the SSCH instruction is used to start execution of an input / output operation for a sub channel.

When the MSCH instruction is issued, the SCCW, that is, the subchannel of the above-mentioned hardware area corresponding to the subchannel number specified by the operand of the instruction is changed by the information of the area specified by the other operand of the same instruction. receive. No change is made when the subchannel is performing an I / O operation. When the SSCH instruction is issued, the status of the subchannel corresponding to the subchannel number specified by the operand of the instruction is checked. If the subchannel is ready for I / O operation, another operand of the same instruction is used. After the channel program address specified by the specified channel is set in the subchannel and the subchannel number and input / output instruction code, that is, SSCH code is set in IOCB, the instruction processing unit 3 enters the input / output processing unit 4. Output instruction activation notification is performed. If the sub-channel is already executing an I / O operation or if the sub-channel cannot accept a new I / O operation, the condition code corresponding to those conditions is set and the instruction is Upon completion, the input / output instruction activation notification to the input / output processing device 4 is not performed.

By implementing the present invention, the execution of MSCH and SSCH instructions is
The difference between the VM mode and the VM mode is as follows. When the instruction processing device 3 is not in the VM mode, that is,
MSC when the instruction processing unit 3 is executing a VMM program
In the H instruction, the subchannel information shown in FIG. 7 is not limited at all, and is changed by the information of the area specified by the operand of the MSCH instruction. When the instruction processing device 3 is in the VM mode, that is, when the instruction processing device 3 is executing the program in the VM mode by the VM dispatch instruction issued from the VMM, the MSCH instruction changes the subchannel information in FIG. Are subject to restrictions. At this time, the dedicated / shared identification information of the subchannel, the VM identification information, and the start address and end address portions are not changed. The dedicated / shared identification information in the sub-channel indicates whether this sub-channel is used by a specific VM or shared by multiple VMs. When the VM identification information indicates that this subchannel is dedicated, the VM that is dedicated to this subchannel
Identification information is set. The start address and the end address indicate the areas on the actual main memory that can be accessed by this subchannel. This information can only be changed by VMM. Other subchannel control information in FIG. 7 can be changed regardless of the VM mode.

Next time the SSCH instruction is issued, the instruction processing unit 3
When not in mode, dedicated / shared identities and VM identities in the sub-channel are not examined. When the instruction processor is in VM mode, the private / shared identification information in the sub-channel is examined. Then, when the sub-channel is shared, the input instruction activation notification to the input / output processing device 4 is performed as in the case of not in the VM mode. When the sub-channel is dedicated, VM identification information in the sub-channel and VM identification information in the instruction processor (this is VMIDR13 in FIG. 4).
There is a comparison with. This comparison is based on the fact that the comparator 28 compares the VM identification information part of the sub-channel read in the FDR 10 and the contents of the VMIDR 13 in FIG. If the comparison results do not match, the current instruction processing device 3
Indicates that the VMM does not allow access to this subchannel by the VM that is running on the SSCH instruction, and the SSCH instruction does not notify the I / O instruction start-up to the I / O processor 4 when the program check condition is detected. finish. If the comparison result is a match, an input / output command activation notification is sent to the input / output processing device 4.

Next, address conversion in the input / output processing device 4 will be described with reference to FIG.

In FIG. 8, reference numeral 30 is a common control section for performing common control for each channel of the input / output processing device 4, and 40 is one of the channels.
It is a channel part extracted, and in practice, a plurality of channel parts are mounted. 50 is a register (CFDR) for holding the read data from the main memory 1, 51 is a local memory (LS) for centrally holding control information related to input / output control, and 52 is an access to LS51. A register (LSAR) that holds the address when performing the operation, 53 is an address generation circuit (LSAC) that generates an LS register from the LSAR contents,
54 is a circuit (MSAC) that generates an address of a hardware area preset in the actual main memory, 55 and 56 are input registers (ACIR, ALIR) of the adder, and 57 is a register (CEAR that holds the end address). ), 58 is an adder, 59 is a register (ALR) that holds the output of the adder, and 60 is the output of the adder and C
A comparator for comparing the contents of EAR57, 61 is a register (CSAR) for holding an address at the time of real main memory access. Further, 71 in the channel unit 40 is a register (CDAR) for holding and updating the actual main memory address of the input / output data accompanying the input / output operation, and 72 is a register (CCR) for holding and updating the CCW being executed in the channel. ), 73 and 74 are registers (CBR) for buffering input / output data between the real main memory and the input / output device, and 75 is a circuit for controlling the I / O interface based on the contents of CCR72.

Now, when an input / output instruction activation notification is issued from the instruction processing device 3 to the input / output processing device 4, the input / output processing device 4
(Hereinafter referred to as IOP) reads the IOCB on the real main memory to CFDR50, inputs the subchannel number part to MSAC54, generates the real main memory address corresponding to the subchannel, and passes it through the adder 58. , Subchannel information is read from the actual main memory via ALR59, CSAR61. The read sub-channel information is stored in a predetermined location of LS51 via CFDR50.
Then, the channel designated by the channel designation information included in this sub-channel information is selected. When the specified channel can be activated, the CCW address, which is one of the sub-channel information (this is the channel program address which is set to the sub-channel by the instruction processing unit when the SSCH instruction is executed), is read from LS51 to ACIR55. Furthermore, the start and end addresses of the actual main memory assigned to this subchannel are set to ALIR56 and CEAR5, respectively.
Read to 7. The contents of ACIR55 and ALIR56 are added by the adder 58 and set in ALR59.
The comparison with the contents of R57 is performed by the comparator 60. If the output of the comparator 60 indicates that the added address is larger than the contents of CEAR57, an address translation exception is detected, this I / O activation is aborted, and the I / O interrupt causes a program check condition. Will be reported. If no address translation example is detected, the content of ALR59 is C
The CCW is sent to the main memory via the AAR61 and the CCW is read to the CFDR50. Since the address related to the input / output operation has an attribute as an absolute address, prefix conversion is not performed.

When CCW is read, the command part, flag part, and count part are transferred to CCR 72 in channel 40. The data address part (virtual real memory address) of CCW is transferred to ACIR55, and if the command part is not reverse read, the address for one page is added, and if it is the reverse read command, the address for one page is subtracted, The in-page address part is deleted and stored in LS51. Then, the contents of the ACIR 55 are added with the start address and compared with the end address in the same manner as described above. When the address translation exception is detected by the comparator 60, the input / output instruction activation operation is stopped.
If no address translation exception is detected, the contents of ALR 59 (actual main memory address) are transferred to the XDAR 71 in the channel unit 40, and the input / output operation by the channel unit 40 is started.

When the address in the CDAR71 detects a page boundary along with the data transfer of the channel section, the channel section 40 is controlled by the centralized control section.
Request an address change to 30. Upon receiving the address update and request, the central control unit 40 reads the data address part, the start address part and the end address part of the corresponding channel from the LS 51 and starts the data address part (virtual real storage address) in the same manner as described above. Address addition and comparison with the end address are performed. If the address translation exception is detected by the comparator 60, the centralized control unit 30 instructs the end of the input / output operation of the channel unit 40 and the input / output operation ends. CD if no address translation exception detected
A new address is set in AR71 and data transfer continues.

〔The invention's effect〕

According to the present invention, the real main memory is divided into a plurality of areas, and each of the divided areas is divided into an operating system (VM).
In a virtual computer system in which the plurality of VMs are respectively operated by an instruction processing device and an input / output processing device including a plurality of sub-channels, as a virtual real storage of By providing means for address constant calculation, that is, address conversion and its upper limit check on the instruction processor side and the input / output processor side respectively, without intervention of VMM,
It is possible to perform address translation associated with I / O processing on the I / O processor side independently of VM operation in the instruction processing unit, and to perform address translation not only for instruction processing but also for sub-channel I / O operations. This has the effect of eliminating the accompanying overhead of main memory access. Further, when the sub-channel is dedicated to a specific VM, a means for holding the identification information of the VM is provided, and the instruction processing device is provided with the identification information of the VM trying to access the sub-channel and the holding VM.
By providing a means for comparing with the identification information of the sub-channel, it is possible to protect the sub-channel from being unnecessarily accessed by another VM.

[Brief description of drawings]

FIG. 1 is a diagram showing the relationship between real main memory partitioning and VM allocation and VM state description block information in the virtual computer system of the present invention. FIG. 2 is a diagram showing the configuration of the real computer system. FIG. 3 is a diagram showing a state of VM dispatch by a VM monitor, FIG. 4 is a diagram showing an address conversion mechanism in an instruction processing device, FIG. 5 is a diagram showing an arrangement of input / output control information in a main storage device, and FIG. FIG. 7 is a diagram showing an input / output control block, FIG. 7 is a diagram showing subchannel information, and FIG. 8 is a diagram showing an address conversion mechanism in an input / output processing device. 1 ... Main storage device, 2 ... Storage control device, 3 ... Command processing device, 4 ... Input / output processing device, 5 ... Input / output device group,
13 …… VM identification information holding register, 14 …… Start address holding register, 15 …… End address holding register, 16 ……
TLB, 26 ... comparator, 51 ... local memory, 57 ... end address holding register, 60 ... comparator.

Claims (2)

[Claims] 1. A real main memory is divided into a plurality of areas, and each divided area is allocated as a virtual real memory of an operating system to each of the plurality of operating systems in a dedicated or shared manner. A virtual computer system in which a plurality of operating systems are respectively operated by an instruction processing device and an input / output processing device including a plurality of subchannels, wherein the instruction processing device is assigned to an operating system operating on the instruction processing device. A means for setting a start address and an end address of the real main memory area; a means for calculating the start address of the real main memory area set to the virtual real memory address issued by the instruction processing device; A means for comparing the address with the end address of the set actual main storage area is provided, The input / output processing unit is provided with an operating system that uses the sub-channel for each of the sub-channels.
Means for setting a start address and an end address of a real main storage area assigned to the system, and calculating a start address of the set real main storage area of the subchannel to a virtual real storage address issued by the subchannel And a means for comparing the calculated address with the end address of the set real main storage area of the sub-channel. 2. The virtual computer system according to claim 1, further comprising means for holding identification information of the operating system when the sub-channel is dedicated to a specific operating system, and instruction processing. The operating system trying to access the subchannel on the device
A virtual computer system comprising means for comparing system identification information with the retained operating system identification information.