JPH07130603A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a method for manufacturing a semiconductor device, which can perform highly accurate alignment between the constituent layers when forming the constituent layers of the semiconductor device. [Structure] Each of the constituent layers 10, 20, 3 on the semiconductor wafer 1
When 0 and 40 are sequentially formed, alignment targets 15 and 25 are formed on the constituent layers 10 and 20, respectively. Then, when another constituent layer 30 is further formed thereon, with reference to the alignment targets 15 and 25, the positional deviation of the wafer 1 with respect to the constituent layers 10 and 20 is reduced as much as possible. Exposure is performed after alignment. At that time, the alignment target 35 is also formed on the constituent layer 30. [Effect] Since the amount of misalignment between the constituent layers can be reduced, the standard value of the amount of misalignment can be set smaller than before, and further miniaturization and high integration can be achieved. it can.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique and a technique particularly effective when applied to a lithography process, for example, to a technique useful for alignment in an exposure apparatus.

[0002]

2. Description of the Related Art In general, each constituent layer such as an insulating layer and a conductive layer constituting a semiconductor device is coated with a resist on a semiconductor wafer and exposed using a mask having a desired pattern.
By developing and etching, the mask pattern is transferred and molded. Therefore, when the exposure is performed, it is necessary to perform the alignment between the mask and the wafer, that is, the alignment with high accuracy.

In order to perform alignment, the following has been done conventionally. That is, in the initial stage of the manufacturing process of a semiconductor device, for example, in the case of MOS, so-called LOCOS (local oxide), which is a selective oxide film for element isolation.
An alignment target (mark) that serves as an index for wafer alignment has been formed in a step of forming an on-of-silicon oxide film or a step of forming a gate insulating film. Then, in the subsequent exposure process, the position of the wafer was aligned based on the alignment target.

[0004]

However, the present inventors have clarified that the above-mentioned technique has the following problems. That is, since the alignment target is provided only on the specific reference layer in the early stage of manufacturing as described above, when the exposure is performed to form the constituent layers located above the reference layer, the reference layer is not used. The wafer could only be aligned with respect to the above. That is, since the constituent layers above the reference layer cannot be aligned with each other, even if the deviation amount of each constituent layer above them from the reference layer is small, the deviation amount between the upper constituent layers may be large. It is a thing. Therefore, the allowable range (standard value) of the misalignment amount must be determined in anticipation of the maximum misalignment between the constituent layers, which hinders further miniaturization and high integration. Was there.

The present invention has been made in view of the above circumstances, and provides a method of manufacturing a semiconductor device which can perform highly accurate alignment between the constituent layers when forming the constituent layers of the semiconductor device. The main purpose is to do. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, in the method for manufacturing a semiconductor device of the present invention, an alignment target is formed on each of the constituent layers of the semiconductor device at the same time when the constituent layers are sequentially formed. Then, in the case of forming a new constituent layer on the top by lithography, based on the alignment target of each constituent layer underneath, the wafer is aligned so that the amount of misalignment with respect to each constituent layer becomes smaller, The resist on the wafer is exposed. Further, in each constituent layer, a mask having a pattern in which the alignment target pattern is drawn in two or more places in addition to the LSI element pattern so that the alignment target can be formed in two or more places in one exposure. (In this specification, a reticle for reduction exposure is included in addition to a mask for equal-magnification exposure.).

[0007]

According to the above-mentioned means, when exposure is performed to form a new constituent layer, based on each alignment target in each constituent layer already formed below that,
Since the wafers are aligned with each other, the alignment between the constituent layers can be performed, and the amount of misalignment between the constituent layers can be reduced. Further, if the alignment targets are formed at two or more places by one exposure, at least two of the constituent layers are formed.
By using the alignment target at the location as a reference, it is possible not only to detect the rotation deviation of the wafer with respect to each constituent layer when forming a new constituent layer and reduce the deviation, but also to reduce the reduction magnification and the image distortion. It is also possible to detect and correct such as.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method of manufacturing a semiconductor device according to the present invention is shown in FIGS. 1 to 8 and described below. 1 and 2 schematically show an alignment target of a semiconductor device formed by the manufacturing method according to the present invention. As shown in the figure, in the present manufacturing method, the constituent layers 10, 2 such as an insulating layer and a conductive layer are formed on the semiconductor wafer 1.
When sequentially forming 0, 30, and 40, the constituent layers 10,
Alignment targets 15 and 25 are formed on 20 respectively. Then, when another constituent layer 30 is further formed thereon by lithography, that is, by exposure, development, and etching, the positional deviation amount of the wafer 1 with respect to the constituent layers 10 and 20 with reference to the alignment targets 15 and 25. The wafer 1 is aligned such that

Then, exposure is performed to transfer a mask pattern to a resist (not shown) on the wafer 1, and the constituent layer 30 is formed into a desired pattern through development and etching. At that time, the alignment target 35 is also formed on the constituent layer 30. When the constituent layer 40 is further formed, the alignment targets 15, 25, 3
The wafer 1 is aligned on the basis of 5.

Taking the constituent layer 30 as an example, an example of the flow of the exposure process in forming the constituent layer 30 will be described. First, an insulating film, a conductive film, or the like for forming the constituent layer 30 is further laminated on the constituent layers 10 and 20 in which the alignment targets 15 and 25 are formed and sequentially laminated. Then, after applying a resist on it, the wafer 1 is attached to the XY stage of the exposure apparatus.

Subsequently, the XY stage is moved to align the alignment targets 15 and 25 with the alignment detection position in the exposure apparatus. The detection position is irradiated with alignment illumination light for detection. Then, the reflected light of the illumination light is detected, and the detection signal is decomposed for each of the targets 15 and 25. That is, the positions of the targets 15 and 25 are individually detected by the disassembling process.

Then, with the alignment target 15 as a reference, the deviation amount (alignment offset) of the wafer 1 with respect to the constituent layer 10 is calculated and calculated, and
Based on the alignment target 25, the constituent layer 20
The deviation amount of the wafer 1 with respect to is also calculated and calculated. Further, the optimum position of the wafer 1 is calculated by arithmetic processing so that each deviation amount is as small as possible based on each deviation amount with respect to the constituent layers 10 and 20. At this time, the value obtained by simply adding each deviation amount may be minimized, or in consideration of the importance of each constituent layer, each deviation amount is multiplied by a coefficient according to the importance and added. However, the value may be minimized. That is, the shift amounts of the constituent layers are a, b,
When c, ..., The value of Expression (1) may be minimized. k ・ a + 1 ・ b + m ・ c, ... (k + 1 + m + ... = 1) ... (1)

The origin is adjusted by moving the XY stage so that the wafer 1 is positioned at the optimum position obtained by the arithmetic processing as described above. Then, exposure is performed to transfer the pattern (mask pattern) of the third constituent layer to the resist. At the time of exposure, if the resist is a positive type,
The mask targets 15 and 2 are arranged so that the portions corresponding to the resist targets 15 and 25 are not irradiated with the exposure light.
A portion corresponding to 5 is set as a light shielding portion. In the case of a negative resist, the portions of the mask corresponding to the targets 15 and 25 are used as the light transmitting portions.

The alignment targets 15 and 2
Reference numerals 5 and 35 each include, for example, a pair of marks and are linear recesses. Then, for example, the distance between the marks in each target is made smaller toward the upper layer, and when the constituent layers 10, 20, 30 are not displaced from each other, all the marks are arranged at equal intervals. Has become. In FIG. 1, in order to make it easy to distinguish the alignment targets 15, 25, and 35, for convenience,
Each target 15, 25, 35 is shown by a solid line and is hatched.

FIG. 3 shows an example of an exposure apparatus used in the manufacturing method according to the present invention. As shown in the figure, the exposure apparatus 5 has the same configuration as the conventional one, and includes an XY stage 50, a reduction projection lens 51,
The mask 52, the alignment illumination light source 53, the signal detection unit 54, the arithmetic processing unit 55, and the reflecting mirror 56. And
For example, the alignment illumination light and the reflected light pass through the reduction projection lens 51 but do not pass through the mask 52.
Ugh The Lens) -OFF This is an AXIS system device.

The signal detecting section 54 detects the reflected light of the alignment illumination light and is a camera or the like. The arithmetic processing unit 55 is, for example, a computer, and as described above, outputs the detection signal from the signal detection unit 54 to each target 1.
5 and 25 are disassembled, and the deviation amount of the wafer 1 is calculated and calculated for each of the constituent layers 10 and 20.
The calculation processing for obtaining the optimum position of is performed.

Further, as shown in FIG. 4, alignment targets 7 are formed at two or more places, for example, at four corners in an exposure region 6 irradiated by one exposure (one shot), so that each constituent layer is formed. The rotation deviation of the wafer 1 can be detected and corrected so as to reduce the deviation. Further, by obtaining the distance between the alignment targets 7 and 7, it is possible to detect the shift of the reduction ratio. Furthermore, four-point alignment target 7
Image distortion can also be detected and corrected by detecting the distortion of the shape formed by connecting.

As described above in detail, according to the above-described embodiment, when the exposure is performed to form the constituent layer 30 in a desired pattern, the alignment targets 15 and 25 of the constituent layers 10 and 20 are used. Since the wafer 1 is aligned, not only the displacement of the constituent layer 30 with respect to the constituent layer 10 can be reduced, but also the displacement of the constituent layer 30 with respect to the constituent layer 20 can be reduced. That is, it is possible to minimize the positional deviation between the constituent layers 10, 20, 30, 40. Therefore, the standard value of the misalignment amount can be set smaller, and further miniaturization and higher integration can be achieved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the alignment target may be formed on all of the constituent layers, or the target may be formed only on the constituent layers in which alignment is important.

Further, the alignment targets 15 and 2
Instead of being composed of a pair of marks, each of the marks 5, 35 may be composed of one mark as shown in FIG. In this case, the design value of each position of each target 15, 25, 35 may be stored in the arithmetic processing unit 55 in advance. Further, instead of making the shape of the target linear, the shape of the alignment targets 16, 26, 36 shown in FIG. 6 may be made rectangular. If you do this,
In the alignment targets 15, 25, 35 described above, the alignment can be performed only in the direction in which they are aligned (one direction), but the alignment can be performed in two directions at the same time. . Needless to say, the shape of the target is not limited to the concave shape and may be a convex shape.

Further, the exposure apparatus 5 is not limited to the OFF AXIS system shown in FIG. 7 (a system in which illumination light and reflected light do not pass through the reduction projection lens 51 and the mask 52). And the TTL shown in FIG.
It goes without saying that a -ON AXIS system (system in which illumination light and reflected light pass through both the reduction projection lens 51 and the mask 52) may be used.

In the above description, the case where the invention made by the present inventor is mainly applied to the manufacturing technology of the semiconductor device which is the application field as the background has been described, but the present invention is not limited thereto. It can also be used for micromachining technology.

[0023]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. In other words, since the alignment targets are provided on the respective constituent layers of the semiconductor device, the alignment can be performed on the respective constituent layers when a new constituent layer is formed. It is possible to reduce the amount of positional deviation of. Therefore, the standard value of the misalignment amount can be set smaller than the conventional value, and further miniaturization and high integration can be achieved.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing an alignment target of a semiconductor device formed by a manufacturing method according to the present invention.

FIG. 2 is a schematic view showing a state of a cross section of the alignment target.

FIG. 3 is a schematic configuration diagram showing an example of an exposure apparatus used in the manufacturing method according to the present invention.

FIG. 4 is a schematic view showing an example of arrangement of alignment targets.

FIG. 5 is a schematic view showing another example of the alignment target.

FIG. 6 is a schematic view showing still another example of the alignment target.

FIG. 7 is a schematic configuration diagram showing another example of the exposure apparatus.

FIG. 8 is a schematic configuration diagram showing still another example of the exposure apparatus.

[Explanation of symbols]

1 Semiconductor Wafer 7,35 Alignment Target 10 Constituent Layer (First Constituent Layer) 20 Constituent Layer (Second Constituent Layer) 30 Constituent Layer (Third Constituent Layer) 40 Constituent Layer 15 Alignment Target (First Alignment Target) ) 25 Alignment Target (Second Alignment Target)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G03F 9/00 H 9122-2H (72) Inventor Osamu Arao 3-3 Fujibashi, Ome City, Tokyo Within Hitachi Tokyo Electronics Co., Ltd. (72) Inventor Kohei Sekiguchi 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated Hitachi, Ltd. Semiconductor Business Division

Claims (3)

[Claims] 1. When sequentially forming each constituent layer constituting a semiconductor device on a semiconductor wafer, a first constituent layer is formed by:
A first alignment target, which serves as an index for aligning the wafer when forming the second constituent layer located above the first constituent layer, is formed, and a wafer of the first alignment target is formed based on the first alignment target. The alignment of the wafer when forming the second constituent layer by performing alignment and forming the third constituent layer above the second constituent layer on the second constituent layer A second alignment target serving as an index is formed, the wafer is aligned based on at least the first alignment target and the second alignment target, and a third constituent layer is formed. Manufacturing method of semiconductor device. 2. At least the first alignment target and the second alignment target are detected, and the positional deviation amount of each of the alignment targets is calculated and calculated, and the total of the positional deviation amounts becomes small. 2. The optimum position is calculated and obtained, the wafer is moved to the optimum position for exposure, and the pattern of the third constituent layer is transferred to the resist on the semiconductor wafer. Manufacturing method of semiconductor device. 3. When the constituent layers are exposed, two exposures are made in one exposure.
3. The method of manufacturing a semiconductor device according to claim 1, wherein a mask having a pattern capable of forming an alignment target is used at more than one place.