JPH0713850B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device, and more particularly to prevention of signal read error.

[Conventional technology]

FIG. 2 shows the structure of a bit line pair of a conventional dynamic semiconductor memory device. The bit line pair BL, ▲ ▼ includes a plurality of memory cells (C _S ), and a transfer gate TG for connecting the memory cells and the bit lines, which receives word line signals (WL ₀ , WL ₁ ...) At the gates. Connected. Each bit line is connected to a dummy cell (DC ₀ , DC ₁ ) for generating a reference level and a dummy word line (DWL ₀ , DWL ₁ ) connecting the bit line to the dummy cell, and the word line and the dummy word line. Rise, and after a signal voltage difference appears on the bit line pair, a sense amplifier (SA) for sense-amplifying the bit line potential is connected. A transfer gate that connects the bit line pair selected according to the column address to the data input line pair (I / O, ▲ ▼) The column decoder 1 output is input to this gate.

Next, consider the signal voltage appearing on each bit line pair during signal reading.

Each bit line is connected to the ground voltage (fixed potential) C ₁ ,
It has a capacitance of C _{2 for} a pair of bit lines and a capacitance of C ₃ for a bit line of an adjacent bit line pair. The bit line length is 1, and the memory cell capacity is C _S.

For memory cells, “H” level: C _S V _CC (V _CC write) “L” level: 0 (0 V write) For dummy cells, (To the capacity of C _S It is assumed that the electric charge is stored.

When the precharge level of the bit line is V _CC , for example, the memory cell connected to the bit line BL ₁ is selected, If a dummy cell is connected to the bit line The potential V _BL1 , ΔV _{▲ ▼} of However, ΔV _{▲ ▼} , ΔV _{▲ ▼} , V _BL1 and V _BL2 are potential changes of the bit lines indicated by the subscripts.

From equations (1) to (3), the bit line Considering that both have the same precharge level, the voltage difference between the bit line pair is as follows from the calculation of the equations (1)-(2) and (1)-(3).

"+" Is for "H" read character, "-" is for "L" read Right side of equation (4) The first term is the original read voltage difference, the second term is the bit line of adjacent bit line pair Is a noise component via the coupling capacitance from.

By the way, as the high integration of memory progresses and the bit line pitch decreases, the capacitance C ₃ between the bit line pair increases, and (4)
The second term in the equation becomes larger. Therefore, this causes a problem that the read voltage is remarkably impaired, the read margin is reduced, the soft error rate is deteriorated, and a malfunction finally occurs.

The following example is a device devised by the present inventors, in which the problems of the above device are solved, and the reduction of the read voltage amplitude due to the noise between adjacent bit line pairs due to the capacitance between bit lines is completely eliminated. It shows a semiconductor memory device that can be zero.

In the semiconductor memory device according to this example, by providing an intersecting portion at one place or a plurality of places on the bit line pair, each pair of bit lines receives exactly the same capacitive coupling noise from the adjacent bit line pair, and reading is performed. The voltage difference is not reduced.

Next, a semiconductor memory device according to this conventional improvement will be described with reference to FIG.

In this improved example, each bit line pair is Is divided into four equal parts a, b, c, d, and these equal points C
At P ₁ , CP ₂ and CP ₃ , they intersect as follows.

That is, the bit line pair Starting from, odd-numbered bit line pairs intersect at CP ₂ and even-numbered bit line pairs intersect at CP ₁ and CP ₃ . As a result, the capacitive coupling noise received by each bit line pair from the adjacent bit line pair is as follows when considered in the same manner as the above-mentioned conventional example.

Bit line Is the capacitive coupling noise ΔV _BL1 ′ received from the adjacent bit line pair,
ΔV _{▲ ▼} 'is And both are exactly the same.

Bit line Is the capacitive coupling noise Δ received from the adjacent bit line pair.
V _BL2 ′, ΔV _{▲ ▼} ′ is And both are exactly the same.

Similarly, for all bit line pairs, the bit lines forming each pair receive the same capacitive coupling noise from the adjacent bit line pairs. The bit line pair at the end of the memory array Also about And both are exactly the same.

As described above, in this improved example, the capacitive coupling noise received by the pair of bit lines from the adjacent bit line pair at the time of signal reading is completely equal, so that there is no reduction in the read voltage difference due to this noise. You can
It is possible to increase the read margin and improve the soft error rate.

FIG. 5 shows a second conventional improvement example. This modified example is different from the modified example of FIG. 4 in that odd-numbered bit line pairs In addition, a crossing is added at the bit line end CP ₄ . The intersections CP ₁ , CP ₂ and CP ₃ provided by this improvement are all
It is impossible to lay out these bit line pairs in perfect symmetry. In the modified example of FIG. 4, even-numbered bit line pairs In each of the above, since there are two intersections, a balanced layout is possible for the entire bit line pair. For example, if the bit line is an Al layer and the wiring layer that can intersect with it is a poly-Si layer, in CP ₁ , BL ₁ is Al, For poly Si, CP ₃ , BL ₁ for poly Si, May be Al, which makes it possible to avoid the imbalance of the stray capacitance of the bit line pair. The improved example of FIG. 5 has a similar effect to this, in which a dummy crossing CP ₄ is added so as to balance even the odd-numbered bit line pairs. It is possible to achieve a balanced state.

In the above improvement example, the bit line pair is divided into four sections and intersected at appropriate places, but this section has the same effect even if it is an integral multiple of 8 sections, 12 sections, etc. Play. Figure 6 shows an example of 8 divisions.
It is clear that the shape shown in FIG. 5 is repeated twice and the same effect as that of the example shown in FIG. 5 can be obtained.

Next, problems of such a conventional improved example will be described.

When the bit line pair includes a cross as in the above-mentioned improved example,
Consider the case where the dummy cell method is applied. FIG. 7 shows a configuration diagram when a conventional dummy cell system is applied to the device of FIG. In this figure, the word lines (WL ₀ , WL ₀ ′, WL ₁ , WL
The intersection of the ₁ ', ...) And the bit line indicates that the memory cell is arranged, and the dummy word line (DW
A circle mark at the intersection of L ₀ , DWL ₁ ) and the bit line indicates that a dummy cell is arranged. As shown in the figure, the memory cell arrangement is such that the memory cells selected by the word line WL ₀ are connected to the bit lines BL ₀ , BL ₁ , BL ₂ , BL ₃ ,.
The memory cells selected by the word line WL ₀ next to the word line WL ₀ ', the bit line Are alternately arranged, such as being connected to. This also applies to the dummy cell arrangement, for example, the dummy word line
The dummy cells selected by DWL ₀ are bit lines BL ₀ , BL ₁ ,
The dummy cells connected to BL ₂ , BL ₃ , ... And selected by the dummy word line DWL ₁ are the bit lines. Connected to.

Considering that it is necessary to connect the dummy cell to the bit line on the side opposite to the bit line to which the memory cell is connected (bit line on the reference side), in the case of FIG. 7, the word line in block a , WL ₀ , WL ₀ ′, WL ₀ is selected, DWL ₁ is selected, and WL ₀ ′ is selected, DWL ₀ is selected.

When the word lines WL ₁ and WL ₁ ′ in the block b are selected, even if any of DWL ₀ and DWL ₁ is selected, only half of the total number of bit line pairs are incompatible.

If the word lines WL ₂ , WL ₂ ′ in the block c are selected, if WL ₂ is selected similarly, DWL ₀ is selected, and if WL ₂ ′ is selected, DWL ₁ is selected. .

When the word lines WL ₃ , WL ₃ ′ in the block d are selected, the situation is similar to.

As described above, the conventional dummy cell method cannot be applied when such a bit line pair includes a cross.

[Problems to be solved by the invention]

Since the conventional semiconductor memory device is configured as described above, when the bit line pair includes a cross, a bit line pair in which the dummy cell is not connected to the bit line on the reference side appears in the normal dummy cell method, and is suitable for that method. There was a problem not to do.

The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor memory device to which the dummy cell system can be applied even when a bit line pair includes a cross.

[Means for solving problems]

A semiconductor memory device according to the present invention decomposes a memory cell array into a plurality of blocks by intersecting bit line pairs, and a block in which memory cells are connected to every other bit line and two memory cells every two. The blocks connected to the bit lines of the book are alternately arranged.

[Action]

In the present invention, the memory cell array is divided into blocks in which memory cells are connected to every other bit line and blocks in which every other two bit lines are connected, by the intersection of bit line pairs. As a result, the normal dummy cell method can be applied even when the bit line pair includes a cross.

〔Example〕

 Examples of the present invention will be described below.

FIG. 1 shows a semiconductor memory device according to an embodiment of the present invention. In this embodiment, compared with the conventional one shown in FIG.
The way of connecting the memory cells and the bit lines in the blocks b and d is different. Focusing on a certain word line, 1) In the blocks a and c, the memory cells are alternately connected every other bit line. In blocks b and d, memory cells are connected alternately every two bit lines, and only on one side of each bit line pair.

Here, the layouts of the memory cells for the connections 1) and 2) described above are possible under the same design criteria. Also,
Even with the arrangement as in 2), the memory cell operation is performed in exactly the same manner as in 1). Although the bit lines to which the memory cells are connected in the blocks b and d are different from the conventional example, even in this case, the effect of the conventional example, that is, the effect of canceling the coupling noise received from the adjacent bit line pair is exactly the same. Occur in.

In the case of the present embodiment, as a method of selecting the dummy word line, when WL _{0 in} block a is selected, DWL ₁ is selected as WL ₀ ′, and DWL ₀ is selected as WL in block b. _{If 1} is selected, DWL ₁ is selected as WL ₁ ′, DWL ₀ is selected as WL _{2 in} block c, DWL ₀ is selected as WL ₂ ′, If the DWL ₁ WL ₃ in the block c is selected, if the DWL ₀ WL ₃ 'is selected, it may be selected DWL _1, thereby the dummy cells which word lines in the block is selected Even if it works, it works effectively.

As described above, according to this embodiment, it is possible to realize the memory array to which the normal dummy cell system can be applied even when the bit line pair includes the intersection.

In the above description, the word lines WL ₀ and WL ₀ ′ are representative of the word lines in the block a, and the same applies to the other word lines in the block a.
The same applies to the other blocks.

Further, the arrangement position of the dummy word line is not limited to the position of the above embodiment, and may be another position.

Further, in the above embodiment, the case where it is applied to the conventional apparatus shown in FIG. 5 is shown, but the present invention can be similarly applied to other apparatuses such as those shown in FIGS.

Further, the dummy cell method is not limited to the case where the dummy cell acts on the bit line on the side opposite to the bit line to which the memory cell is connected as in the above embodiment, but when the dummy cell acts on the bit line on the same side (dummy reversal method). Etc.), and the present invention can be applied in the same manner as the above embodiment.

〔The invention's effect〕

As described above, according to the semiconductor memory device of the present invention, the memory cell array is divided into a plurality of blocks by the intersection of bit line pairs, and the memory cells are connected to every other bit line and every other two blocks. Since the blocks connected to the two bit lines are alternately arranged, it is possible to realize a memory cell array to which the normal dummy cell system can be applied even when the bit line pair includes an intersection, and the reliability is high. There is an effect that can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional semiconductor memory device, and FIG. 3 is a memory cell capacity of the conventional semiconductor memory device. FIG. 4, FIG. 5, FIG. 5, and FIG. 6 are configuration diagrams showing a conventional semiconductor memory device having a bit line pair crossing, and FIG. 7 is a dummy memory cell in a conventional semiconductor memory device having a bit line pair crossing. It is a block diagram when a system is applied. WL ₀ , WL ₁ ……… Word line, C _S …… Memory cell, SA ……
Sense amplifier, CP ₁ , CP ₂ , CP ₃ ... Crossing, CP ₄ ... Bit line end, a, b, c, d ... Block. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A memory cell array comprising a plurality of word lines, a plurality of bit lines, and a plurality of memory cells located at intersections of the word lines, the two bit lines forming a pair, and a voltage between the bit line pairs. In a semiconductor memory device having a configuration for inputting to one sense amplifier for detecting a difference, each bit line pair has an intersection at one location or a plurality of locations, and the memory cell array is a plurality of blocks divided by the intersection. A block in which the memory cells are connected to every other bit line of the bit lines intersecting the word line, and a bit line in which the memory cells intersect the word line. A semiconductor memory device characterized in that every other two adjacent bit lines are alternately arranged. 2. When each bit line pair is divided into four equal parts in the longitudinal direction and three equal dividing points and bit line ends are CP ₁ , CP ₂ , CP ₃ and CP ₄ , the bit line pair is Equal point CP ₂ and bit line end CP ₄
In the semiconductor memory device of Claims preceding claim, characterized in that the one with the cross and those having intersecting at equal points CP ₁ and CP ₃ are alternately arranged.