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JPH07120913B2 - Method for manufacturing chip-shaped electronic component - Google Patents

Method for manufacturing chip-shaped electronic component

Info

Publication number
JPH07120913B2
JPH07120913B2 JP2012869A JP1286990A JPH07120913B2 JP H07120913 B2 JPH07120913 B2 JP H07120913B2 JP 2012869 A JP2012869 A JP 2012869A JP 1286990 A JP1286990 A JP 1286990A JP H07120913 B2 JPH07120913 B2 JP H07120913B2
Authority
JP
Japan
Prior art keywords
electrode
extraction electrode
chip
groove
extraction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2012869A
Other languages
Japanese (ja)
Other versions
JPH03216009A (en
Inventor
康廣 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2012869A priority Critical patent/JPH07120913B2/en
Publication of JPH03216009A publication Critical patent/JPH03216009A/en
Publication of JPH07120913B2 publication Critical patent/JPH07120913B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Description

【発明の詳細な説明】 (a)産業上の利用分野 この発明は、複数の基板を積層して、その端面に外部電
極を形成したチップ状電子部品を製造するチップ状電子
部品の製造方法に関する。
Description: (a) Field of Industrial Application The present invention relates to a method for manufacturing a chip-shaped electronic component for manufacturing a chip-shaped electronic component in which a plurality of substrates are laminated and external electrodes are formed on the end faces thereof. .

(b)従来の技術 従来より、例えばチップ状積層セラミックコンデンサ
は、特定パターンの電極と引出電極が形成された複数の
基板を積層して積層体を形成し、その積層体の両端面に
外部電極を形成することによって製造されている。
(B) Conventional Technology Conventionally, for example, in a chip-shaped monolithic ceramic capacitor, a plurality of substrates having electrodes of a specific pattern and lead electrodes are laminated to form a laminate, and external electrodes are provided on both end faces of the laminate. Are manufactured by forming.

また、例えばチップ状圧電部品は、圧電基板の両主面に
特定パターンの電極と引出電極が形成されて成る圧電共
振子を2つの封止板間に積層して、この積層体の端面に
外部電極を形成することによって製造されている。この
チップ状圧電部品の外部電極形成部分の断面構造を第10
図に示す。
Further, for example, in a chip-shaped piezoelectric component, a piezoelectric resonator in which electrodes having a specific pattern and lead-out electrodes are formed on both main surfaces of a piezoelectric substrate is laminated between two sealing plates, and an external surface is provided on an end surface of the laminated body. It is manufactured by forming electrodes. The cross-sectional structure of the external electrode formation part of this chip-shaped piezoelectric component is
Shown in the figure.

第10図において1は両主面にAg膜からなる振動電極と引
出電極が形成された圧電基板であり、同図においては一
方の引出電極5が表れている。また、6,7はそれぞれ封
止板であり、これらの3つの基板が積層されて、その端
面にAg,Ag/Pd,Cu,Niまたはモネル等の膜からなる外部電
極11が形成される。このことにより、引出電極5の端部
が外部電極11に電気的に接続される。
In FIG. 10, reference numeral 1 denotes a piezoelectric substrate having a vibrating electrode made of an Ag film and a lead electrode formed on both main surfaces, and one lead electrode 5 is shown in the figure. Further, 6 and 7 are sealing plates, respectively, and these three substrates are laminated, and an external electrode 11 made of a film of Ag, Ag / Pd, Cu, Ni or Monel is formed on the end face thereof. As a result, the end portion of the extraction electrode 5 is electrically connected to the external electrode 11.

(c)発明が解決しようとする課題 ところが、第10図に示したような構造のチップ状電子部
品においては、引出電極5と外部電極11とは非常に微小
な領域で接続されるだけであるため、各基板寸法のバラ
ツキなどによって断線し易いという問題があった。
(C) Problem to be Solved by the Invention However, in the chip-shaped electronic component having the structure shown in FIG. 10, the extraction electrode 5 and the external electrode 11 are only connected in a very small area. Therefore, there is a problem that the wiring is easily broken due to variations in the dimensions of each board.

この発明の目的は、基板に形成されている引出電極に対
し、外部電極を確実に接続できるようにして信頼性を高
めたチップ状電子部品製造するチップ状電子部品の製造
方法を提供することにある。
An object of the present invention is to provide a manufacturing method of a chip-shaped electronic component for manufacturing a chip-shaped electronic component with improved reliability by reliably connecting an external electrode to an extraction electrode formed on a substrate. is there.

(d)課題を解決するための手段 この発明のチップ状電子部品の製造方法は、特定パター
ンの電極と引出電極が形成された基板を含む複数の基板
からなる積層体を形成し、その後に前記積層体の端面の
一部に前記引出電極が露出する溝を形成し、前記積層体
端面の一部または全部を被覆するように外部電極を形成
することを特徴とする。
(D) Means for Solving the Problem In the method for manufacturing a chip-shaped electronic component of the present invention, a laminated body including a plurality of substrates including a substrate on which an electrode having a specific pattern and an extraction electrode is formed is formed, and then the above-mentioned method is performed. A groove exposing the extraction electrode is formed in a part of the end surface of the stack, and an external electrode is formed so as to cover part or all of the end surface of the stack.

(e)作用 この発明のチップ状電子部品の製造方法においては、特
定パターンの電極と引出電極が形成された基板を含む複
数の基板からなる積層体の端面の一部に前記引出電極が
露出する溝を形成して、前記積層体端面の一部または全
部を被覆する外部電極を形成する。したがって、溝内に
おいて引出電極に外部電極を容易かつ確実に接続するこ
とができる。仮に引出電極の端面が積層体端面より内部
にある場合でも、上記溝の形成により、その溝内に引出
電極の端部が確実に露出される。また、溝の内面は、そ
の他の積層体端面とは異なり、平滑面であるため、引出
電極の端面と外部電極とが確実に接続される。しかも溝
の斜面において引出電極の端面が露出する場合には露出
面積が増大し、外部電極との接続状態もより確実にな
る。また、積層体の形成後に、その端部の一部を除去し
て引出電極を露出させるので、引出電極の必要な部分を
確実に露出させることができる。また、引出電極の上下
両側や一方の側のみを露出させる場合でも、その形状等
を任意に設計することができ高い密閉性を維持しなが
ら、信頼性の高い引出電極と外部電極の接続を行うこと
ができる。また、溝によって基板に対する引出電極の位
置精度や基板自体の寸法精度のバラツキを吸収すること
ができ、容易かつ確実に引出電極と外部電極とを接続す
ることができる。さらに、形成された積層体に溝を形成
するので、従来の積層体を製造するための設置を変更す
ることなく利用することができる。すなわち、積層体を
製造するための新たな設備投資等が不要である。
(E) Action In the method for manufacturing a chip-shaped electronic component of the present invention, the extraction electrode is exposed at a part of the end face of the laminate including a plurality of substrates including the substrate on which the electrode having the specific pattern and the extraction electrode are formed. A groove is formed to form an external electrode that covers a part or all of the end surface of the laminate. Therefore, the external electrode can be easily and surely connected to the extraction electrode in the groove. Even if the end surface of the extraction electrode is inside the end surface of the stacked body, the formation of the groove ensures that the end portion of the extraction electrode is exposed in the groove. Further, since the inner surface of the groove is a smooth surface, unlike the other end surfaces of the laminate, the end surface of the extraction electrode and the external electrode are reliably connected. Moreover, when the end face of the extraction electrode is exposed on the slope of the groove, the exposed area increases, and the connection state with the external electrode becomes more reliable. Further, since the lead electrode is exposed by removing a part of the end portion thereof after the formation of the laminated body, it is possible to surely expose the necessary portion of the lead electrode. Further, even when exposing the upper and lower sides or only one side of the extraction electrode, the shape and the like can be arbitrarily designed, and the highly reliable connection between the extraction electrode and the external electrode is achieved while maintaining high sealing property. be able to. Further, the groove can absorb variations in the positional accuracy of the extraction electrode with respect to the substrate and the dimensional accuracy of the substrate itself, and the extraction electrode and the external electrode can be connected easily and reliably. Further, since the groove is formed in the formed laminated body, it can be used without changing the installation for manufacturing the conventional laminated body. That is, new capital investment for manufacturing the laminated body is unnecessary.

(f)実施例 この発明のチップ状電子部品の製造方法によって製造さ
れるチップ状圧電部品の構造の一例を第1図〜第3図に
示す。
(F) Example FIGS. 1 to 3 show an example of the structure of a chip-shaped piezoelectric component manufactured by the method for manufacturing a chip-shaped electronic component of the present invention.

第1図は積層体の積層前の状態を表す分解斜視図であ
る。1は圧電基板であり、図において基板上面の中央部
に振動電極2、一方の辺に引出電極3を形成し、基板下
面中央部に振動電極4、引出電極3に対向する辺に引出
電極5をそれぞれ形成してエネルギ閉じ込め厚み振動モ
ードの圧電共振子を構成している。6,7はそれぞれセラ
ミック板からなる封止基板であり圧電基板1の上下に積
層することによって積層体を構成する。尚、圧電共振子
の振動電極付近の振動を阻害しないように、振動電極付
近にはわずかな空洞が形成される。
FIG. 1 is an exploded perspective view showing a state before stacking of the stacked body. Reference numeral 1 denotes a piezoelectric substrate. In the figure, a vibrating electrode 2 is formed in the center of the upper surface of the substrate, an extraction electrode 3 is formed on one side of the substrate, a vibrating electrode 4 is formed in the center of the lower surface of the substrate, and an extraction electrode 5 is formed on the side facing the extraction electrode 3. To form a piezoelectric resonator of energy trapping thickness vibration mode. Reference numerals 6 and 7 denote sealing substrates made of ceramic plates, which are laminated on the piezoelectric substrate 1 to form a laminated body. A slight cavity is formed near the vibrating electrode so as not to hinder the vibration of the piezoelectric resonator near the vibrating electrode.

第2図(A)〜(C)は積層体形成後の製造手順も表す
斜視図である。(A)に示すように圧電基板1を2つの
封止基板6,7間に積層し、その後、(B)に示すように
前記引出電極3,5の形成部付近にそれぞれ溝8,9を形成す
る。このことにより、溝8,9内に引出電極3,5の端面がそ
れぞれ露出する。
FIGS. 2A to 2C are perspective views also showing a manufacturing procedure after the laminated body is formed. As shown in (A), the piezoelectric substrate 1 is laminated between the two sealing substrates 6 and 7, and then, as shown in (B), grooves 8 and 9 are formed near the formation portions of the extraction electrodes 3 and 5, respectively. Form. As a result, the end faces of the extraction electrodes 3 and 5 are exposed in the grooves 8 and 9, respectively.

積層体端面の引出電極形成部付近に溝を形成する方法と
しては研削加工機による研削やサンドブラスト法など公
知の方法を用いることができる。通常、圧電基板1およ
び引出電極5は封止板6,7より軟質であるため、積層体
端面の全面をサンドブラスト処理することによって第3
図の例のように圧電基板1および引出電極5部分に溝9
を形成することができる。また、研削加工による場合に
は積層体端面の引出電極形成部付近に砥石車が接触する
ように位置決めする。なお、多数の積層体をカセットに
堆積させて同時に研削加工すれば一度に多数の積層体に
溝を形成することができる。
As a method of forming a groove in the vicinity of the extraction electrode forming portion on the end surface of the laminate, a known method such as grinding with a grinding machine or sandblasting can be used. Usually, the piezoelectric substrate 1 and the extraction electrode 5 are softer than the sealing plates 6 and 7, so that the entire surface of the end face of the laminated body is sandblasted to form a third layer.
As shown in the figure, grooves 9 are formed in the piezoelectric substrate 1 and the extraction electrode 5 portion.
Can be formed. In the case of grinding, the grinding wheel is positioned so as to come into contact with the vicinity of the extraction electrode forming portion on the end surface of the laminate. It should be noted that grooves can be formed in a large number of laminated bodies at one time by depositing a large number of laminated bodies in a cassette and simultaneously grinding them.

その後、第2図(C)に示すように積層体の両端面に外
部電極10,11を形成することによってチップ状圧電部品
を完成させる。
After that, as shown in FIG. 2C, external electrodes 10 and 11 are formed on both end faces of the laminated body to complete the chip-shaped piezoelectric component.

第3図は第2図(C)に示した状態におけるチップ状圧
電部品の中央部分断面図である。この図から明らかなよ
うに溝9内において引出電極5の端部が広い面積に亘っ
て露出し、積層体端面の全面に外部電極11が形成される
ことによって、引出電極5の端部が外部電極11と確実に
接続される。
FIG. 3 is a central partial sectional view of the chip-shaped piezoelectric component in the state shown in FIG. 2 (C). As is clear from this figure, the end portion of the extraction electrode 5 is exposed in the groove 9 over a wide area, and the external electrode 11 is formed on the entire surface of the end face of the laminated body. Securely connected to the electrode 11.

次に他のチップ状電子部品の例を第4図(A),(B)
に示す。
Next, examples of other chip-shaped electronic components are shown in FIGS. 4 (A) and 4 (B).
Shown in.

第4図(A)は溝および外部電極形成前の積層体の斜視
図であり、31,32,33はそれぞれ基板、34,35,36はこれら
の基板に形成されている引出電極である。このような積
層体形成後、第4図(B)に示すように、積層体に対し
溝37,38等を形成することによって、上記各引出電極を
溝内に露出させ、更に外部電極39,40,41を形成すること
によって三端子タイプのチップ状電子部品を完成させ
る。
FIG. 4 (A) is a perspective view of the laminated body before the formation of the groove and the external electrode. Reference numerals 31, 32 and 33 are substrates, and 34, 35 and 36 are extraction electrodes formed on these substrates. After forming such a laminated body, as shown in FIG. 4 (B), by forming grooves 37, 38 and the like in the laminated body, the respective extraction electrodes are exposed in the grooves, and further external electrodes 39, 38 are formed. By forming 40 and 41, a three-terminal type chip-shaped electronic component is completed.

次に積層体に形成する他の溝形状の例を第5図〜第8図
に示す。
Next, examples of other groove shapes formed in the laminated body are shown in FIGS.

第5図の例は封止板7の厚み方向の中心寄り部分に溝を
形成した例であり、引出電極5が溝9の上側斜面に露出
する。
The example of FIG. 5 is an example in which a groove is formed in a portion of the sealing plate 7 near the center in the thickness direction, and the extraction electrode 5 is exposed on the upper slope of the groove 9.

第6図は、ちょうど引出電極5を中心として溝9を形成
した例であり、引出電極5は溝9の底部に露出する。
FIG. 6 shows an example in which the groove 9 is formed with the extraction electrode 5 as the center, and the extraction electrode 5 is exposed at the bottom of the groove 9.

第7図は、封止板7に溝9を形成して引出電極5ほほと
んどそのまま残存させることによって、引出電極5の露
出面積5を増大させた例である。
FIG. 7 is an example in which the exposed area 5 of the extraction electrode 5 is increased by forming the groove 9 in the sealing plate 7 and leaving the extraction electrode 5 almost as it is.

さらに、第8図は引出電極5の上部および下部に溝9aお
よび9bを形成して引出電極5の端部を長く露出させた例
である。
Further, FIG. 8 shows an example in which grooves 9a and 9b are formed in the upper and lower portions of the extraction electrode 5 to expose the end of the extraction electrode 5 for a long time.

以上に示した例は何れも圧電基板の上下面に封止板6,7
を積層した例であったが、多数の基板に形成された多数
の引出電極を積層体の端面において外部電極と接続する
場合にも適用することができる。第9図はその多層チッ
プ状圧電部品の端部付近の部分断面図である。ここで、
21,23はそれぞれ圧電基板、22,24はそれぞれの圧電基板
に形成された引出電極、25,26,27はそれぞれ封止板、28
は外部電極である。図に示すように各基板を積層して引
出電極22,24の端面が溝内に露出するように2つの溝を
形成し、その後積層体の端面の全面に外部電極28を形成
している。このようにして各引出電極が共通の外部電極
28に対してそれぞれ確実に接続される。
In each of the above examples, the sealing plates 6 and 7 were attached to the upper and lower surfaces of the piezoelectric substrate.
However, the present invention can also be applied to a case where a large number of extraction electrodes formed on a large number of substrates are connected to external electrodes on the end faces of the laminated body. FIG. 9 is a partial cross-sectional view of the vicinity of the end portion of the multilayer chip piezoelectric component. here,
Reference numerals 21 and 23 are piezoelectric substrates, 22 and 24 are extraction electrodes formed on the respective piezoelectric substrates, 25, 26 and 27 are sealing plates, 28
Is an external electrode. As shown in the figure, the respective substrates are laminated to form two grooves so that the end surfaces of the extraction electrodes 22 and 24 are exposed in the grooves, and then the external electrode 28 is formed on the entire end surface of the laminated body. In this way, each extraction electrode is a common external electrode
Securely connected to each 28.

尚、各図においては説明上積層体に対する溝を深く描い
たが、実際にはもっと浅い溝で充分な効果が得られる。
In each drawing, the groove for the stacked body is drawn deep for the sake of explanation, but in reality, a shallower groove can provide a sufficient effect.

(g)発明の効果 この発明によれば、積層体の端面に形成された溝内に引
出電極の端部が確実に露出し、この溝内を含めて積層体
端面に外部電極が形成されるため、引出電極と外部電極
とは電気的に確実に接続されることになる。したがっ
て、基板に対する引出電極の位置精度および基板自体の
寸法精度のバラツキが上記溝によって吸収され、しかも
広い面積で引出電極と外部電極とが接続されるため、良
品率が高く信頼性の高いチップ状電子部品を製造するこ
とができる。また、引出電極の上下両側や一方の側のみ
を露出させる場合でも、その形状等を任意にでき高い密
閉性を維持しながら、信頼性の高い引出電極の接続を行
うことができる。さらに、形成された積層体に溝を形成
するので、従来の積層体を製造するための設備を変更す
ることなく利用することができ、積層体を製造するため
の新たな設備投資等が不要である。
(G) Effect of the Invention According to the present invention, the end portion of the extraction electrode is surely exposed in the groove formed on the end surface of the laminate, and the external electrode is formed on the end surface of the laminate including this groove. Therefore, the extraction electrode and the external electrode are electrically reliably connected. Therefore, variations in the positional accuracy of the extraction electrode with respect to the substrate and the dimensional accuracy of the substrate itself are absorbed by the groove, and since the extraction electrode and the external electrode are connected in a large area, the chip shape is highly reliable and highly reliable. Electronic parts can be manufactured. Further, even when only the upper and lower sides or only one side of the extraction electrode is exposed, it is possible to connect the extraction electrode with high reliability while maintaining a high hermeticity by making the shape and the like arbitrary. Further, since the groove is formed in the formed laminated body, it can be used without changing the equipment for manufacturing the conventional laminated body, and new capital investment for manufacturing the laminated body is unnecessary. is there.

【図面の簡単な説明】[Brief description of drawings]

第1図はこの発明の実施例であるチップ状圧電部品を構
成する各基板の構成を示す分解斜視図、第2図(A)〜
(C)は同チップ状圧電部品の製造途中の各状態を表す
斜視図、第3図は同チップ状圧電部品の中央部分断面図
である。第4図(A),(B)は三端子タイプのチップ
状電子部品の構成を示す図である。第5図〜第8図は積
層体に形成される異なった溝形状の例を示す断面図であ
る。第9図は多層チップ状圧電部品の部分断面図であ
る。第10図は従来のチップ状圧電部品の部分断面図であ
る。 1……圧電基板、2,4……振動電極、 3,5,34,35,36……引出電極、 6,7……封止板、 8,9,37,38……溝、 10,11,39,40,41……外部電極、 31,32,33……基板。
FIG. 1 is an exploded perspective view showing the constitution of each substrate constituting a chip-shaped piezoelectric component according to an embodiment of the present invention, and FIG. 2 (A)-
FIG. 3C is a perspective view showing each state during manufacturing of the chip-shaped piezoelectric component, and FIG. 3 is a central partial sectional view of the chip-shaped piezoelectric component. 4 (A) and 4 (B) are diagrams showing the configuration of a three-terminal type chip-shaped electronic component. 5 to 8 are sectional views showing examples of different groove shapes formed in the laminated body. FIG. 9 is a partial cross-sectional view of a multilayer chip piezoelectric component. FIG. 10 is a partial sectional view of a conventional chip-shaped piezoelectric component. 1 …… Piezoelectric substrate, 2,4 …… Vibration electrode, 3,5,34,35,36 …… Extraction electrode, 6,7 …… Seal plate, 8,9,37,38 …… Groove, 10, 11,39,40,41 …… External electrodes, 31,32,33 …… Board.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】特定パターンの電極と引出電極が形成され
た基板を含む複数の基板からなる積層体を形成し、その
後に前記積層体端面の一部に前記引出電極が露出する溝
を形成し、前記積層体端面の一部または全部を被覆する
ように外部電極を形成することを特徴とするチップ状電
子部品の製造方法。
1. A laminate comprising a plurality of substrates including a substrate on which an electrode having a specific pattern and an extraction electrode is formed, and thereafter, a groove exposing the extraction electrode is formed on a part of an end face of the laminate. A method for manufacturing a chip-shaped electronic component, comprising forming an external electrode so as to cover a part or all of the end surface of the laminate.
JP2012869A 1990-01-22 1990-01-22 Method for manufacturing chip-shaped electronic component Expired - Lifetime JPH07120913B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012869A JPH07120913B2 (en) 1990-01-22 1990-01-22 Method for manufacturing chip-shaped electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012869A JPH07120913B2 (en) 1990-01-22 1990-01-22 Method for manufacturing chip-shaped electronic component

Publications (2)

Publication Number Publication Date
JPH03216009A JPH03216009A (en) 1991-09-24
JPH07120913B2 true JPH07120913B2 (en) 1995-12-20

Family

ID=11817427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012869A Expired - Lifetime JPH07120913B2 (en) 1990-01-22 1990-01-22 Method for manufacturing chip-shaped electronic component

Country Status (1)

Country Link
JP (1) JPH07120913B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4412837B2 (en) * 2000-09-28 2010-02-10 京セラ株式会社 Multilayer electronic component and manufacturing method thereof
JP2018182039A (en) * 2017-04-12 2018-11-15 太陽誘電株式会社 Multilayer ceramic capacitor and method of manufacturing the same
JP7769588B2 (en) * 2022-05-27 2025-11-13 Tdk株式会社 Electronic component and method for manufacturing electronic component
JP2023174113A (en) * 2022-05-27 2023-12-07 Tdk株式会社 Electronic components and electronic component manufacturing methods
JP2023176236A (en) * 2022-05-31 2023-12-13 Tdk株式会社 Electronic components and electronic component manufacturing methods

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50864U (en) * 1973-04-30 1975-01-07
JPH025931U (en) * 1988-06-24 1990-01-16

Also Published As

Publication number Publication date
JPH03216009A (en) 1991-09-24

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