JPH07120700B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device.

In particular, the present invention relates to a semiconductor device manufacturing method with an improved element isolation method.

[Outline of Invention]

According to the present invention, in a method of manufacturing a semiconductor device, a step of forming a groove in a semiconductor substrate, a step of forming a first insulating layer on the surface of the semiconductor substrate including the groove, and a step of forming a first insulating layer on the surface of the first insulating layer. A oxidizable semiconductor layer, a step of forming a second insulating layer on the semiconductor layer to a depth not less than the depth of the groove to fill the groove, and a second step outside the groove. Etching the insulating layer using the oxidizable semiconductor layer as an etching stopper; etching the semiconductor layer outside the groove using the first insulating layer as an etching stopper; and etching the semiconductor layer. After the removal, the oxidizable semiconductor layer is oxidized to fill the concave portion by over-etching of the semiconductor layer above the groove with an oxide film. The controllability with makes it good,
The active region exposed by overetching is almost eliminated.

[Conventional technology]

In a semiconductor device such as an integrated circuit, usually, a groove is formed in a semiconductor substrate and an insulating material is embedded in the groove to separate elements.

FIG. 3 is a process diagram of a conventional element isolation method. Conventionally, first grooves 2 are formed by etching the semiconductor substrate 1, to fill the grooves 2 with SiO ₂ and then forming a SiO ₂ layer 3 on the surface of the semiconductor substrate 1 by CVD or the like, the SiO ₂ on the substrate 1 By etching away the so that SiO ₂ remains in the groove 2,
This separates the elements.

[Problems to be solved by the invention]

With the above-mentioned conventional techniques, it is difficult to uniformly etch SiO ₂ with good reproducibility. That is, because of the in-plane variations in the etching rate of the SiO ₂ in the in-plane distribution and RIE (reactive ion etching), variations occur such as the thickness of the SiO _2, SiO ₂ is the surface on the active region of the semiconductor substrate 1 If the conditions are set so that the film is completely etched in the inside, it is unavoidable to set the condition that the thickest part is etched.
As indicated by reference numeral 4 in the figure, there is a possibility that a portion is overetched partially and the side wall 4 of the active region is exposed. The exposure of the active region 4 also causes an increase in leak current, which is not preferable.

The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to provide an element isolation method for forming a stable isolation region in which an active region is not exposed with good controllability.

[Means for solving problems]

In order to achieve the above object, a method of manufacturing a semiconductor device of the present invention comprises a step of forming a groove in a semiconductor substrate, a step of forming a first insulating layer on the surface of the semiconductor substrate including the groove, A step of forming an oxidizable semiconductor layer on the first insulating layer; a step of forming a second insulating layer on the semiconductor layer to a depth not less than the depth of the groove to fill the groove; Etching away the second insulating layer outside by using the oxidizable semiconductor layer as an etching stopper; and removing the second insulating layer by etching, and then removing the semiconductor layer outside the groove. The step of etching away the first insulating layer as an etching stopper and the step of etching away the semiconductor layer, and then oxidizing the oxidizable semiconductor layer, thereby overetching the semiconductor layer above the groove. Part of a configuration and a step of embedding the oxide film.

[Action]

With the above structure, the controllability of the etching of the semiconductor layer is improved due to the existence of the first insulating layer, and the controllability of the etching of the second insulating layer is improved due to the existence of the semiconductor layer. Further, even if an over-etched portion is generated in the semiconductor layer in the groove opening portion when the semiconductor layer is etched, it can be oxidized and expanded to fill the over-etched portion. Even if overetching occurs in the first insulating layer in the groove opening due to the etching of the first insulating layer, the active region is hardly exposed because the first insulating layer is thin.

Example of Invention

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows an embodiment of the present invention, and particularly is a process chart of the element isolation method.

First, in step A, a groove 11 having a depth of, for example, 5000 Å is etched in a portion of the semiconductor substrate 10 made of silicon Si to be an element isolation region. In step B, the insulating film 12 that is the first insulating layer is formed on the entire surface of the substrate 10. this is,
For example, the substrate 10 is thermally oxidized to form a thin SiO ₂ film of about 500 Å. Then, in step C, an oxidizable semiconductor layer, for example, a polysilicon layer 13 is formed on the SiO ₂ film 12 to a thickness of 500Å. After forming the polysilicon layer 13, in step D, an insulator such as SiO ₂ 14 is deposited to a thickness of about 1 μm by CVD or the like, and the groove 11 is filled with SiO ₂ . This insulating layer 14 constitutes the second insulating layer, and here, as shown in the figure,
A recess 15 is formed in the upper part of the groove 11. Therefore, in step E, glass is spin-coated to form SO on the insulating layer 14.
The G layer 16 is formed and the upper surface is made flat.

After filling the groove 11 with SiO ₂ as described above,
Each deposited layer except 11 is etched to complete the formation of the element isolation region.

First, in step F, the SOG layer 16 and the insulating layer 14 are etched by RIE. This etching is performed over the entire surface with good controllability due to the presence of the polysilicon layer 13 as the lower layer of the insulating layer 14. Further, since the recess 15 is flattened by the SOG layer 16, the SiO ₂ 14 remaining in 11 is removed. The top surface of is flat. Next, in step G, the polysilicon layer 13 is etched by RIE. This etching is also performed over the entire surface with good controllability because the SiO ₂ layer 12 is formed under the polysilicon layer 13. By this etching in the step G, the polysilicon layer 13 is slightly over-etched at the opening of the groove 11 and a recess 17 is formed. Then, in step H, thermal oxidation is then performed to oxidize the exposed portion of the polysilicon layer, so that the oxidized portion 18 expands and the recess 17 disappears. And in step I,
The SiO ₂ film 12 is etched by RIE. Since this SiO ₂ film 12 has a small film thickness, the overetched portion at the opening end of the groove 11 of the substrate 10 which becomes the active region can be very small.

In this step, the SiO ₂ 12 which is the first insulating layer is entirely removed, but this SiO ₂ 12 may be partially removed.

Incidentally, in the above-mentioned embodiment, the process C and the process D of FIG.
A step of providing a passivation film 20 of Si ₃ N ₄ as shown in FIG. In addition, SiO ₂
It is preferable to provide a Si ₃ N ₄ film between the film 12 and the polysilicon layer 13 so that the active region is not oxidized.

〔The invention's effect〕

According to the present invention, since the material filling the groove is almost an insulator, the capacitance of the element isolation region does not increase, and the active region is hardly exposed by etching. In addition, since the insulator for element isolation is deposited after the semiconductor layer is provided, the insulator can be etched over the entire surface with good controllability, and the semiconductor layer is provided after the insulating film is provided on the substrate. The entire surface of the semiconductor layer can be etched with good control.

[Brief description of drawings]

FIG. 1 is a process diagram of an element isolation method according to an embodiment of the present invention, FIG. 2 is a sectional view of an element isolation region formation intermediate step according to a second embodiment of the present invention, and FIG. 3 is a conventional device. It is process drawing of the inter-separation method. 10 ... Semiconductor substrate, 11 ... Groove, 12 ... Insulating film (first insulating layer), 13 ... Semiconductor layer, 14 ... Insulating layer (second insulating layer), 15 ... Recess, 16 ... … SOG layer, 17 …… dent, 18 ……
Oxidation part.

Claims (1)

[Claims] 1. A step of forming a groove in a semiconductor substrate, a step of forming a first insulating layer on the surface of the semiconductor substrate including the groove, and an oxidizable semiconductor layer on the first insulating layer. A step of forming a second insulating layer on the semiconductor layer to a depth of the groove or more to fill the groove, and a step of forming the second insulating layer outside the groove, Etching away the oxidizable semiconductor layer as an etching stopper; etching the second insulating layer, etching the oxidizable semiconductor layer outside the groove, and etching the first insulating layer. A step of removing the oxidizable semiconductor layer by etching as a stopper, and oxidizing the oxidizable semiconductor layer after the oxidizable semiconductor layer is removed by etching to form a concave portion due to over-etching of the oxidizable semiconductor layer above the groove into an oxide film. Yo Method of manufacturing a semiconductor device having a burying.