JPH07128405A - LSI test board - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide an LSI test board that allows a test additional circuit for giving a desired function to a test board to a wide variety of test devices. A first substrate 1 having a first terminal 10 connected to a contact terminal of a test head and a second terminal 11 connected to the first terminal, and a second substrate of the first substrate. A second substrate 2 having a third terminal 20 detachably connected to the terminal and a plurality of fourth terminals 21 connected to the third terminal, and a fourth terminal of the second substrate Has a plurality of fifth terminals 30 detachably connected thereto and a third substrate 3 having an LSI socket 31 connected to the fifth terminals, and the second substrate is a predetermined one. The D / A conversion circuit 22 and the A / D conversion circuit 2 are provided between the terminal 20 of FIG.
A test additional circuit such as 3 is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI test board installed and used on a test head of an LSI tester, and is applied to an LSI test board that enables a digital / analog mixed LSI to be tested by a digital tester. Regarding effective technology.

[0002]

2. Description of the Related Art An LSI tester includes a storage device having a test program, a central processing unit for controlling the entire tester, a controller for controlling a bias voltage and a clock timing for a device under test as an LSI under test, and Some are configured by pin electronics including a driver for applying a voltage and timing according to a test program to a device under test by a control signal of the controller and a comparison circuit for comparing signals from the device under test. LS like this
An LSI test board on which a device under test is mounted is installed on the test head of the I tester. For example, a digital tester mainly has a function of testing a logical operation of a digital LSI, and has a function of measuring a current of a device under test, an input threshold voltage of each terminal, an input leak current, an output voltage, an output current and the like. . on the other hand,
Analog / digital mixed LS with analog circuit
When testing I, it has sufficient capability for testing the digital section, but for testing the analog section, it has the function of generating and measuring AC signals for measuring the frequency response, or measuring voltage and current. It is inferior in terms of fine resolution.

Such an analog / digital mixed L
When the SI is measured, if the analog part and the digital part are divided into two separate testers and the measurement is performed twice, it takes a long measurement time and the measurement cost becomes large. On the other hand,
Although it is possible to use an analog / digital dual-purpose tester, such a tester has a small measurement time and a low measurement cost, but the price per unit is high and its introduction is not always easy.

With respect to this point, Japanese Patent Laid-Open No. 64-39567 discloses an apparatus capable of efficiently and accurately measuring an analog / digital mixed LSI using a digital tester without impairing its versatility. . According to this, a second test board for connecting the test pins of the first board and the test head is provided between the first board on which the device under test is mounted and the test head of the digital tester. In this case, a board connecting connector is provided on the second board, and the board connecting connector connects the test pin of the test head not connected to the first board to the first board. Is. Then, for example, an external substrate that converts an analog signal output from the device under test into a digital signal and can supply the digital signal to the digital tester can be mounted on the substrate connecting connector.

As the structure of the LSI test board,
As described in JP-A-1-123172, a first board having a contact terminal connected to a contact pin of a test head and a load circuit for measurement connected to the contact terminal, on which an additional circuit board can be mounted. And a second substrate that is replaceably connected to the first substrate and has an LSI socket mounted therein. With this structure, the number of external terminals increases due to high integration of the device under test. It is said that this can be dealt with by changing the second board and the additional circuit board.

[0006]

However, in the one disclosed in the above-mentioned Japanese Patent Laid-Open No. 64-39567, the board connecting connector is the first device on which the device under test is mounted.
Since the board is unique to the board, the external board to be mounted and used in the board connecting connector must be created or prepared for each type of the device under test and the first board. Further, also in the one disclosed in JP-A-1-123172, both the second board and the additional circuit board must be changed in order to cope with an increase in the number of external terminals of the device under test, for example. In addition, JP-A-1-1231
In the structure described in No. 72, the second board on which the device under test is mounted and the additional circuit board are mounted on the first board, the wiring connecting them is lengthened, and is affected by noise or the like. It has been found by the present inventor that the reliability of the test may decrease. Further, the present inventor also examined the operating frequency of the test device, and as the analog / digital dual-use tester is more expensive than the digital tester, the faster the operating speed of the testable device is, the more the tester operates. When the frequency of the signal to be exchanged with a small number of terminals of the device under test is high, the satisfactory test cannot be performed unless an expensive tester is prepared for the function of the small number of terminals. I also found that there is a problem.

It is an object of the present invention to provide an LSI test board that allows a test additional circuit for giving a desired function to the test board to a general purpose for many kinds of test devices. Another object of the present invention is an LSI test board capable of shortening the signal wiring for connecting the additional test circuit and the device under test and the signal wiring for connecting the additional test circuit and the test head. To provide. Another object of the present invention is to
An object of the present invention is to provide an LSI test board that enables the tester to test an LSI that requires a small number or a part of signals having a frequency higher than the signal frequency that the tester can support.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

(1) A first substrate having a plurality of first terminals connected to the contact terminals of the test head and second terminals connected from the first terminals through predetermined wirings. ,
A second terminal having a third terminal detachably connected to the second terminal of the first substrate and a plurality of fourth terminals connected to the third terminal through a predetermined wiring. Board, a plurality of fifth terminals detachably connected to the fourth terminal of the second board, and an LSI socket connected to the fifth terminal through a predetermined wiring. A third board, and the second board is provided with an additional test circuit for changing and outputting the input signal between a predetermined third terminal and a predetermined fourth terminal. It is provided to form an LSI test board. That is, the first to third substrates are vertically stacked in three stages. (2) To enable the test by the digital tester of the analog / digital mixed LSI, a D / A conversion circuit and an A / D conversion circuit can be adopted as the additional test circuit. (3) In order to enable the tester to test an LSI that requires a signal with a frequency higher than the signal frequency that the tester can support, the frequency of the clock signal supplied from the predetermined third terminal is used as the test additional circuit. A first frequency conversion circuit that raises the frequency and supplies it to a predetermined fourth terminal, and a second frequency that lowers the frequency of the signal supplied from the predetermined fourth terminal and supplies it to a predetermined third terminal. A conversion circuit can be employed. (4) A tester can be supported on an LSI test board that interfaces an LSI socket in which an LSI under test is mounted to a plurality of contact terminals of a test head, regardless of the above-described three-tiered structure of the LSI test board. In order to enable the tester to test an LSI that requires a signal having a frequency equal to or higher than the signal frequency, the first frequency conversion in which the frequency of the clock signal supplied from the predetermined contact terminal of the test head is increased and the LSI is supplied to the LSI socket An LSI test board is configured by providing a circuit and a second frequency conversion circuit that lowers the frequency of the signal supplied from the LSI socket and supplies the signal to a predetermined contact terminal. (5) In order to simply configure the first frequency conversion circuit, a phase locked loop circuit in which a frequency divider is provided in the frequency feedback circuit can be adopted. (6) In order to simply configure the second frequency conversion circuit, the signal supplied from the LSI socket is synchronized with the frequency of the timing signal supplied via the predetermined contact terminal of the test head so as to synchronize with the predetermined frequency. An output gate circuit that outputs to the contact terminal can be adopted.

[0011]

According to the above means, the structure of the LSI test board in which the first to third substrates are vertically stacked in three stages connects the additional test circuit and the device under test because of the vertically stacked structure. The signal wiring for connecting the test additional circuit and the test head is shortened. Further, in the three-stage vertically stacked structure, the connection mode between the fifth terminal on the third substrate and the LSI socket is changed depending on the type of the device under test, the pin arrangement of the test device and the difference in the number of pins. It is possible to deal with it by simply replacing the third board, that is, by adding only a third board to the test board. Make it universally available to test devices. The first and second frequency conversion circuits mounted on the LSI test board enable the tester to test an LSI that requires a small number or some terminals of a signal having a frequency higher than the signal frequency that the tester can support.

[0012]

1 is a plan view of an LSI test board according to a first embodiment of the present invention, and FIG. 2 shows a vertical sectional structure of the LSI test board. The LSI test board shown in the figure is a first test board such as a test fixture board.
Substrate 1, a second substrate 2 such as a measurement circuit substrate, and a third substrate 3 such as a socket conversion substrate are vertically stacked in three stages on a test head 4 of a tester.

The first substrate 1 has a plurality of first terminals 10 connected to the contact terminals 40 of the test head 4 and second terminals connected to the first terminals 10 via predetermined wirings. 11 and. A load circuit (not shown) on the first substrate,
A relay 12, a buffer 13 and the like are arranged.
The relay 12 is used for switching the connection mode between the first terminal 10 and the second terminal 11 and for switching the load circuit connected to the second terminal 11. The relay 12 can be controlled from the tester side or by setting a dip switch (not shown) on the first substrate 1. Although not particularly limited, the buffer 13 performs conversion of signal amplitude to be supplied from the predetermined second terminal 11 to the predetermined first terminal 10 and signal amplification.

The second substrate 2 is the second substrate of the first substrate 1 described above.
Third terminal 20 detachably connected to the terminal 11 of the
And a plurality of fourth terminals 21 connected to the third terminals 20 via predetermined wiring. This second substrate 2 is
Between the predetermined third terminal 20 and the predetermined fourth terminal 21, an additional test circuit for changing the format of the input signal and outputting the input signal is provided. In the first embodiment, the test additional circuit is not particularly limited, but D / which converts the digital information supplied from the predetermined third terminal 20 into analog information and supplies the analog information to the predetermined fourth terminal 21. A conversion circuit 22,
The A / D conversion circuit 23 converts the analog information supplied from the predetermined fourth terminal 21 into digital information and supplies the digital information to the predetermined third terminal 20. As the D / A conversion circuit 22, a load resistance type D / A conversion circuit, a D / A conversion circuit using a ladder resistance network, and a segment type or digital correction type D / A conversion circuit are required. Can be adopted according to. As the A / D conversion circuit 23, a double integration type, successive approximation type, parallel comparison type, etc. A / D
A conversion circuit can be adopted as appropriate.

The third substrate 3 has a plurality of fifth terminals 3 detachably connected to the fourth terminals 21 of the second substrate 2.
0 and an LSI socket 31 connected to the fifth terminal 30 via a predetermined wiring.

FIG. 3 shows the structure of the fourth terminal 21 and the fifth terminal 30 as an example of the terminal structure which is detachably connected. The structure shown in (A) of the figure is a male-female fitting structure, and the fifth terminal 30 is fitted into a hole formed in the upper end portion of the fourth terminal 21. (B) in the figure
The structure shown in is a so-called pogo pin structure,
The fourth terminal 21 is configured by providing a piston 30b, which is elastically urged downward by a compression coil spring 30a, in the cylinder 30c, and the fifth terminal 30 is configured by the piston 30b.
It is configured as a contact terminal that contacts the tip of the. In this terminal structure, the upper and lower screw portions 30e of the posts 30d functioning as spacers for positioning and fixing the upper and lower substrates 2 and 3 in the horizontal direction are inserted into the upper and lower substrates 2 and 3 and fixed with nuts 30f. Has been added. Regarding the structure of the other terminals, the structure of the terminals 21 and 30 can be appropriately selected and adopted.

FIG. 4 shows an example of the third substrate 3 as the socket conversion substrate. Although not particularly limited, the LSI socket 31 shown in the drawing has terminals P1 to P14, and accordingly, the fifth terminal of the third substrate is set to 30-1 to 30-14. According to this example, the terminals P1 to P14 are sequentially connected to the fifth terminals 30-1 to 30-14 via the pattern wiring 33 of the substrate.

Device under test DUT shown in FIG.
Is an analog / analog converter including an A / D converter ADC that inputs an analog signal from the terminal P1, a D / A converter DAC that outputs an analog signal to the terminal P7, and a logic circuit LOG.
It is a digital mixed LSI.

According to this example, the fifth terminal 30-1 is an analog input terminal, the terminal 30-7 is an analog output terminal, and the terminals 30-2 to 30-6 and the terminals 30-9 to 30-13 are digital input terminals. The output terminal and the terminal 30-14 are power supply terminals such as VCC, and the terminal 30-8 is a reference potential terminal such as GND. Therefore, the fifth terminals 30-1 to 30-
The function of each of the fourth terminals 21 connected to 14 corresponds to that. For example, the terminal 30-1 is the second substrate 2
Is connected to the analog output of the D / A conversion circuit 22 in the above through the predetermined fourth terminal 21, and the terminal 30-7 is connected to the analog input of the A / D conversion circuit 23 in the second substrate 2 by the predetermined fourth terminal. It is connected via the terminal 21.

The signal input / output function of the second terminal 11 on the first substrate 1 and the second terminal 11 and the first terminal 10
For the connection form by the relay 12 etc.
It will be determined according to the specific signal input / output functions of the board 2 and the third board 3.

The first terminal 10 of the LSI test board of this embodiment is connected to the contact terminal 40 provided on the test head 4 of the digital tester. The digital tester supplies a test signal to the device under test DUT according to the test program, and the device under test DUT is thereby supplied.
Observe the signal output from the UT. At this time, when the device under test DUT requires an analog signal, the digital tester outputs a digital signal for generating the analog signal in the D / A conversion circuit 22. on the other hand,
The analog signal output from the device under test DUT is converted into a digital signal by the A / D conversion circuit 23, and the digital tester takes in the digital signal and observes it. Therefore, the device under test DUT A
The test including the D / A converter ADC and the D / A converter DAC is performed by the additional test circuit 2 mounted on the second substrate 2.
It can be performed by the digital tester by the action of 2, 23. At this time, since the second substrate and the third substrate are vertically stacked, the A / D converter ADC and the D / A converter DAC built in the device under test DUT and the second substrate Since the wiring connecting the D / A conversion circuit 22 and the A / D conversion circuit 23 as well as the wiring from the test head 40 to the device under test DUT are short,
A highly reliable device test can be performed by minimizing the influence of noise.

FIG. 5 shows an example of the third substrate 3 when the device under test DUT is an analog / digital mixed LSI having only an A / D converter ADC as an analog circuit interfaced with the outside. The difference from FIG. 4 is that the DUT converter DAC is not mounted in the device under test DUT and the terminals P3 to P7 are connected to the logic circuit L.
The analog input of the A / D converter ADC is connected to the terminal P2 and the terminal 30-1 of the substrate 3 is connected to the terminal P2, and the terminals 30-2 to 30-6 are connected to the terminal P3. That is, they are separately connected to P7 by the pattern wiring 33, respectively. This difference is because the functions of the terminals 30-1 to 30-14 of the third substrate are maintained as they are.
That is, when the device under test DUT is different,
Only by changing the pattern wiring 33 for connecting the terminals 30-1 to 30-14 of the third board and the terminals P1 to P14 of the LSI socket 31, the setting mode of the first board and the second board 2 can be changed. It can be used as it is for testing another device under test as shown in FIG.

FIG. 6 shows an example of the third substrate 3 when the device under test DUT is an analog / digital mixed LSI having only a D / A converter DAC as an analog circuit interfaced with the outside. The difference from FIG. 4 is that the device under test DUT is not equipped with the A / D converter ADC, the terminals P3 to P5 and P7 are connected to the logic circuit LOG, and the analog output of the D / A converter ADC is the terminal. The terminal 30-6 of the substrate 3 is connected to the terminal P6 and the terminals 30-2 to 30- are connected to the terminal P6.
5 and 30-7 are separately connected to the terminals P3 to P5 and P7 by the pattern wiring 33, respectively. The difference is that the functions of the terminals 30-1 to 30-14 of the third substrate are maintained as in the case of FIG. That is, when the device under test is different from that of FIG. 4, only the pattern wiring 33 for connecting the terminals 30-1 to 30-14 of the third substrate and the terminals P1 to P14 of the LSI socket is changed. Then, the setting mode of the first substrate and the second substrate 2
It can be used as it is for testing another device under test as shown in FIG.

FIG. 7 shows an example of a conversion circuit 24 different from the A / D conversion circuit 23 as an additional test circuit mounted on the second substrate 2. The device under test DUT shown in the figure is a VTR servo LSI for servo-controlling the tape drive system of the VTR, although not particularly limited thereto. The pulse width modulation signal PWM output from the device under test DUT is the ground potential GND and the power supply voltage VDD.
And 4 types of DC levels BL1 to BL4 between which the pulse widths are different from each other. The conversion circuit 24 shown in the figure converts such a pulse width modulation signal PWM into a signal in which only the pulse width is significant. In this specification, such a conversion can also be regarded as an A / D conversion.

The conversion circuit 24 is a 2-bit digital signal DA supplied from a digital tester (not shown).
1, DA2 is converted into one of four values by the A / D converter 25, and the level shift circuit 26 level-shifts it to a level between the power supply voltage VDD and the ground potential GND. The level output from the level shift circuit 26 is 4 in total.
The levels are L1 to L4. This level L1-L
Reference numeral 4 is a reference level for determining a signal waveform superimposed on four types of DC levels BL1 to BL4 in the pulse width modulation signal PWM. The output of the level shift circuit 26 and the pulse width modulation signal PWM are supplied to the comparator 27. The comparator 27 outputs a high level when the level of the pulse width modulation signal PWM is higher than the reference level, and outputs a low level when the level is low. The 2 bits DA1 and DA2 for forming the reference level are supplied from the tester so that the reference levels L1 to L4 corresponding to the DC level of the pulse width modulation signal PWM can be sequentially generated. Therefore, as shown in FIG. 7, the output of the comparator 27 is a signal in which only the pulse width of the pulse width modulation signal PWM is significant.

FIG. 8 shows an LSI according to the second embodiment of the present invention.
A top view of the test board is shown. Also in this embodiment, the first substrate 101, the second substrate 102, and the third substrate 103 are vertically stacked as in the first embodiment described with reference to FIGS. Substrate 101, 102, 103
The basic configuration of the first is described with reference to FIG. 1 and FIG.
This is the same as the boards 1, 2, 3 of the embodiment, and the same circuit members are designated by the same reference numerals and detailed description thereof will be omitted.

The major difference between the first embodiment and the second embodiment is the configuration of the additional test circuit mounted on the second substrate 102. The additional test circuit of this embodiment includes a first frequency conversion circuit 28 which raises the frequency of a clock signal supplied from a predetermined third terminal 20 and supplies it to a predetermined fourth terminal 21, and a predetermined frequency conversion circuit 28. The second frequency conversion circuit 29 lowers the frequency of the signal supplied from the fourth terminal 21 and supplies the signal to the predetermined third terminal 20. As the first frequency conversion circuit 28, a phase locked loop circuit in which a frequency divider circuit is provided with a frequency divider can be adopted. Further, as the second frequency conversion circuit, the LS
It is possible to employ an output gate circuit that outputs a signal supplied from the I socket to a predetermined contact terminal in synchronization with the frequency of a timing signal supplied via a predetermined contact terminal of the test head. The difference in such an additional test circuit on the LSI test board is
Specific LSI socket 31 provided on the substrate 103 of
And the type of device under test mounted therein, and the specific switch control states of the relay 12 and the like on the first substrate 101 are also different.

By using the above-described frequency conversion circuits 28 and 29 as the additional test circuit, the tester can support a part of the signal frequencies required for operating the device under test mounted in the LSI socket 31. Even when the frequency exceeds the maximum frequency, the tester only needs to output the signal of the frequency supported by the tester.
Raises the signal frequency and supplies it to the device under test. When the frequency of the specific signal output from the device under test is also a frequency that the tester cannot directly process, the second frequency conversion circuit 29 lowers the signal frequency of the high frequency and supplies it to the tester. This enables the tester to test an LSI that requires a signal with a frequency higher than the signal frequency that the tester can support. Further, similarly to the first embodiment, when the device under test DUT is different by the vertically stacked three-stage configuration of the LSI test board,
By only changing the pattern wiring 33 for connecting the fifth terminal 30 of the third substrate 3 and the terminal of the LSI socket 31, the setting mode of the first substrate 1 and the second substrate 2 itself can be changed. It can be directly used for testing another device under test DUT.

FIG. 9 shows a third embodiment of the present invention.
The LSI test board of the embodiment shown in the figure is not limited to the three-stage vertically stacked structure described in the above embodiment, and the LSI socket 31 in which the device under test DUT is mounted is connected to a plurality of test heads. It is configured as an LSI test board for interfacing with terminals. The LSI test board of this embodiment is provided with a first frequency conversion circuit 60 for increasing the frequency of a clock signal supplied from a predetermined contact terminal of the test head and supplying it to the LSI socket 31, and a first frequency conversion circuit 31 supplied from the LSI socket. And a second frequency conversion circuit 70 for lowering the frequency of the signal to be supplied to a predetermined contact terminal.

According to FIG. 9, the first frequency conversion circuit 60 is a phase locked loop circuit (hereinafter also simply referred to as a PLL circuit 60) in which a frequency feedback circuit includes a frequency divider. The PLL circuit 60 is not particularly limited, but the phase comparison circuit PD, the low pass filter LPF,
Voltage control oscillator VCO and programmable frequency divider D
It is composed of IV. The phase comparison circuit PD compares the phase of the 38.5 MHz clock signal output from the tester 80 with the output of the programmable frequency divider DIV, and if there is a difference, generates a voltage proportional to the direction and magnitude of the phase. Output. This voltage is smoothed by the low-pass filter LPF and input to the voltage control oscillator circuit VCO, and its output signal frequency is changed until the output frequency of the programmable frequency divider circuit DIV becomes equal to the output signal frequency of the tester 80. The loop control is repeated to make the output signal frequency of the voltage control oscillator circuit VCO stable. Accordingly, the output signal frequency of the voltage control oscillator circuit VCO is, for example, the division ratio of the programmable frequency divider DIV is 1 /
If it is n, it is n times 38.5 MHz. In the figure, the signal frequency is 135 MHz, for example. Therefore, even if the tester 80 whose maximum frequency of a processable signal is about 40 MHz is used, a signal having a higher frequency can be supplied to the device under test DUT. By adopting the programmable frequency divider DIV as the frequency divider, the versatility of the first frequency conversion circuit, that is, the second substrate 2 can be increased.

According to this embodiment, the device under test DU
T operates in synchronization with such a high frequency signal, and R,
The G, B, and I signals are also output with high frequencies as in the above. At this time, the second frequency conversion circuit 70
Is an output gate for outputting a signal supplied from the LSI socket 31 toward a predetermined contact terminal in synchronization with a frequency of a timing signal (output latch strobe) φ supplied through a predetermined contact terminal of the test head. A circuit (hereinafter also simply referred to as the output gate circuit 70). That is, the output gate circuit 70 has four comparators 71 to 74 corresponding to the respective signals R, G, B and I, and the respective comparators 71 to 74 have a common output latch strobe φ at a low level. The output operation is performed each time the output instruction level is set to the above, and the output is supplied to the tester 80 separately. According to this example, the output gate circuit 70 outputs the signals R, G, and the signals output from the device under test DUT.
Although B and I will be thinned out and supplied to the tester 80,
It is sufficient if the required accuracy can be obtained in relation to the resolution necessary for measuring the signals R, G, B and I.

FIG. 10 shows an example block diagram of the device under test DUT shown in FIG. The device under test DUT shown in the figure is a color palette LSI. This color palette LSI has logic circuits 92, 9
3, a RAM 94, and a DA converter 95. In an actual system, they are interfaced with and controlled by the frame buffer memory 90 and the microprocessor (MPU) 91, and R (red), G (green), B (blue), Each analog signal of I (luminance) is supplied to a display device (not shown). The logic circuit 92 is the frame buffer memory 90.
The image data is read from and is drawn in the RAM 94. The logic circuit 93 decodes the command from the microprocessor 91, performs data processing for changing the display color of the image data drawn in the RAM to a desired color, and executes the data processing.
The image data after data processing is expanded to. The DA converter 95 D / A converts the image data expanded in the RAM and outputs it.

The configuration of the PLL circuit 60 and the output gate circuit 70 shown in FIG. 9 is the frequency conversion circuit 2 of FIG.
It can also be applied to 8, 29. In this case, the input on the side opposite to that which receives the output of the programmable frequency divider DIV by the phase comparator circuit PD is coupled to a predetermined third terminal 20 on the second substrate 2 and the voltage control oscillator circuit VCO. The output is coupled to a predetermined fourth terminal 2 on the second substrate 2. The input of the gate circuit 70 is the second substrate 2
, And the output of the gate circuit 70 is coupled to a predetermined third terminal 20 of the second substrate 2.

According to the above embodiment, there are the following effects. (1) The structure of the LSI test board in which the first to third substrates 1 to 3 are vertically stacked in three stages is D
A / A converter DAC, A / D converter ADC, first frequency conversion circuit 28, second frequency conversion circuit 29, PLL circuit 60, output gate circuit 70 and other test additional circuits and the device under test DUT. The signal wiring for connecting and the signal wiring for connecting the additional test circuit and the test head can be shortened. This can improve the reliability of device testing by minimizing the influence of noise and the like. (2) D / A converter DAC or A as an additional test circuit
By adopting the / D converter ADC, the analog / digital mixed LSI can be tested by the digital tester. (3) In the three-stage vertically stacked structure, the type of the device under test, the pin arrangement of the test device, the difference in the number of pins, and the like are connected to the fifth terminal 30 on the third substrate 3 and the LSI socket 31. This can be dealt with almost simply by changing the mode, in other words, it can be dealt with by exchanging only the third substrate 3. Therefore, the additional test circuit that gives the LSI test board a desired function can be generally used for many types of devices under test DUT. (4) On the LSI test board, the frequency conversion circuits 28, 2
9. By mounting the PLL circuit 60, the output gate circuit 70, and the like, it is possible to test an LSI that requires a small number or some terminals of a signal having a signal frequency that can be supported by the tester by the tester.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes. For example, in the above embodiment, the first to third substrates are each rectangular, but the present invention is not limited to this, and a circular or circular concentric three-stage vertically stacked structure may be used if necessary. it can. Further, the additional circuit for the test includes the D / A converter DAC, the A / D converter ADC, the frequency conversion circuits 28 and 2.
9. The circuit is not limited to the PLL circuit 60 and the output gate circuit 70, and may be any circuit that changes the input signal format and outputs. Further, the LSI socket can be appropriately changed according to the package form of the device under test. Further, the device under test itself is not limited to the one described in the above embodiment.

In the above description, the case where the invention made by the present inventor is mainly applied to the test board for the analog / digital mixed LSI, which is the field of application in the background, has been described, but the present invention is not limited thereto. It goes without saying that the present invention can also be applied to a test board for a digital LSI instead of the above.

[0037]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) Since the three-stage vertically stacked structure of the first to third substrates is adopted as the structure of the LSI test board, the vertically stacked structure is used to connect the additional test circuit and the device under test. The signal wiring and the signal wiring for connecting the test additional circuit and the test head can be shortened, and deterioration of the reliability of the test due to the influence of noise can be minimized. (2) In the three-stage vertically stacked structure, the connection mode between the fifth terminal on the third substrate and the LSI socket is changed depending on the type of the device under test, the pin arrangement of the test device and the difference in the number of pins. It is possible to deal with this by simply replacing the third board, in other words, by replacing only the third board, which makes it possible to add an additional test circuit that gives the test board a desired function to many types of test. It can be used universally for devices. (3) By mounting the first and second frequency conversion circuits on the LSI test board, the tester can test the LSI that requires a small number or some terminals of a signal frequency higher than the signal frequency that the tester can support. Will be able to.

[Brief description of drawings]

FIG. 1 is a plan view of an LSI test board according to a first embodiment of the present invention.

FIG. 2 is a vertical sectional view showing a three-stage vertically stacked structure of an LSI test board.

FIG. 3 is a vertical cross-sectional view showing a terminal structure that is detachably connected.

FIG. 4 is a plan view showing an example of a third substrate for a device under test equipped with an A / D converter and a D / A converter as analog circuits.

FIG. 5 is a plan view showing an example of a third substrate for a device under test in which only an A / D converter is mounted as an analog circuit.

FIG. 6 is a plan view showing an example of a third substrate for a device under test in which only a D / A converter is mounted as an analog circuit.

FIG. 7 is an explanatory diagram showing an example of a conversion circuit as a test additional circuit mounted on a second substrate.

FIG. 8 is a plan view of an LSI test board having a three-stage vertically stacked structure in which a frequency conversion circuit is used as a test additional circuit as a second embodiment of the present invention.

FIG. 9 is a circuit diagram showing an LSI test board having a PLL circuit and an output gate circuit as a third embodiment of the present invention.

10 is a block diagram of an example of the device under test shown in FIG.

[Explanation of symbols]

 1 1st board | substrate 10 1st terminal 11 2nd terminal 2 2nd board | substrate 20 3rd terminal 21 4th terminal 22 D / A conversion circuit (additional circuit for a test) 23 A / D conversion circuit (test Additional circuit) 24 conversion circuit (additional circuit for test) 28 first frequency conversion circuit 29 second frequency conversion circuit 3 third substrate 30 fifth terminal 31 LSI socket DUT device under test 33 pattern wiring 4 test head 44 contact terminal 60 PLL circuit (first frequency conversion circuit) DIV programmable frequency divider 70 output gate circuit (second frequency conversion circuit) φ output latch strobe 101 first substrate 102 second substrate 103 third substrate

Front Page Continuation (72) Inventor Akihiko Hiraishi 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Semiconductor Company, Hitachi, Ltd. (72) Inventor Shigeru Takeuchi 5-20 Kamimizuhoncho, Kodaira-shi, Tokyo No. 1 Incorporated company Hitachi Ltd. Semiconductor Division (72) Inventor Shigemi Hirose 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Division

Claims (6)

[Claims] 1. A first substrate having a plurality of first terminals connected to contact terminals of a test head, and second terminals connected to the first terminals via predetermined wirings. A second terminal having a third terminal detachably connected to the second terminal of the first substrate and a plurality of fourth terminals connected to the third terminal through a predetermined wiring. Board, a plurality of fifth terminals removably connected to the fourth terminals of the second board, and an LSI socket connected to the fifth terminals through predetermined wiring. A third board, and the second board includes an additional test circuit for changing the format of the input signal and outputting the input signal between the predetermined third terminal and the predetermined fourth terminal. L characterized by being composed of
SI test board. 2. The D / A conversion circuit, wherein the additional test circuit converts digital information supplied from a predetermined third terminal into analog information and supplies the analog information to a predetermined fourth terminal,
A / D which converts analog information supplied from a predetermined fourth terminal into digital information and supplies the digital information to a predetermined third terminal
The LSI test board according to claim 1, further comprising a conversion circuit. 3. The test additional circuit includes a first frequency conversion circuit which raises a frequency of a clock signal supplied from a predetermined third terminal and supplies the clock signal to a predetermined fourth terminal, and a predetermined frequency conversion circuit. A second frequency conversion circuit that lowers the frequency of the signal supplied from the terminal 4 and supplies the signal to a predetermined third terminal;
The LSI test board according to claim 1, wherein the LSI test board comprises: 4. An LSI to which an LSI under test is mounted
In an LSI test board for interfacing a socket with a plurality of contact terminals of a test head, a first frequency conversion circuit for increasing the frequency of a clock signal supplied from a predetermined contact terminal of the test head and supplying it to the LSI socket, An LSI test board, comprising: a second frequency conversion circuit which lowers the frequency of a signal supplied from an LSI socket and supplies it to a predetermined contact terminal. 5. The LSI according to claim 4, wherein the first frequency conversion circuit is a phase locked loop circuit in which a frequency divider circuit is provided with a frequency divider.
Test board. 6. The second frequency conversion circuit directs a signal supplied from an LSI socket to a predetermined contact terminal in synchronization with a frequency of a timing signal supplied via a predetermined contact terminal of a test head. 5. The LSI test board according to claim 4, wherein the LSI test board is an output gate circuit for outputting the output.