JPH07111832B2 - Semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device integrated into a large scale integrated circuit, and more particularly to a dynamic random access memory (hereinafter referred to as dynamic RAM).

[0002]

2. Description of the Related Art First, a general arrangement of a dynamic RAM will be described with reference to FIG. In the figure,
MCA is a memory cell array, WL is a word line, BL is a bit line, SAA is a sense amplifier row, and word line WL
A plurality of bit lines BL and bit lines BL are provided in the memory cell array MCA depending on the memory capacity, but only one is shown here.

FIG. 3 shows an equivalent circuit of a conventional sense amplifier at the end portion of the sense amplifier array SAA surrounded by a, b, c and d in FIG. In the figure, SBL1,
/ SBL1 and / SBL2 are aluminum wirings in the sense amplifier row connected to the bit lines, 1 is an aluminum wiring for short-circuiting a cell plate of a memory cell (not shown), and QS1 and QS2 are insulated gate field effect transistors forming a sense amplifier. (Hereinafter referred to as FET), D1, G1 and S1 are the drain, gate and source of the FET QS1, D2, G2 and S2 are the drain, gate and source of the FET QS2, and 2 is an aluminum connected to the sense amplifier activation signal. Wiring, aluminum wiring SBL1,
/ SBL1 is connected to drains D1 and D2 of FETs forming a sense amplifier, and aluminum wiring 2 is connected to sources S1 and S2 thereof. BL1 and / BL1 are bit lines connected to the aluminum wirings SBL1 and / SBL1, respectively, and S is a sense amplifier activation signal. In addition, F in the figure
ET is an N-channel enhancement type. See also W
L1 and WL2 are word lines, and DWL1 and DWL
2 is a dummy word line. QC1, QC2 and CC
Reference numerals 1 and CC2 are FETs and capacitors that form a memory cell, and QD1 and QD2 and CD1 and CD2 are FETs and capacitors that form a dummy cell. Also, Q
R1 and QR2 are dummy cell discharge FETs, and a dummy cell reset signal RST is connected to each gate. The aluminum wirings SBL1 and / SBL1 have stray capacitances CS10 and CS20 with respect to the ground potential and a line capacitance CS12 between the aluminum wirings SBL1 and / SBL1.
Are electrically connected to each other, a line capacitance CS11 for the outer aluminum wiring 1 is connected to the aluminum wiring SBL1, and an adjacent aluminum wiring / SB is connected to the aluminum wiring / SBL1.
The line capacitance CS23 for L2 is connected.

Conventionally, in order to prevent a malfunction during a read operation of a dynamic RAM, a pair of bit lines B is formed.
Balancing the capacitances of L and / BL has been performed.

For example, Japanese Unexamined Patent Publication No. 58-111183 also considers balancing of capacitance associated with a pair of bit lines BL and / BL, and further, a dummy bit to which a memory cell and a sense amplifier are connected. The idea is to arrange the lines so that the capacitance associated with the outermost bit line of the memory cell array is made equal to the capacitance associated with the adjacent bit line.

However, as a result of various studies by the present inventor, in order to balance the capacitances associated with the paired bit lines BL and / BL, only the bit lines BL and / BL located in the memory array are balanced. It is not enough to consider it, and the aluminum wirings SBL1 and / S arranged in the sense amplifier row are arranged.
It has been found that if the capacitance associated with BL1 is not taken into consideration, an imbalance occurs in the capacitance associated with the bit lines BL and / BL as a result.

Regarding this point, for example, aluminum wiring SB
When the capacitance associated with L1 is larger than the capacitance associated with the aluminum wiring / SBL1 and as a result the capacitance associated with the bit line BL is larger than the bit line / BL, the operation of the dynamic RAM is performed as shown in FIG. When reading the stored contents of the capacitor CC1 of
The operation will be described with reference to FIG. 3 and FIG. 4 which is an operation waveform diagram of the aluminum wiring connected to the bit line and the bit line.

First, it is assumed that the storage content of the capacitor CC1 is "1". First, the dummy cell reset signal RST becomes "H", the FETs QR1 and QR2 are turned on, and the capacitors CD1 and CD2 are discharged. Further, the bit lines BL1 and / BL1 are precharged to "H" level by a precharge means (not shown). Next, after the dummy cell reset signal RST becomes "L",
At time t0, the word line WL1 and the dummy word line D
WL2 becomes "H" and the FETs QC1 and QD2 are turned on to connect the bit line BL1 and the aluminum wiring SBL1 to the capacitor CC1, the bit line / BL1 and the aluminum wiring / SBL1 to the capacitor CD2. By this operation, the electric charge stored in the stray capacitance CS10, the line capacitances CS11 and CS12 connected to the aluminum wiring SBL1, and the electric charge stored in the capacitor CC1 are averaged, and at the same time, the stray capacitance connected to the aluminum wiring / SBL1. The charges stored in CS20, the line capacitances CS23 and CS12, and the charges stored in the capacitor CD2 are averaged. At this time, the capacitances associated with the bit lines BL1 and / BL1 excluding the aluminum wirings SBL1 and / SBL1 are arranged so as to be substantially equal, so these capacitances are not considered here.

Generally, the capacitance of the capacitor CC1 of the memory cell is made larger than that of the capacitor CD2 of the dummy cell, and the stored content of the capacitor CC1 of the memory cell is "1", and the capacitor CD2 of the dummy cell is discharged and is similar to "0". Therefore, the potential of the bit line BL1 becomes higher than the potential of the bit line / BL1. At this time,
The total capacitance CBL connected to the bit line BL1 as described above
Since 1 is larger than the total capacitance / CBL1 connected to the bit line / BL1, the potential of the bit line BL1 precharged to the "H" level is not easily changed.

Next, at time t1, the sense amplifier drive signal S becomes "L" and the sense amplifier is activated. At this time, as described above, the bit line BL1, that is, FETQS.
The gate potential of 2 is the bit line / BL1, that is, FETQS1.
Since it is higher than the gate potential of
ETQS1 is turned off and bit line /
The potential of BL1 becomes even lower, and as a result, the bit line B
The memory content "1" of the capacitor CC1 of the memory cell is stored in L1.
Is read correctly.

Next, the read operation when the stored content of the capacitor CC1 of the memory cell is "0" will be described. In this case, the discharge of the capacitor of the dummy cell, the precharge of the bit line, and the operation of setting the word line and the dummy word line to "H" are performed in the same manner as in the above case.

Now, the bit line BL1 and the aluminum wiring SBL
1 and the capacitor CC1 are connected, and the bit line / BL1
When the aluminum wiring / SBL1 and the capacitor CD2 are connected, the stored content of the capacitor CC1 is "0", and the capacitor CD2 is also discharged and is in the same state as "0". Therefore, the bit line BL1 and the bit Line / BL1
The potentials of both become low. At this time, the capacitor CC1
Is larger than the capacity of the capacitor CD2, but as described above, CBL1> C / BL1 is provided between the capacity C / BL1 associated with the bit line / BL1 and the capacity CBL1 associated with the bit line BL1. If the difference is large, the potential of the bit line BL1 becomes higher than that of the bit line / BL1 as shown in FIG. 4 (b). Therefore, since the FET QS2 is turned on and the FET QS1 is turned off, the potential of the bit line BL1 does not become like the broken line in FIG. 4 (b), and conversely, the current of the bit line / BL1 becomes lower, and as a result, "1" is read from the bit line BL1 and a read error occurs.

[0013]

The conventional semiconductor memory device is configured as described above, and even if the capacitance associated with the bit lines in the memory cell array is balanced as described above, Since the capacitances associated with the wirings are not balanced, the capacitances associated with the bit lines are different, resulting in a read error.

The present invention has been made in view of the above problems, and by balancing the capacitances associated with the wirings connected to the bit lines in the sense amplifier, the error in reading the content of the memory cell is reduced. An object of the present invention is to provide a semiconductor memory device capable of suppressing the occurrence.

[0015]

A semiconductor memory device according to the present invention has a plurality of memory cells connected to each other.
The first and second bits arranged in parallel adjacent to each other
In addition to having multiple bit line pairs consisting of
Corresponding to a number of bit line pairs, each of which is the first
And a plurality of sense amplifiers having a second transistor
In the semiconductor memory device having, disposed side by side in the first and second along cormorants direction transistor on an extension line of the bit line pairs corresponding respective sense amplifiers, first and second sense amplifiers to both the gate electrode of the transistor extending in a direction along an extension of the corresponding bit line pairs are arranged, the first and second both the gate electrodes of the source region of the transistor of each sense amplifier is provided on the first side of the same side Te, provided on a second side of the same side with respect to the first and second both the gate electrodes and drain regions in the transistor in each sense amplifier, each electrically connecting the source region of the first and second transistors of the sense amplifier, the drain region and the second tiger of the first transistor of each sense amplifier The gate electrode of the register, the one bit line of the corresponding bit line pairs are electrically connected by a first wiring layer disposed on the first and on the second transistor, the first of the sense amplifier 2 of the drain region and the gate electrode of the first transistor of the transistor, the other bit line of the corresponding bit line pair, electricity by a second wiring layer disposed on the first and on the second transistor Each sense amplifier is configured by electrically connecting the two.

[0016]

According to the present invention, by configuring each sense amplifier included in the semiconductor memory device by the arrangement and connection as described above, the bit electrodes corresponding to the gate electrodes of the first and second transistors of each sense amplifier. They are arranged extending on an extension line pair along cormorants direction, yet its extended 2
The source of each transistor on one side of the two gate electrodes and the other side on the same side for each gate electrode
Located on a first side, with drains on each gate
Since they are arranged on the same side as the second side with respect to the electrodes, the capacitances associated with the respective wirings in the sense amplifier are made substantially uniform, and the occurrence of read errors is further suppressed.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing the structure of a semiconductor memory device according to an embodiment of the present invention, which shows a, b, and a at the ends of a sense amplifier array SAA of a dynamic RAM arranged as shown in FIG.
The portion surrounded by c and d is shown. In FIG. 1, S
BL1, / SBL1, ..., / SBL3 are respectively connected to bit lines, aluminum wiring in the sense amplifier, 3 is aluminum wiring for short-circuiting a cell plate of a memory cell (not shown),
, G6 are gates of FETs forming the sense amplifier, D1, ..., D6 are drains of FETs forming the sense amplifier, and S1, ..., S6 are F forming the sense amplifier.
Sources of ET, 2 are aluminum wirings commonly connecting the sources of FETs forming the sense amplifier to the sense amplifier activation signal, and aluminum wirings SBL1, / SBL1, ..., /
SBL3 is connected to the drain of the FET that constitutes the sense amplifier.

As is apparent from FIG. 1, two transistors forming each sense amplifier corresponding to each bit line pair, for example, a transistor including a gate G1, a source S1 and a drain D1 and a gate. G
The transistor composed of 2, the source S2, and the drain D2 is arranged along the extension line of the corresponding bit line pair.

In the dynamic RAM of this embodiment, as shown in FIG. 1, the intervals d1, d2, and d3 between the aluminum wirings in the sense amplifiers adjacent to each other with a certain repetition period are arranged to be equal in each sense amplifier. Further, the aluminum wiring SBL1 of the outermost sense amplifier of the sense amplifier array SAA and the aluminum wiring 3 arranged further outside thereof are arranged so that the distance between them is equal to d1, d2 and d3.

Further, as shown in FIG. 1, two FETs forming a sense amplifier connected to a pair of bit lines arranged in parallel with each other have gates in the same direction. As is clear from the figure, it is arranged so as to extend in the extension line direction of the aluminum wiring, and the drain and the source are arranged on the same side with respect to the gate.
That is, the pair of aluminum wirings SBL1 and / SBL
The drains D1 and D2 of the FET to which 1 is connected are both arranged on one side of the gates G1 and G2, that is, on the lower side in the drawing as is clear from the drawing in FIG.
Both S2 and S2 are arranged on the opposite side, that is, on the upper side in the drawing, as is apparent from the drawing in FIG. In addition, other pairs of aluminum wirings are similarly arranged. As a result, even if a mask shift occurs between the diffusion region shown by the broken line and the gate shown by the diagonal line in the manufacturing process,
Since the areas of the pair of aluminum wirings, for example, the drain regions connected to SBL1 and / SBL1, for example, D1 and D2 both increase and decrease, the areas are the same and the capacitance is not unbalanced.

Therefore, in the equivalent circuit diagram of the sense amplifier section shown in FIG. 3, the aluminum wiring SBL1 in the sense amplifier is used.
And / SBL1 have substantially the same capacitance, and thus the total capacitance CBL1 with bit line BL1 and the total capacitance C / BL1 with bit line / BL1 are substantially equal.

Next, the dynamic RAM according to this embodiment
3 will be described with reference to FIG. 3 and FIG. 5, which is an operation waveform diagram of the bit line, in the case of reading the stored contents of the capacitor CC1 of the memory cell of FIG.

Here, it is assumed that the stored content of the capacitor CC1 is "1". First, the dummy reset signal RS
T becomes "H", the FETs QR1 and QR2 are turned on to discharge the capacitors CD1 and CD2, and the bit lines BL1 and / BL1 are precharged to "H" level by a precharge means (not shown). Next, after the dummy cell reset signal RST becomes "L", time t0
, The word line WL1 and the dummy word line DWL2
Becomes "H", the FETs QC1 and QD2 are turned on, and the bit line BL1, the aluminum wiring SBL1 and the capacitor CC are
1 and the bit line / BL1 and aluminum wiring / SBL1 are connected to the capacitor CD2. By this operation, the stray capacitance C connected to the aluminum wiring SBL1
The charges stored in S10, the line capacitances CS11 and CS12, and the charges stored in the capacitor CC1 are averaged, and at the same time, stored in the floating capacitance CS20, the line capacitances CS23 and CS12 connected to the aluminum wiring / SBL1. The electric charge and the electric charge stored in the capacitor CD2 are averaged. At this time, the capacitances associated with the bit lines BL1 and / BL1 excluding the aluminum wirings SBL1 and / SBL1 are already arranged to be substantially equal, so these are not taken into consideration here.

Generally, the capacitance of the memory cell capacitor CC1 is made larger than that of the dummy cell capacitor CD2, the stored content of the memory cell capacitor CC1 is "1", and the dummy cell capacitor CD2 is discharged to "0". Since it is in the same state as
The potential of L1 becomes higher than the potential of bit line / BL1.

At time t1, the sense amplifier activation signal S becomes "L" and the sense amplifier is activated. At this time, as described above, the potential of the bit line BL1, that is, the FETQ
The gate potential of S2 is the potential of bit line / BL1, that is, FE
Since it is higher than the gate potential of TQS1, FETQS2 is turned on, FETQS1 is turned off, and the potential of bit line / BL1 is further lowered as shown in FIG.
The stored content "1" of the capacitor CC1 of the memory cell is correctly read out to "1".

Next, the read operation when the stored content of the capacitor CC1 of the memory cell is "0" will be described. In this case, the discharge of the capacitor of the dummy cell, the precharge of the bit line, and the operation of setting the word line and the dummy word line to "H" are performed in the same manner as above. Now, the bit line BL1 and the aluminum wiring SBL1 are connected to the capacitor CC1, and the bit line / BL1 and the aluminum wiring / SBL are connected.
1 and the capacitor CD2 are connected, the capacitor C
The memory content of C1 is "0", and the capacitor CD2
Is also discharged and is in the same state as "0", the potentials of the bit lines BL1 and / BL1 are both low.

At this time, the capacitance of the capacitor CC1 is made larger than that of the capacitor CD2, and the bit line BL1 and the bit line / BL1 are set as described above.
Since the capacitances associated with are almost equal, the potential of the bit line BL1 surely becomes lower than the potential of the bit line / BL1. Therefore, as shown in FIG. 5 (b), the potential of the bit line BL1 becomes lower than the potential of the bit line / BL1.
1 stores the content “0” of the capacitor CC1 of the memory cell
Is read normally.

In the above embodiment, the case where the bit line, the wiring inside the sense amplifier and the wiring outside the bit line are formed of aluminum has been described, but they may be formed of other materials. Has the same effect as.

Further, in the above-mentioned embodiment, the bit line and the wiring inside the sense amplifier and the wiring outside thereof are formed of the same material, but by appropriately selecting the position and side shape of the outside wiring, Only the wiring can be formed of a material different from that of the bit line and the wiring in the sense amplifier.

Although the FET is an N-channel FET in the above embodiment, it may be a P-channel FET, a complementary MISFET, or a bipolar transistor, and the same effect as that of the above embodiment can be obtained.

In the above embodiment, the dynamic RAM is used.
However, another memory such as a static RAM may be used, and the same effect as the above embodiment can be obtained.

[0032]

As described above, according to the semiconductor memory device of the present invention , a plurality of memory cells are connected to each.
And a first and a second arranged adjacent to each other in parallel
While having a plurality of bit line pairs consisting of
It is provided corresponding to these plural bit line pairs,
A plurality of senses having first and second transistors
In a semiconductor memory device including an amplifier , a bit corresponding to the first and second transistors of each sense amplifier
Arrange them side by side in the direction along the extension of the line pair, and
Gate voltage in the first and second transistors of the pump.
In the direction along the extension line of the corresponding bit line pair with both poles
The first and second transistors of each sense amplifier are arranged to extend.
The source area in the transistor is connected to each
It is provided on the same side as the first side
The first and second transistors of each sense amplifier
The drain region in each pair to the respective gate electrodes.
On the same side as the second side,
The source regions of the first and second transistors are electrically connected.
Connected to each other, and the first transistor of each sense amplifier is connected.
The rain region and the gate electrode of the second transistor,
The first and second bit lines of the corresponding bit line pair are
By the first wiring layer placed on the second transistor
Second transistor of each sense amplifier electrically connected
Drain region and gate electrode of the first transistor
To the other bit line of the corresponding bit line pair,
And a second wiring layer disposed on the second transistor.
Each sense amplifier is configured by electrically connecting
As a result, the capacitances associated with the respective bit lines are made more uniform, and it is possible to more completely suppress the occurrence of errors when reading the contents of the memory cells connected to the bit lines.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a layout diagram of a dynamic RAM.

FIG. 3 is an equivalent circuit diagram showing a connection between a memory cell and a sense amplifier.

FIG. 4 is a waveform diagram showing a part of the operation of the conventional dynamic RAM.

5 is a waveform chart showing a part of the operation of the apparatus of FIG.

[Explanation of symbols]

MCA memory cell array SAA sense amplifier column BL1, / BL1 bit line SBL1, / SBL1, ..., / SBL3 Wiring connected to bit line 3 Wiring CC1, CC2 Memory cell capacitors

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location 7735-4M H01L 27/10 681 G

Claims (1)

[Claims] 1. A are connected a plurality of memory cells each, and having a plurality of first and second consists of the bit line bit line pairs arranged in parallel adjacent to each other, the plurality of bit line pairs bit lines provided corresponding, respectively, which in a semiconductor memory device having a plurality of sense amplifiers having first and second transistors, first and second transistors of each sense amplifier corresponding to They are arranged in earthenware pots along on an extension line of paired direction, on an extension line of the bit line pair together corresponding gate electrode in the first and second transistors of each sense amplifier
They are arranged extending in a direction along, with is provided on the first side of the same side with respect to the first and the source region of the second transistor are both the gate electrodes of each of the sense amplifiers, each sense drain region in the first and second transistor amplifiers provided on the second side of the same side with respect to both the gate electrodes, the source of the first and second transistors of each sense amplifier The regions are electrically connected to each other and are connected to the drain region of the first transistor of each sense amplifier .
Good beauty gate electrode of the second transistor, to one of the bit lines of the corresponding bit line pairs are electrically connected by the first wiring layer disposed on the first and on the second transistor, each drain region of the second transistor of the sense amplifier
Good beauty gate electrode of the first transistor, the other bit line of the bit line pair corresponding, formed by electrically connected by a second wiring layer disposed on the first and on the second transistor A semiconductor memory device characterized by the above.