JPH07119916B2 - Thin film field effect transistor element array - Google Patents

Description

TECHNICAL FIELD The present invention relates to a thin film field effect transistor element array used particularly in an active matrix type liquid crystal display.

[Conventional technology]

Liquid crystal displays are drawing attention as flat panel displays for portable computers and wall-mounted televisions. Among them, the active matrix method, in which thin film field effect transistors formed into an array on a glass substrate and used as a switch for each pixel is capable of full color display, is expected to be applied to televisions, etc. Is being developed. In order to put this active matrix type liquid crystal display into practical use, cost reduction is an important issue, and as a countermeasure against it, there is simplification of structure and process. In the reverse staggered method in which the gate electrode of the thin film field effect transistor is formed on the glass substrate side with respect to the source and drain electrodes, there are a structure for etching the back channel part and a structure for placing a passivation film on the back channel part. The latter structure facilitates thinning of the semiconductor layer and prevents an increase in photo-off current. As a conventional technique for the thin film field effect transistor having the structure in which the passivation film is arranged, there is a manufacturing method using six masks.

FIGS. 3 (a) to 3 (j) are one step diagrams for forming a thin film field effect transistor element array based on the conventional method, and include (a), (c), (e), (g) and (I)
Is a plan view seen from above, (b), (d),
(F), (h) and (j) are (a), (c),
A-A ', BB', C- in (e), (g) and (i)
It is sectional drawing of C ', DD', and EE '. In FIG. 3, 1 is a glass substrate which is a translucent insulating substrate, and 2a
Is a chromium (Cr) gate electrode, and 4 is a drain electrode. 6b is a transparent pixel electrode composed of a transparent conductive film. Further, 7 is silicon nitride (SiN _X ), 8 is hydrogenated amorphous silicon (a-Si: H), and 9 is phosphorus-doped n-type hydrogenated amorphous silicon (n ⁺ -a-Si: H).
And 10 is a passivation film. The source electrode 14 arranged on the opposite side of the drain electrode 4 across the channel portion of the thin film field effect transistor 11 is a transparent pixel electrode 6b.
It is connected to the.

Chromium as a gate electrode and a drain electrode, SiN as the first insulating film to be used for the gate insulating film _X, the semiconductor film as _{a-Si: H, SiN X} , n -type semiconductor film as the second insulating film to be used for the passivation film Doped with phosphorus as n ⁺ −a
-Si: H, indium and tin oxide (In
A process of manufacturing a conventional thin film field effect transistor array using dium tin oxide (ITO) will be described with reference to FIG. First, a chromium film is formed on the glass substrate 1, and the chromium gate electrode 2a and the chromium gate bus line 3a are formed by the photolithography method using the first mask pattern (FIGS. 3A and 3B). . Then, SiN _X 7 as a first insulating film, a-Si: sequentially laminated passivation film 10 made of H 8, SiN _X. Then, the SiN _X for the passivation film 10 is subjected to a photolithography method using a second mask by a photolithography method to leave only the intersections on the gate electrode 2a and the chromium drain bus line 5a, and SiN _X for the passivation film 10 in other portions. Is removed (Fig. 3 (c),
(D)). Furthermore, after depositing n ⁺ -a-Si: H9, the third
A on the gate electrode 2a and at the intersection with the chromium drain bus line 5a by photolithography using the mask of
-Si: H8 and n ⁺ -a-Si: H9 are formed into islands (Fig. 3 (e),
(F)). Then, after depositing ITO, a transparent pixel electrode 6b is formed using a fourth mask (FIG. 3 (g),
(H)). Then, after forming the chromium film, the chromium is etched by the photolithography method using the fifth mask to form the chromium drain bus line 5a, the drain electrode 4, and the source electrode 14. Then, n ⁺ -a-Si: H is etched using the same resist pattern to remove the n-type amorphous silicon between the drain electrode 4 and the source electrode 14, and the channel part of the thin film field effect transistor 11 is removed. (Fig. 3 (i),
(J)). Finally, using the sixth mask pattern, SiN _X on the gate terminal around the thin film transistor array panel is used.
By removing 7, the thin film transistor array manufacturing process is completed.

Thus, in order to manufacture an inverted staggered thin film transistor array having a structure in which a passivation film is formed on the channel, at least 6 mask patterns are required.

[Problems to be Solved by the Invention]

Now, as the display size of the display increases and the definition increases, defects due to dust or the like in the photolithography process are likely to occur. Therefore, in order to increase the yield of the display and reduce the production cost, it is necessary to shorten the photolithography process as much as possible.

An object of the present invention is to provide a thin film field effect transistor element array capable of shortening the photolithography process from 6 times to 4 times and increasing the yield.

[Means for Solving the Problems]

According to the present invention, gate bus lines and drain bus lines are formed in a matrix on a translucent insulating substrate, and a thin film field effect transistor is formed near each intersection of the gate bus lines and the drain bus lines. , A thin film field effect transistor element array in which a pixel electrode is connected to each of the thin film field effect transistors,
A pixel electrode made of a transparent conductive film is formed on the insulating substrate, and an island-shaped gate electrode and the drain bus line are formed by a laminated film of the transparent conductive film and a first metal.
An island-shaped first insulating layer, a semiconductor layer and a second insulating layer are formed at each intersection of the thin film field effect transistor forming portion and the gate bus line and the drain bus line. The drain and source electrodes and the gate bus line of the thin film field effect transistor are formed by the above.

[Action]

According to the thin film field effect transistor element array of the present invention, it is possible to shorten the photolithography process in which defects are likely to occur.

[Embodiment] FIGS. 1 (a) to 1 (h) show a method of manufacturing a thin film field effect transistor element array having a structure according to the present invention.
It is a process drawing which shows an Example, (a), (c), (e) and (g) are the top views seen from the upper part, (b),
(D), (f) and (h) are (a),
A-A ', BB', C- in (c), (e) and (g)
It is sectional drawing of C ', DD'. In FIG. 1, 1 is a glass substrate which is a translucent insulating substrate, and 2a and 3a are chromium gate electrodes and chromium gate bus lines using chromium as a metal. And 5a is a chromium drain bus line also made of chromium. 7 is the first
Of silicon nitride (SiN _X ) as an insulating film, 8 is hydrogenated amorphous silicon (a-Si: H), 9 is phosphorus-doped n-type hydrogenated amorphous silicon (n ⁺ -a-Si: H), 10
Is a passivation film made of SiN _x which is the second insulating film. And 5b and 6b are made of ITO,
A transparent drain bus line and a transparent pixel electrode. Furthermore, 4 and 14 are a drain electrode and a source electrode, respectively. Reference numeral 11 is a thin film field effect transistor.

A method of manufacturing a thin film field effect transistor element array having the structure of the present invention will be described with reference to FIG. First, a 500 Å ITO film is formed on the glass substrate 1 by the sputtering method, then 1000 Å chromium is formed as the first metal, and the first mask pattern is used by the photolithography method.
A chrome gate electrode 2a, a transparent gate electrode 2b, a chrome drain bus line 5a, a transparent drain bus line 5b, a chrome pixel electrode 6a, and a transparent pixel electrode 6b are formed (FIG. 1 (a),
(B)). Specifically, the first mask pattern is formed with a photoresist, and chromium in a portion not covered with the photoresist is removed by a wet etching method. This chrome etching is Alternatively, a dry etching method using a may be used. Subsequently, ITO is wet-etched with the same resist pattern to remove the ITO not covered by the photoresist. Then, after etching, the photoresist is peeled off to complete the photolithography using the first mask pattern. The features of the mask pattern are that the chromium gate electrode 2a and the transparent gate electrode 2b are island-shaped and that the drain bus line is formed first. Next, plasma CVD (Chemical Vapor
The Deposition) _{method, SiN X 7, a-Si} : H8, the passivation film 10 formed in sequence consisting of SiN _X, stacked. In addition,
The film thicknesses of the SiN _X 7, the a-Si: H film 8 and the passivation film 10 are 3000Å, 500Å and 1000Å, respectively. And
SiN _X for passivation film 10 is removed by photolithography using a second mask, leaving only the gate electrode 2a and the intersection with the chrome gate bus line 3a, and removing the SiN _X for passivation film 10 in other portions. To do. (Figs. 3 (c) and (d)). Specifically, SiN _X is removed by a dry etching method. Furthermore, after depositing n ⁺ -a-Si: H 9 by photolithography using a third mask, SiN on the gate electrode 2a and at the intersection of the chromium gate bus line 3a and the chromium gate bus line 3a is formed. _X 7, a−Si: H8, n
⁺ −a−Si: H9 is formed into islands (FIGS. 3 (e) and (f). Specifically, the third mask pattern shape is formed by photoresist. And CF ₄ gas is used. Part of SiN _X 7, which is not covered by the resist by the dry etching method,
a-Si: H8 and n ⁺ a-Si: H9 are removed, and the photoresist is stripped. After that, a chromium film of 2000 Å is formed as the second metal by the sputtering method, and then the chromium gate bus line 3a, the drain electrode 4, and the source electrode 14 are formed by the photolithography method using the fourth mask pattern. 2a and the drain electrode 4 are connected to the chromium gate bus line 3a and the chromium drain bus line 5a, respectively. Specifically, a photoresist is used to form the shape of the fourth mask pattern, and the second metal, chromium, is removed from the resist-free portion by wet etching. Then, the etching is further advanced to remove the chromium pixel electrode 6a made of the first metal and the like, so that the transparent pixel electrode 6b and the like are exposed. Then, by etching the n ⁺ -a-Si: H9 using the same resist pattern,
The n ⁺ -a-Si: H between the drain electrode 4 and the source electrode 14 is removed to form the channel part of the thin film field effect transistor 11 (FIGS. 1 (g) and (h)). Finally, the photoresist is removed to complete the thin film field effect transistor element array.

As described in the manufacturing method above, in the thin film field effect transistor element array according to this embodiment, as shown in FIG. 1, the photolithography process required for manufacturing is shortened to four processes. In fact, the yield has increased by more than 20%.

Since the gate bus line 3a of the thin film transistor array according to the present invention is formed at the end of the manufacturing process, the film thickness can be increased. Therefore, since a low resistance gate bus line can be formed, propagation delay of a gate pulse can be prevented, and a larger area display can be realized. In the case of this embodiment, the drain bus line is partially ITO.
However, since the drain bus line is arranged in the vertical direction of the display, it is shorter than the gate bus line, and the capacitance of the thin film field effect transistor only needs to be considered on the drain electrode side. Propagation delay of signals due to wiring resistance and wiring capacitance is short (reference, 1985 Autumn Meeting of the Institute of Electronics, Information and Communication Engineers, Semiconductor and Materials Division, page 185). Therefore, it is possible to realize a larger display with a high yield, which does not deteriorate the display quality due to insufficient writing of the signal voltage.

In this embodiment, ITO is used as the transparent conductive film, but In ₂ O ₃ and SnO ₃ can also be used. Further, as the gate insulating film, SiO ₂ may be used instead of SiN _x . Further, it is possible to use other metals such as Ta, Al and Mo instead of chromium for the gate bus line and the drain bus line.

A plan view of another thin film field effect transistor element array according to the present invention is shown in FIG. In this case, the chrome gate electrode 2a made of the first metal and the transparent gate electrode 2b are also arranged below the chrome gate bus line 3a made of the second metal, thereby performing the multiple wiring of the gate bus lines. It realizes prevention of disconnection and lower wiring resistance. Also in the drain bus line, by extending the drain electrode 4 made of chromium, which is the second metal, onto the transparent drain bus line 5b, most of the drain bus line except the intersection of the gate bus lines is made of metal. It is formed from a thin film and has a low resistance and measures against disconnection by multiple wiring.

〔The invention's effect〕

As described above, according to the thin film field effect transistor array of the present invention, it is possible to form a thin film transistor array having a passivation film on the channel with four masks used and to reduce the resistance of the gate bus line. Therefore, it is possible to realize a larger display with a high yield without causing deterioration in display quality.

[Brief description of drawings]

1 (a) to 1 (h) are plan views and cross-sectional views illustrating a manufacturing process of an embodiment of a thin film field effect transistor element array according to the present invention, and FIG. 2 is a plan view of another embodiment,
3 (a) to 3 (j) are a plan view and a cross-sectional view illustrating a manufacturing process of a conventional thin film field effect transistor element array. In the figure, 1 ... glass substrate, 2a ... chrome gate electrode, 2b ... transparent gate electrode, 3a ... chrome gate bus line, 4 ...
Drain electrode, 5a ... Chromium drain bus line, 5b ...
… Transparent drain bus line, 6a …… Chromium pixel electrode, 6b
...... Transparent pixel electrode, 7 ... SiN _X , 8 ... a-Si: H, 9 ...
... n ⁺ -a-Si: H, 10 ... passivation film, 11 ... thin film field effect transistor, 14 ... source electrode.

Claims (1)

[Claims] 1. A plurality of parallel gate bus lines and a plurality of parallel drain bus lines are arranged so as to intersect with each other on a translucent insulating substrate, and the intersecting portions are formed in a matrix shape. In the thin film field effect transistor element array, wherein a thin film field effect transistor is formed near each intersection with the drain bus line, and a pixel electrode is connected to each of the thin film field effect transistor, the insulating substrate A pixel electrode made of a transparent conductive film is formed thereon, and an island-shaped gate electrode and the drain bus line are formed by a laminated film of the transparent conductive film and a first metal, and the thin film field effect transistor forming portion is formed. And an island-shaped first insulating layer, a semiconductor layer, and a second insulating layer at each intersection of the gate bus line and the drain bus line. Made is, first the second metal, the drain of the thin film field effect transistors, thin film field effect transistor array, characterized in that the source electrode, and the gate bus line is formed.