JPH07118685B2 - Package internal failure detection system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing system composed of a plurality of packages, and more particularly to a system having a function of detecting a failure in the package (called a package internal failure detection system).

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of a conventional package internal failure detection system. Referring to FIG. 3, in normal operation, this system provides a data signal in which M (M: any positive integer) channels of K (K: any positive integer) bits are multiplexed in one frame. , Between packages. The operation of this system at the time of failure detection (judgment) will be described below.

The package 310, which is the first package
On the side, the data signal SD1 input to the multiplexing circuit 311
Part of SD ₁ , SD1 _2, ... SD1 _N are input to the parity generators 314 ₁ , 314 _2, ... 314 _N. Parity generators 314 ₁ , 314 ₂ ... 314 _N are required by the control signals C1 ₁ , C1 ₂ ... C1 _N of the control circuit 313 for the respective data signals SD1 ₁ , SD1 ₂ ... SD1 _N. The part is subjected to parity counting and addition, and is output to the multiplexing circuit 311. In the multiplexing circuit 311,
Data signals SD1 ₁ , SD1 ₂ ... SD1 _N and counting result C
D ₁ , CD _2, ... CD _N are multiplexed to generate a data signal SD2
Is output. SD2 passes through speed conversion unit 312 and SD3
It is sent to the package 320 as ₁ .

On the other hand, on the side of the package 320 which is the second package, a part of each of the data signals SD3 ₁ , SD3 ₂ ... SD3 _L input to the multiplexing circuit 321 is a parity decision unit 324 ₁ , 324 ₂ ... 324 _L. Entered in. Parity determiners 324 ₁ , 324 _2, ... 324 _L are
The control signals C2 ₁ , C2 _2, ..., C2 _L of the control circuit 323 count the parity for each of the data signals SD3 ₁ , SD3 _2, ..., SD3 _L and determine the result.

In this system, the above operation causes a failure inside the package 310, that is, the data signal SD1 ₁
-Multiple circuit 311 and speed converter 3 for SD1 _N
A failure such as 12 is detected.

[0006]

The above-mentioned package 3
Parity is counted and added at the entrance of 10 (first package), and parity is counted (judged) at the entrance of the next package 320 (second package) to monitor the entrance to the exit of the package 310. With conventional package internal failure detection systems, including
For example, when the multiple rule changes depending on the usage mode of the package, it is necessary to change the parity detection range, which causes a problem that the configuration for detecting the internal failure becomes complicated.

Further, the fault detection method shown in FIG. 4 of Japanese Patent Laid-Open No. 1-280937 targets a single package, and in the case of providing a plurality of packages whose multiple rule changes depending on the usage mode of the package. Not considered.

An object of the present invention is to provide a package internal failure detection system capable of handling a plurality of packages having different multiple rules without complicating the circuit.

[0009]

According to the present invention, on the side of the first package to which a plurality of data signals are input in parallel, a pattern generator for generating a fixed pattern, the fixed pattern and the plurality of data are provided. The signal and the channel selected from among these are multiplexed, and M (M is a natural number) in one frame.
A first multiplex circuit for generating a multiplex signal including a plurality of channels, the second package being a package next to the first package, wherein a plurality of data signals including the multiplex signal are input. The package side includes a second multiplexing circuit that multiplexes channels selected from a plurality of data signals to generate a multiplexed signal of M channels in one frame, and an output of the second multiplexing circuit. And a pattern determiner for determining the fixed pattern, the first and the second
Has a control circuit that controls the multiplex circuit in common, and the control circuit changes the multiplex rule in common to check the data from the input to the output of the package with the pattern determiner to detect the internal failure of the package. A package internal failure detection system characterized by the above is obtained.

According to the present invention, further, in the normal operation, the first multiplexing circuit includes data in which M channels are multiplexed in one frame and the fixed pattern is multiplexed in a predetermined channel. A signal is output, and at the time of failure determination, multiplexing is performed by interchanging with the channel for which the multiplexing position of the fixed pattern is to be determined, and the second multiplex circuit, at the time of failure determination, The package internal failure detection system is characterized in that the fixed pattern exchanged by the first multiplexing circuit and the multiplexing position of the channel to be determined are multiplexed so as to be restored. .

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A package internal failure detection system according to an embodiment of the present invention will be described below with reference to the drawings.

As in the conventional example, this system also has M (M: any positive integer) channels of K (K: any positive integer) bits multiplexed in one frame during normal operation. The data signal is transmitted between the packages.

FIG. 1 is a block diagram showing a package internal failure detection system according to this embodiment. In FIG. 1, the present system includes a package 10 that is a first package to which a plurality of data signals are input in parallel, and a plurality of packages that are a package next to the package 10 (a second package) and that include multiple signals. 20 to which the data signal of
And a control circuit 30 connected to both.

On the package 10 side, a pattern generator (PG) 14 for generating a fixed pattern and a channel selected from the fixed pattern and a plurality of data signals are multiplexed, and M (M is a natural number) is set in one frame. ) A multiplexing circuit 11 for generating a multiplexed signal including a plurality of channels and a speed conversion unit 12 for converting the bit rate of the data signal are provided.

On the package 20 side, channels selected from a plurality of data signals are multiplexed and M frames are transmitted in one frame.
(M is a natural number) A multiplexing circuit 21 for generating multiplexed signals of channels, a pattern determiner (PD) 24 for determining a fixed pattern included in the output of the multiplexing circuit 21, and a predetermined pattern for an input data signal. And a circuit unit 22 for performing the processing of.

The control circuit 30 controls the multiplexing circuits 11 and 21 in common.

Next, the operation of the system during normal operation and failure detection (judgment) will be described.

FIG. 2 is a timing chart of data signals for explaining the operation of this system. Referring to FIG. 1 and FIG. 2 together, first, the operation of the present system during normal operation will be described.

On the package 10 side, of the data signals SD1 ₁ , SD1 ₂ ... SD1 _N , for example, the data channel "1" is selected from the package input signal SD1 _1.
Then, the data channel "2" from the package input signal SD1 ₂ and the fixed pattern CD generated by the pattern generator 14 are input to the multiplexing circuit 11, and these are multiplexed to output the data signal SD2. Data signal SD2
Is packaged as SD3 ₁ via the speed conversion unit 12
Sent to 0.

Subsequently, on the package 20 side, the multiplexing circuit 21 causes the package input signals SD3 ₁ , SD3 _2, ... SD by the control signal C20 output from the control circuit 30.
Of 3 _N, for example, data channels "1, 2, CD" from the package input signal SD3 ₁ and, multiplexed data signal by selecting a data channel "3,4" from the package input signal SD3 ₂ SD4 To generate. Then, the data signal SD4 is input to the circuit unit 22 and subjected to predetermined processing. Further, the pattern determiner 24 extracts the fixed pattern CD from the data signal SD4.

In this embodiment, the fixed pattern CD is generated by the pattern generator 14 and the fixed pattern CD is taken out by the pattern judging unit 24 during the above-mentioned normal operation. This is a normal data signal processing. Needless to say, it does not hinder the operation of the system.

Next, the operation at the time of package failure detection (judgment) is performed as follows.

Referring to FIGS. 1 and 2 together, for example, the leftmost channel of SD2, that is, SD1 ₁
When the data of (1) is determined, the multiplexing signal is multiplexed by the multiplexing circuit 11 on the package 10 side by the control signal C1 ′ output from the control circuit 30 to generate the data signal SD2 ′. This data signal SD2 'is a data channel "1".
And the fixed pattern CD are replaced with each other. Then, the data signal SD2 'undergoes a speed converting section 12, SD3 _1' is delivered to the package 20 as.

On the package 20 side, the control circuit C2 'output from the control circuit 30 causes the multiplexing circuit 21 to select the data channels "CD, 2, 1" and the package input signal SD3 ₂ from the package input signal SD3 ₁ '. The data channels “3, 4” are selected from among these to generate the multiplexed data signal SD4. The data signal SD4 has the same channel order as that in the normal operation, but this does not make the system configuration complicated due to a large difference in processing between the normal time and the failure detection. This is the operation set for this purpose.

Further, the fixed pattern CD is taken out from the data signal SD4, and the pattern judging device 24 judges the data.

If the result of this determination is "normal", then the second channel from the left in the figure of SD2, that is, S
The same operation is performed by exchanging the data channel "2" of D1 ₂ and the fixed pattern CD, and the error determination of the data signal is performed for all the data channels in one frame.

As described above, the internal failure of the package could be detected.

It goes without saying that the multiplex circuit in the package internal failure detection system according to this embodiment is composed of a known multiplex circuit.

[0029]

The package internal failure detection system according to the present invention can be applied to a plurality of packages having different multiplexing rules despite a relatively simple circuit configuration. Specifically, a package internal failure (mainly internal memory monitoring) detection circuit of an interface card or the like can be simply configured.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a package internal failure detection system according to an exemplary embodiment of the present invention.

2 is a timing chart of a data signal for explaining the operation of the system shown in FIG.

FIG. 3 is a block diagram showing a conventional package internal failure detection system.

[Explanation of symbols]

10, 20 Package 11, 21 Multiplexed circuit 12 Speed converter 14 Pattern generator 22 Circuit part 24 Pattern determiner 30 Control circuit SD1 ₁ , SD1 ₂ ... SD1 _N data signal SD2 data signal SD3 ₁ , SD3 ₂ ... SD3 _L data signal SD4 data signal CD fixed pattern

Claims (2)

[Claims] 1. A pattern generator for generating a fixed pattern, and a channel selected from the fixed pattern and the plurality of data signals, on the side of the first package into which a plurality of data signals are input in parallel. And a first multiplex circuit for generating a multiplex signal including M (M is a natural number) channels in one frame, and is a package next to the first package. A second package for inputting a plurality of data signals including the second channel that multiplexes channels selected from the plurality of data signals and generates a multiplexed signal of M channels in one frame. A circuit and a pattern determiner that determines the fixed pattern included in the output of the second multiplex circuit, and a control circuit that commonly controls the first and second multiplex circuits, control A package internal failure detection system characterized in that data from an input to an output of a package is checked by the pattern determiner to detect an internal failure of the package by commonly changing a multiple rule in a circuit. 2. The first multiplexing circuit outputs a data signal in which M channels are multiplexed in one frame and the fixed pattern is multiplexed in a predetermined channel in a normal operation, When a failure is determined, multiplexing is performed by interchanging with the channel for which the fixed position of the fixed pattern is to be determined.
In the case of the failure determination, the multiplex circuit of (1) multiplexes so that the fixed pattern replaced by the first multiplex circuit and the multiplex position of the channel to be determined are restored. The package internal failure detection system according to claim 1.