JPH07118628B2 - signal processing device - Google Patents

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a PCM codec and a DSP (Digital Signal Processor)
r) and performs coding/decoding of digital PCM signals and other signal processing,
More specifically, this paper relates to technology that enables practical signal processing within a DSP through highly accurate A/D and D/A conversion, and technology for clock transfer of output signals that is required as a result of synchronizing the signal processing realized thereby with the same clock.

BACKGROUND ART A signal processing device is a device that performs encoding/decoding and other processing of digital PCM signals and the like.

Typical examples of such converters include an A/D converter that encodes an analog telephone band signal on a subscriber line and a digital PCM signal on a trunk line, and a D/A converter that decodes the signal.

Generally, when an analog signal is converted to a digital signal at the transmitting end, the analog signal is first sampled at a fixed interval, and each sampled signal is then quantized. Quantization is an operation in which the amplitude level of the analog signal is divided into multiple ranges in advance, and all analog signals within a certain range are represented by a single corresponding digital representative value. The resulting quantized signal is then coded and converted into a digital signal.
The digital PCM signal is transmitted over the transmission line as a PCM signal. At the receiving end, the digital PCM signal is converted back into an analog signal and reproduced as a telephone signal such as voice.

As mentioned above, during the quantization process, there is a range of analog signals in which the same code can be expressed even if the sampled values fluctuate to some extent, and at the receiving end, all sampled values within this range are decoded as analog signals of the same amplitude. Therefore, an inherent error occurs between the analog signal before encoding and the analog signal after decoding. This error is called quantization noise.

Here, the signal-to-quantization noise ratio (S/N) is used as a measure of the quality of a communication signal. The range represented by the same code above is called the quantization step, and if this quantization step is uniform, the quantization noise will be constant. Therefore, if the amplitude of the signal, i.e., the analog input, is large, the S/N ratio will be
However, in order to improve communication quality, regardless of the amplitude of the above,
It is desirable to keep the S/N ratio constant. Therefore, for analog inputs with small amplitudes, the quantization step is made smaller,
Non-linear quantization is generally employed, in which the quantization step is increased for analog inputs with large amplitudes.
For telephone signals, the companding law known as μ-law is used as the companding characteristic of the nonlinear quantization described above in Japan and the United States, while the companding law known as A-law is used in other regions, primarily Europe.

In recent years, 8-bit companding A/D converters and D/A converters that perform signal conversion based on the above companding law have become available from many manufacturers at fairly low cost, despite their complex configuration. These ICs are commonly known as PCM CODECs (PCM coder/decoders).

On the other hand, when transmitting data other than voice signals using telephone band signals, signal processing circuits that are often used in combination with converters such as the PCM CODEC mentioned above include equalizers, attenuators,
These circuits have traditionally been configured as analog circuits, placed before the A/D converter on the encoding side and after the D/A converter on the decoding side.

FIG. 1 shows a conventional example of a digital PCM channel device realized as a combination of the above circuits and a PCM codec.

First, the PCM CODEC 1 has a low-pass filter (LPF) 7 and
An A/D conversion unit consisting of an A/D converter 8, a D/A converter 10, and an LPF
The A/D converter 8 and the D/A converter 10 perform data conversion based on the 8-bit μ-law companding described above. The LPFs 7 and 11 also provide a band that can express the frequency band of the analog signals, which are the input and output signals, in terms of the sampling frequency, i.e., half the sampling frequency.
This is a low-pass filter that limits the frequency band up to 100 kHz. In this way, the PCM CODEC1 also integrates the low-pass filter into a chip, which ultimately makes it possible to reduce the cost of the encoding/decoding section.

The hybrid transformer 3 separates the analog telephone band signal (analog data) transmitted on the two-wire subscriber line 2 into a transmission signal and a reception signal. The equalizers 4 and 13 correct the loss of the signal frequency characteristics in the two-wire subscriber line 2 or the four-wire transmission line 9 within the telephone band. The attenuators 6 and 12 correct the loss of the signal level that occurs depending on the line. Balanced circuit
15 adjusts the impedance of the hybrid transformer 3 in order to attenuate echoes (echoes) of signals from the receiving side to the transmitting side, which are caused by impedance mismatch in the hybrid transformer 3.
and 14 adjust the signal level. The settings and control of the above circuits are electrically controlled by remote control from a center (station) (not shown), as indicated by the dashed lines in the figure. This control is generally called remote provisioning.

Here, the circuits 4, 6, 12, 13, and 15 are important circuits necessary for improving communication quality. However, if each of the circuits is configured with an analog circuit as shown in Figure 1, the circuit scale becomes large, increasing the cost of the entire device. Furthermore, there is a problem in that the remote provisioning required for setting each of the analog circuits becomes complicated.

Meanwhile, DSPs (Digital Signal Processors) have begun to be widely used in various fields, and DSP LSIs are becoming available at low cost. DSP processing performance is improving year by year, and more and more parts that were previously processed analogue are now being processed by DSPs. This is because DSP processing allows the hardware scale of devices to be reduced. Also, by using DSPs, the effects of product variations that occur during the manufacturing process, which have a significant impact on analogue circuits, can be minimised. Furthermore, processing operations can be easily changed by simply changing the built-in firmware. Based on this technology, in fields such as telephone band signal processing,
Conventional analog processing is being replaced one after another by DSPs. In other words, there is a growing demand to replace the aforementioned equalizers, attenuators, balancing circuits, and other circuit components with DSPs.

Figure 2 shows the general configuration of a digital PCM channel device, assuming that the processing by each of the above circuits is performed by a DSP. In this figure, parts with the same numbers as in Figure 1 have the same functions. As shown in this figure, DSP1
6 is provided on the digital signal side of the PCM CODEC 1. The same function as the impedance control of the hybrid transformer 3 performed by the balancing circuit 15 in FIG. 1 is realized by the DSP 16. Therefore, the impedance of the hybrid transformer 3 is controlled by the second
As conceptually shown by the resistance R in the figure, the impedance is fixed at a constant value, allowing signal leakage to occur. Coarse attenuators 17 and 18 are circuits that roughly adjust the analog signal level in increments of, for example, 3 dB, and have a pre-processing nature.

As shown in FIG. 2, it is desirable that the DSP 16 be combined with a PCM CODEC 1, which is currently available at low cost.
However, in reality, it is not possible to realize a coding/decoding device with the desired performance by simply combining signals in this way. This is due to the S/N ratio mentioned above. The μ-law companding in PCM CODEC is a code conversion rule that is established on the premise that the digital signal coded on the transmitting side is sent directly to the receiving side through a transmission line, where it is decoded according to the same companding rule as on the transmitting side.
Therefore, when DSP processing is performed on a digital signal after A/D conversion, quantization noise, which originally only occurred during encoding, also occurs during decoding. Therefore, in order to improve communication quality, it is necessary to increase the number of quantization bits as much as possible, make each quantization step as small as possible, and minimize quantization noise. However,
Currently, most PCM codecs in circulation use 8-bit quantization, which does not have very high quantization accuracy. Therefore, simply combining commercially available PCM codecs will result in the following:
This poses a problem in that the S/N ratio of the communication signal is inevitably degraded.

To address the problem of the deterioration of the S/N ratio, it is possible to use converters corresponding to the A/D converter 8 and D/A converter 10 in Fig. 2, which have a smaller quantization step than the 8-bit quantizer used in the PCM CODEC, and which can maintain the same step size even up to a high level. For example, a linear converter that performs 16-bit linear quantization can be used. Depending on the level of signal processing performed by the DSP, a linear converter of about 15 bits may be sufficient, but a PCM CODEC based on the above-mentioned 8-bit μ-law companding may be used.
Considering that the DEC has the same resolution as a 14-bit linear converter in the low signal level range, it is still 16
A resolution of about 1/4 bits is required.

However, A/D and D with high resolution of 15 or 16 bits
The circuitry of the A/D converter is more complex and larger than that of commercially available PCM CODECs.
and D/A converters have the problem of being extremely disadvantageous in terms of cost. Furthermore, while PCM codecs have built-in low-pass filters, the high-resolution linear converters mentioned above do not have such filters. Therefore, a new low-pass filter must be installed, which increases costs and also increases the chip area.

Next, we will discuss general techniques that can be considered when a digital PCM channel unit is configured by combining A/D and D/A converters with a DSP, as in Figure 2 above, and the DSP performs processing similar to that of the equalizer, attenuator, and balancing circuit described above.

FIG. 3 shows again an example of a general configuration that can be considered as a digital PCM channel device based on the above configuration.

In the figure, a hybrid transformer 21, an A/D converter 23
The D/A converter 24 has the same functions as those shown by numbers 3, 8 and 10 in Fig. 2, respectively. As in Fig. 2, the impedance of the hybrid transformer 21 is kept constant. The two-wire subscriber line 20 and the four-wire transmission line 30 are also the same as those shown by numbers 2 and 9 in Fig. 2. The pre-processing circuit 22 also has the same functions as those shown by numbers 2 and 9 in Fig. 2, the amplifier 5, the coarse attenuator 17 and the LPF 7 in Fig. 2.
2, and the post-processing circuit 25 is a combination of the LPF 11, coarse attenuator 18, and amplifier 14 of Fig. 2. Although not shown in Fig. 2, the pre-processing circuit 22 may also perform processing such as emphasizing high frequency components of the analog signal in order to improve the quality of the communication signal. Conversely, the post-processing circuit 25 may also perform processing such as restoring the signal characteristics that were emphasized on the transmitting side.

3, an input signal SIN converted into digital data by an A/D converter 23 and a received PCM signal RIN from a four-wire transmission line 30 are input to a DSP 19. In the DSP 19, a transmission level setting/equalizer 27 and a reception level setting/equalizer 28 are connected to the DSP 19.
are realized as firmware and perform the same processing operations as the equalizers 4 and 13 and attenuators 6 and 12 in Fig. 1. That is, for the input signal SIN and the received PCM signal RIN, the loss of the signal frequency characteristics in the two-wire subscriber line 20 or the four-wire transmission line 30 is precisely corrected within the telephone band, and the loss of the signal level that occurs depending on the line is also precisely corrected.

At this time, part of the signal going from the post-processing circuit 25 to the subscriber line 20 sneaks in via the hybrid transformer 21, is included in the input signal SIN and input to the DSP 19, and so it is necessary to cancel out part of this signal. For this purpose, the precision balancing circuit 29 generates the above-mentioned component from the received output signal ROUT, and this is added (actually subtracted) to the input signal SIN by the adder 26, thereby canceling out the above-mentioned component.

This processing involves finding the difference between a processed reception output signal ROUT, which is a reception system signal, and an input signal SIN, which is a transmission system signal, and is processing that spans both the reception system and the transmission system.

Here, the digital transmission system including the digital PCM channel device of FIG. 3 has a transmission speed of, for example, 64 Kbit/sec and operates in synchronization with an 8 KHz clock.
In the figure, unless it is a completely cascaded synchronous network, D/A converter 2
The receiving circuits such as the A/D converter 24 operate in synchronization with the receiving clock extracted from the received PCM signal RIN, and the transmitting circuits such as the A/D converter 23 operate in synchronization with the transmitting clock generated in a channel device (not shown). In this case, the receiving clock is a divided clock from the master clock of the remote terminal station, and the transmitting clock is a divided clock from the master clock of the local station. Therefore, the frequencies of both are nominally 8K.
Hz, but they do not use the same master clock,
In reality, the frequencies differ slightly, with the maximum difference being 10 ^-4
It will be about that level.

A difference of 10 ^-4 means that, for example, when data is input 10,000 times in the transmission system, the number of pieces of data in the reception system will be 10,001.

This results in a slight difference in the sampling timing of the received PCM signal RIN and the input signal SIN input to the DSP 19. Therefore, even if the adder 26 attempts to cancel out the received signal component contained in the input signal SIN using the output of the precision balancing circuit 29, which receives the received PCM signal RIN as its input, the expected result cannot be obtained because signals at different times are added.

Moreover, when there is a deviation of 10 ^-4 with an 8KHz clock, the
Once per second, data overtaking occurs, causing the data at that point to be lost.

This requires that one clock be synchronized with the other clock. In this case, the received PCM signal RIN is a signal that has already been sampled on the transmitting side, and the receiving clock has already been generated on the transmitting side, so the receiving clock is required to receive the received PCM signal RIN. Therefore, the receiving clock is used as the transmitting clock.

However, the received PCM signal RIN passes through many repeaters from the source terminal, and each repeater adds a little jitter, so it already contains a large amount of jitter. Therefore, if this signal is used as a transmission clock, it will pass through many repeaters before reaching the destination terminal, and the jitter will increase further, significantly degrading communication quality. As a result, if we try to ensure the same communication quality as when clock generators are installed at both ends and these are operated in precise synchronization, the distance to which jitter is added will be twice the distance for a round trip, i.e., the one-way distance, and the repeater distance will be limited to half.

In the echo canceller, the signal going to the subscriber is routed through the hybrid transformer 21, but the echo contained in the transmission signal is cancelled out by adaptively generating a pseudo echo based on the received signal and subtracting it from the transmission signal, so processing is performed on both the transmission signal and the reception signal, and the same problems as those described above arise.

To solve the above problems, a digital signal clock transfer system is required in which the digital PCM channel device shown in FIG. 3 operates the D/A converter 24, A/D converter 23, precision balancing circuit 29, etc. in synchronization with the receiving clock, and the resulting transmit signal is resynchronized with the transmit clock generated by the clock generator of the local station and output as the output signal SOUT.

In this case, it is desirable that the communication quality is good and that it can be made compact.

4 is a block diagram of a conventional clock transfer system. In the figure, the first clock system digital data 34 is
The digital signal is converted into analog data by a D/A converter 31 that operates on a first clock 35, and then passed through an analog low-pass filter 32.
The output of the filter 32 is converted into time-continuous data and then input to an A/D converter 33 that operates on a second clock 36.
Then, the clock signal is converted into the second clock system digital data 37, and clock transfer is performed.

However, in the device of FIG. 4, the input digital data is converted back to analog data by the D/A converter 31, and this data is
Since the signal is converted back into digital data by the digital/digital converter 33, quantization noise occurs, resulting in a decrease in communication quality.
The analog low-pass filter 32 is required, and even if it is integrated like a digital circuit, it cannot be made compact.

DISCLOSURE OF THE INVENTION The present invention has been made in view of the above circumstances, and
Low-cost PCM CODEC and DSP (Digit
High-precision A/D
The first objective is to realize practical signal processing within a DSP by enabling digital to analog and digital to analog conversion. The second objective is to enable clock transfer of output signals, which is necessary as a result of synchronizing the signal processing with the same clock so that it can be performed without any inconsistencies on the transmitting and receiving sides, while keeping the signal digital.

In order to achieve the above object of the present invention, first, an analog input signal is subjected to a first and a second shift in amplitude value.
The A/D conversion means converts the signals individually in the A/D conversion systems and calculates the average of the respective conversion results to obtain a digital output signal with higher conversion accuracy than when the A/D conversion system is a single system. The first A/D conversion system of the means is, for example, the first amplifier 38, the first companding A/D converter 39, and the first linear converter 42 in Fig. 5, and the second A/D conversion system is, for example, the second amplifier 38, the first companding A/D converter 39, and the first linear converter 42 in Fig. 5.
amplifier 40, second companding A/D converter 41, second linear conversion unit 43
The calculation of the average value is carried out, for example, by the calculation unit 44 shown in FIG.

Next, the digital input signal is converted separately by first and second D/A conversion systems, and a quantization error occurring before conversion by the first D/A conversion system is detected and added to the digital input signal to the second D/A conversion system.
The D/A conversion means mixes the results of the conversions of the conversion systems at a predetermined ratio to obtain an analog output signal with higher conversion accuracy than when the D/A conversion system is a single system.
The D/A conversion system is, for example, the first companding unit 45 and the first companding D/A converter 49 in FIG. 6, and the second D/A conversion system is, for example, the second companding unit 46 and the second companding D/A converter 50 in FIG.
The quantization error from the first D/A conversion system is detected, for example, by a detector 47 in FIG. 6, and added to the input to the second D/A conversion system by a noise adder 48. The conversion results from the first and second D/A conversion systems are then mixed at a predetermined ratio by, for example, first and second amplifiers 51 and 52 and an adder 53 in FIG. 6.

The digital signal/clock transfer means also includes a digital signal/clock transfer means for upsampling the first digital data sequence, detecting the timing difference between the first clock and the second clock, and generating second digital data synchronized with the second clock by interpolation from the upsampling data based on the timing difference. In this means, the means for upsampling the first digital data sequence is, for example, the data conversion circuit 63 and the upsampling digital low-pass filter 64 shown in FIG. 13A. The means for detecting the timing difference between the first clock and the second clock is, for example, the timing difference detection circuit 66 shown in FIG. 13A. This means may be disclosed as a circuit shown in, for example, FIGS. 19, 24, and 25. Additionally, the means for performing the interpolation process may be, for example, the digital signal/clock transfer means shown in FIG. 13A.
This is the interpolation processing unit 65 in the figure, and is specifically disclosed as the processing in Figs. 18 and 26, etc.

In addition, the high sampling digital low-pass filter 64 mentioned above
13B as an invention configured with a plurality of blocks, and FIG. 28 as an output timing adjustment circuit related to the timing difference detection circuit 66, etc. are disclosed.

The above-mentioned invention may be configured, for example, as an encoding/decoding device for digital PCM signals, by using two PCM CODECs and one
The A/D conversion means and the D/A conversion means are implemented by two PCs that perform 8-bit companding, encoding, and decoding.
This can be achieved using the M-CODEC and some of the functions of one DSP.
The digital signal clock transfer means is the DSP (Digital Signal Processor)
This can be achieved using the functions of the Digital Signal Processor.

Therefore, highly accurate A/D and D/A conversion can be achieved with an inexpensive and compact configuration consisting of two PCM CODECs and one DSP. This allows signal processing functions, such as attenuators, equalizers, and balancing networks, which were previously implemented using analog circuits, to be implemented using digital signal processing in a single DSP. In this case, to prevent timing discrepancies between signals processed on the transmitting and receiving sides, the signal processing is performed, for example, in synchronization with the receive clock of a digital receive signal received from an external line. Therefore, on the transmitting side, it becomes necessary to resynchronize the digital output signal for transmission, which is synchronized with the receive clock, with the transmit clock. This process is easily achieved using digital signal clock transfer means implemented within the DSP.

As described above, according to the present invention, an inexpensive PCM CODEC and
By using a signal processing device that combines DSP etc., high precision A/D
This makes it possible to easily realize D/A conversion, which previously required large-scale analog circuits, and it is now possible to easily perform signal processing with a single DSP. Furthermore, the clock transfer means for digital signals required in this case is also
It can be realized as digital signal processing within the same DSP. In this case, the present invention realizes the timing difference detection means within the digital signal clock transfer means with extremely simple circuits and processing.

Therefore, for example, by integrating the device while maintaining high communication quality, the entire device can be made very small, and a signal processing device that is low in cost, low in power consumption, and highly reliable can be put into practical use.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a conventional example of a digital PCM channel device; FIG. 2 is a diagram showing a general configuration of a digital PCM channel device; FIG. 3 is a diagram showing another general configuration of a digital PCM channel device; FIG. 4 is a block diagram of a conventional example of a clock transfer device; FIG. 5 is a basic block diagram of an A/D conversion device according to the first embodiment; FIG. 6 is a basic block diagram of a D/A conversion device according to the first embodiment; FIG. 7 is a diagram showing the correspondence of each numerical value under general μ-law; 14A, 14B and 14C are time charts of waveforms of each part of the second embodiment; FIG. 15 is a block diagram of a data conversion circuit; FIG. 16 is a block diagram of a high sampling digital low pass filter; FIG. 17 is a diagram showing the attenuation of the filter of FIG. 16; FIG. 18 is a flowchart of the operation of the interpolation processing unit; FIG. 19 is a block diagram of a timing difference detection circuit; 27A and 27B are operation timing charts of the fourth embodiment, FIG. 28 is a configuration diagram of an output timing adjustment circuit according to the fourth embodiment, and FIG. 29 is an operation timing chart of the output timing adjustment circuit.

First Embodiment First, the first embodiment will be described. In this embodiment, two PCM codecs based on 8-bit μ-law companding are used to
It is characterized by improving the accuracy of D/A and D/A conversion.

5 is a diagram showing the basic configuration of an A/D conversion device according to a first embodiment of the present invention. In the figure, an analog signal A _in is applied in common to a first A/D conversion system and a second A/D conversion system.
In the first A/D conversion system, the signal A _in is amplified by a factor of k1 in the first amplifier 38 and then converted into a first PCM code P1 in the first companding A/D converter 39. In the second A/D conversion system, the signal A _in is amplified by a factor of k1 in the second amplifier 40.
The signal is amplified by two times and then converted into a second PCM code by a second companding A/D converter 41.
P2, where k1 and k2 are real numbers that satisfy k1 × k2 = 1.

Meanwhile, the DSP is provided with at least a first linear conversion unit 42, a second linear conversion unit 43, and an arithmetic unit 44. The first and second linear conversion units 42 and 43 convert the first and second PCM signals, respectively.
The codes P1 and P2 are converted into first and second linear codes L1 and L2. The average value (L1+L2)/2 of these linear codes L1 and L2 is calculated by the calculation unit 44, and this average value becomes the digital conversion output Dout. Then, the first linear code L1 and the second linear code L2 are _{converted into} the digital conversion output Dout.
As will be described later in Figure 12, processing is performed based on the functions of the precision balancing circuit, the equalizer, the attenuator, etc.

FIG. 6 shows the basic configuration of a D/A conversion device according to a first embodiment of the present invention. After the above-described processing steps are performed within the DSP (described later in FIG. 12), a digital signal _Din input as a linear PCM code is applied to a first companding unit 45, where it is converted into a first companding PCM code P3. This first companding PCM code P3 is input to a first D/A conversion system. This system includes a first companding D/A converter 49 that converts the code P3 into a first analog signal A1, and a first amplifier 51 that amplifies the signal A1 by a factor of k3.

In addition to the converter 45, the DSP is also provided with at least a second companding converter 46, a detector 47, and a noise adder 48.
47 detects the quantization noise N of the first companded PCM code P3. In the figure, the detection section 47 is made up of a linear conversion section 47-1 and a subtraction section 47-2.

The quantization noise N is applied to the noise adder 48, where N is k
After being multiplied, it is added to the digital signal D _in .
In the figure, the noise adder 48 is composed of an amplifier (gain k4) 48-1 and an adder 48-2. The output of the noise adder 48 is converted into a second companded PCM code P4 by a second companding converter 46. This code P4 is input to a second D/A conversion system. This system converts the code P4 into a second analog signal A2.
A converter 50 and a second amplifier 5 that amplifies the signal A2 by k5 times.
2. Here, the relationship between k3, k4, and k5 is defined as k3 + k5 = 1, k4 = k3/(1 - k3), and k
3, k4 and k5 are all positive real numbers.

The amplified outputs of the first and second analog signals A1 and A2 thus obtained are added in an adder 53 to obtain an analog converted output _Aout .

The operation of the first embodiment shown in FIGS. 5 and 6 will now be described.

First, let us consider the A/D conversion device shown in Fig. 5. Here, the amplification factor k1 of the first amplifier 38 is k1 = k (therefore, the amplification factor k2 of the second amplifier 40 is k1 = k2).
The amplification factor of the analog signal A in is k (=1/k), and the amplitude of the analog signal A _in is α. After amplification, this signal A _in becomes αk and α/k, which are input to the corresponding companding A/D converters 39 and 41, and become the first and second PCM codes P1 and P2, which are digital values.
These PCM codes are companded codes and are not actual numerical values, so they cannot be used for calculations as they are.
The above codes are then converted back into linear codes L1 and L2, which represent actual numerical values, by linear conversion units 42 and 43. In this state, the average value (L1 + L2)/2 is calculated by calculation unit 43. As will be described in detail later, in addition to the 255 or 256 possible output values of an 8-bit companding CODEC, an intermediate value between adjacent output values is generated from the average value, thereby increasing the variety of output values. This truly means an improvement in the resolution of the A/D conversion device.
The reason is simply that linear codes L1 and L2 are
The 1/k magnification causes a mutual shift, and L1 and L2 have the same value L
When L1 and L2 are different, L is the output value, but when L1 and L2 are different, the intermediate value appears as the output value.

The above operation will be explained further based on a specific example.

First, in the A/D conversion device of FIG. 5, the amplification factor k of the first amplifier 38 is
1, and the amplification factor k of the second amplifier 40 is set to k (=1.01).
2 is set to 1/k (=1/1.01). In the explanation of this embodiment, μ-law is used as an example of the companding law. However, the effect of the present invention remains the same even when A-law is used.

Figure 7 shows the correspondence of each value under the general μ-law. In this figure, the voltage range of the analog input to the companding A/D converters 39 and 41 in Figure 5 (the column of linear input in the figure)
For example, is set to -8158 to +8158, and within that range, 2 ³ (= 256) output values (OUTPUTVALUE) are set. The unit of analog input voltage is, for example, millivolts. And, analog input (linear input in the figure)
For each value, an 8-bit digital code is determined as the μ-law PCM output and output from the A/D converter. For simplicity, the diagram shows only the case for a positive linear input, and only the fourth segment is shown in full, with the intermediate values of the other segments omitted. Here, a segment refers to each polygonal line region when the μ-law characteristic is approximated by multiple polygonal line characteristics, and the quantization step is constant within each region.

The 8-bit digital code in the μ-law PCM output is merely a classification symbol and does not represent an actual amplitude value. Therefore, the first and second linear conversion units (μ/L conversion units) 42 and 43 in the DSP in FIG. 5 convert the corresponding digital values from 0 to 8031 (output values (OUTPUT) in FIG. 7) into
This digital value therefore has 14 bits of precision.

As mentioned above, the first and second linear codes L1 and L2 in FIG. 5 each appear as numerical data corresponding to αk and α/k. In the case of an 8-bit companding A/D converter, the above L1
The output level types for L1 and L2 are 255 or 256 respectively.
However, the actual analog input is -8158 to
The L1 and L2 output levels are continuous values within the range of +8158, and there are 16316 different types, even if we consider only the integer part. The difference between the types of L1 and L2 output levels and the continuous values of the analog input causes the quantization noise mentioned above.
The evaluation item for the converter is the S/N (unit: dB) mentioned above. S here is, for example, the 8 dB for telephone signals.
In the case of a bit-companding A/D (D/A) converter, for example, if a 1010Hz sine wave signal is input to the A/D converter and the output obtained is input to a D/A converter, the signal portion of that output, i.e., the 1010Hz component, is referred to as the 1010Hz component.
The frequency components other than these are noise N. Most of this noise is quantization noise caused by representing a range of analog input with a single output value that is the center value.

Therefore, a high S/N ratio means that the quantization noise is small, and the waveform distortion is small.
To increase the S/N ratio, it is necessary to reduce the quantization noise, which in turn requires increasing the output value of the A/D (D/A) converter, thereby reducing the length of the quantization step.

In the embodiment of FIG. 5, by using two 8-bit companding A/D converters 39 and 41, the output value can be increased as shown below. Moreover, by utilizing a commercially available PCM codec, even if two 8-bit companding A/D converters are used, a signal processing device can be realized at a lower cost than if a single converter with high quantization accuracy (i.e., 8 bits or more) is used.

In FIG. 5, the output values of the first and second linear codes L1 and L2 are respectively D(α·k) and D(α/k). If k is k
If k=1 instead of k=1.01, L1 and L2 will naturally have the same output value. However, as shown as a preferred example in this embodiment, if k=1.01 and the first and second amplification factors are 1.01,
If the difference is small, such as 1/1.01, αk and α/k will be different values. However, the difference is small, and αk and α/k
If the difference between αk and α/k is within the range of each row shown in the column for linear input in Figure 7, the output values D(α·k) and D(α/k) will both match. On the other hand, if the difference between αk and α/k is outside the range of each row, the output values D(α·k) and D(α/k) will be different. In other words, if k≠1 and k is a value close to 1, and one of them enters into an adjacent range (row), the output value corresponding to that adjacent range will be D(α·k).
In the former case (when they match), the average value of αk and α/k, that is, is near the center of the range of each row of the linear input in FIG. 7, and in the latter case (when there is no match), the average value appears near the boundary between the adjacent ranges of each row.

In the calculation unit 44 in FIG. 5, the first and second linear codes
Calculating the average value of L1 and L2, the output Therefore, in the latter case described above, the output _Dout also takes an intermediate value between the output value of this row and the output value of the adjacent row.
When L1 and L2 are in the same range, L1 and L2 are the same.
_The output Dout, which is the average value of L1 and L2, is the same as each of the above output values. In this way, the output value shown in the output value (OUTPUTVALUE) column in Figure 7 and a new output value that is exactly midway between these adjacent output values are generated, and A/
This is equivalent to increasing the resolution of a D converter.

FIG. 8 is a diagram showing the correspondence of values of each part in the A/D conversion device, and shows the amplitude α of the analog signal A _in in FIG. 5, the output value αk of the first amplifier 38, the output value α/k of the second amplifier 4, D(αk) which is the value of the first linear code L1, D(α/k) which is the value of the second linear code L2, and the digital conversion output
D _out The point to note in FIG. 8 is that the normal quantized output values Q2' and Q2' of the companding A/D converters 39 and 41 are shown at the right end.
In addition to Q3', Q4', etc., new output values indicated by Q1, Q2, Q3, Q4, etc. have appeared. This relationship is shown in a more easily understandable way in Figure 9.
Each of Q3', Q4', etc. corresponds to a row in Figure 7.
In the figure, with regard to D(α·k) and D(α/k), if α is within the range of area A in the figure, both of the quantized outputs will be Q3', and the digital conversion output _Dout will also be Q3'. If α is in area B, each quantized output will be divided into Q4' and Q3', and the output _Dout will be the intermediate value Q3. If α is in area C, each quantized output will also be divided into Q3' and Q2', and the output _Dout will be the intermediate value Q2.

In this way, the number of output values has been increased from 255 to
This embodiment nearly doubles the signal strength, and the size of the quantization step (Δ) is nearly halved. As a result, as is generally known, the quantization noise power Δ ² /12 becomes 1/4, and the S/N ratio becomes 6d.
B is improved, and even if DSP processing is applied to the digital conversion output D _out , the deterioration of the S/N ratio can be kept to a minimum.

In this case, as can be seen from FIG. 9, the companding A/D converter 3
If the new boundary values (decision values, shown by dotted lines) are the values obtained by subtracting 1/4 of the quantization step from the upper boundary of the adjacent quantized output values 9 and 41 (Figure 5) and adding 1/4 to the lower boundary, the width of the range that each newly generated output value can take will be the same, making it optimal. Calculating the amplification factor k from this gives us the following: is.

In the case of companding A/D conversion, the quantization step is made larger in areas where the output value is large (i.e., the noise is larger), so the value of (quantization step/|output value|) is generally close to a constant value when added to the output of linear A/D conversion. If this ratio is a constant value, the value of k in the above equation can be uniquely determined. However, as is clear from Figure 7, when we calculate (quantization step/|output value|) for each row, the value cannot be said to be sufficiently constant. For example,
The difference between the values is large: a value of 256/8031 (=3.18%) in part of the eighth segment and a value of 4/33 (=12%) in part of the second segment. Therefore, the optimum value must be determined experimentally. In fact, experiments using a μ-law 8-bit companding A/D converter revealed that k = 1.025 was the optimum value.

Next, the operation of the D/A conversion device shown in Fig. 6 will be explained. For ease of explanation, the amplification factor k3 of the first amplifier 51 is assumed to be 2/3. Therefore, as mentioned above, Under this condition, if the value of the digital signal Din _in FIG. 6 is β, _Din is
45 and input to the first companding D/A converter 49, where it is converted into a first analog signal A1, and then is
(= k3) times. This output is In this case, the first companded PCM code P3 is converted into
The digital signal Din is then input to the digital companding unit 45 and converted back into a linear signal. This allows the output value D(β) for the digital signal _Din (=β) to be recognized as a digital value on the input side. The difference between the value β of the digital signal _Din and the output value D(β) is then calculated in the subtraction unit 47-2, thereby determining the voltage E of the quantization noise N generated from the companding unit 45 via the D/A converter 49. That is, E=β-D(β) (1)

This E is multiplied by 2 (=k4) in the amplifier 48-1 to obtain the input signal D
The resulting signal is added to _in and input to the second companding converter 46. That is, the input to the converter 46 is β + 2E, which can be rewritten using equation (1) as follows: β + 2E = D(β) + 3E (2) Here, |E| corresponds to the output value D(β) or is smaller than 1/2 of the nearest quantization step (q). This is because if the voltage E of the quantization noise N is greater than 1/2 of the quantization step, D(β) will be a different adjacent output value. For example, in FIG. 7, if D(β) is the output value 359, the linear input β will be 351 to 366, and the quantization error will be ±8 or less. This is less than 1/2 of the quantization step 16 of segment 4. Therefore, 3|E| in equation (2) above is less than 3/2 times the nearest quantization step q of D(β).

Here, D _in → second companding conversion unit 46 → D/A converter 50 in FIG.
The value D(β+2E) of the second analog signal A2 obtained by the processing of the second D/A conversion system is classified according to the following conditions to: When +1.5q>3E≧0.5q: D(β+2E)=D(β)+q (3) When +0.5q>3E≧−0.5q: D(β+2E)=D(β) (4) When −0.5q>3E≧−1.5q: D(β+2E)=D(β)−q (5) Here, D(β)+q is the output value adjacent to the upper side of the output value D(β), and D(β)−q is the output value D
This output value is the output value adjacent to the lower side of (β). This output value is multiplied by 1/(=k5) by the second amplifier 52 in FIG. 6, and then added to the adder 53.
The output of the first D/A conversion system mentioned above is From this and the above equations (3) to (5), the sum output _Aout is a value that is classified under the following conditions. That is, when +1.5q > 3E ≥ 0.5q: When +0.5q > 3E ≥ -0.5q: When −0.5q＞3E≧−1.5q: This becomes:

The relationships between the above equations (6) to (8) are shown in Figure 10. First, if a conventional configuration were to have only one companding/expanding conversion section and one companding D/A converter, the entire input digital signal Din within the range of region A _in Figure 10 would be represented by an analog signal with a value of D(β). Therefore, if the digital signal _Din is within the range of region B, the quantization error is small, but if it is within region C or D, the quantization error becomes large. In contrast, in the above-mentioned embodiment, the quantization error can be reduced as shown below.

First, if we rewrite the condition in the above equation (3) or (6), we get 0.5q > E ≥ 0.5q/3. That is, this is the range of the voltage E of the quantization noise of the value β of the digital signal _Din under the condition and the representative value D(β). This shows that the value β of the digital signal _Din in Figure 6 is within the range of area C in Figure 10. That is, β is the representative value D in that range.
The deviation corresponding to (β) is the case when there is quantization noise with a magnitude of about 1/3 of the quantization step q. In such a case, as shown in the above equations (3) and (6),
As a result, the analog signal A _out is a value obtained by adding q/3 to the representative value D (β), and the analog signal A _out and the β
In other words, the quantization error between the 6th
If the value β of the digital signal D _in is within the range of area C in FIG. 10, the output of the first companding D/A converter 49 in FIG. 6 is D
The output of the second companding D/A converter 50 in FIG. 6 is D(β)+q as shown in the above equation (3). Therefore, the outputs from the first and second amplifiers 51 and 52 are and, These are then added by the adder 53, and the analog signal A _out is obtained as follows, as shown in the above equation (6) or FIG. 10:
Therefore, in the past, if the value β of the digital input signal D _in was within the range of area A in FIG. 10, the analog signal A _out could only be expressed as D(β), but in this embodiment, if β is within the range of area C of area A, A
_out can be expressed as {D(β)+q/3}, and the quantization error of β and A _out can be reduced.

Next, in the case of the condition of the above-mentioned formula (5) or (8), the relationship is completely opposite to the above-mentioned condition, and A _out is the representative value D
The value is obtained by subtracting q/3 from (β), and the quantization error between the analog signal A _out and the value of β in area D is reduced.

In addition, in the case of the condition of the above-mentioned formula (4) or (7), β
Since the value of is close to the representative value D(β), the representative value D is used as A _out .
(β) is output as is.

As described above and shown in Fig. 6, the quantization noise generated in the first D/A conversion system via the route _Din → first companding unit 45 → first companding D/A conversion unit 49 is added to the input signal of the second D/A conversion system via the route _Din → second companding unit 46 → second companding D/A converter 50. Therefore, the quantization noise from the first D/A conversion system is almost completely canceled out, and only a maximum of q/2 quantization noise is generated in the second D/A conversion system. At the output of adder 53, the output of the second D/A conversion system is multiplied by 1/3 (=k5) in second amplifier 52, resulting in a maximum of q/6 quantization noise, 1/3 of the conventional level.

In conclusion, in the case of the embodiment of FIG. 6, the output value increases by about three times compared to when only a normal companding D/A converter is used.
For example, a high-resolution companding D/A converter equivalent to 9.5 bits (256×3≈2 ^9.5 ) can be obtained.

The above operation will be explained based on a more specific example. In the explanation of this embodiment, similarly to the case of FIG. 5, the μ-companding law is used.
Although law is taken as an example, the effect of the present invention is the same even when A-law is used.

11A and 11B are diagrams showing the correspondence between values of each part in the D/A conversion device of FIG. 6, and correspond to FIG. 7 for the A/D conversion device. 11A and 11B show the amplitude β of the digital signal D _in in FIG. 6, the first companded PCM code
P3, the value D(β) of the analog signal A1 (digital representation);
Quantum noise N (digital value), voltage E of quantization noise N
(digital value), the digital output (β+2) of the adder 48-2, the second companded PCM code P4, the second analog signal A2 and the analog conversion output As shown in the figure, each analog conversion output A
_{The outs} appear at equal intervals of 5.333 between each other.
The D/A converters 49, 50, etc. correspond exactly to the companding A/D converters 39, 41, etc. in Fig. 5, and as can be seen from the output values (OUTPUT VALUE) in Fig. 7, for example, in the case of segment 4 in the figure, the quantized outputs appear at equal intervals of 16 between each other. Therefore, from Figs. 11A and 11B, it can be seen that the D/A converters 49 and 5
By combining 0, the output interval of the analog conversion output A _out can be subdivided into 1/3 of that of a normal D/A conversion output,
It can be seen that the number of output values has tripled.

The above example shows the case where k3 = 2/3. However, if k3 = 1/2, by performing calculations similar to those of the above-mentioned equations (3) to (8), it can be understood that the number of output values of the analog conversion output A _out will double, and despite the use of an 8-bit companding D/A converter, it will be equivalent to a 9-bit companding D/A converter.

If k3 = 3/4, the number of output values will be four times as many,
It will be understood that although an 8-bit companding D/A converter is used, it is equivalent to a 10-bit companding D/A converter.

FIG. 12 is a detailed circuit diagram of a preferred example of the configuration of the A/D and D/A conversion device according to the present invention.
This means that it can be configured with two sets of existing PCM CODECs and a few other elements.
By simply adding another inexpensive PCM codec to the configuration shown in Figure 2, a high-resolution A/D converter that can be used in practical applications can be obtained.
In addition, in FIG. 12,
The hybrid transformer, amplifier, coarse attenuator, etc. are omitted.

In FIG. 12, the two companding A/D converters 39 and 41 in FIG.
The two companding D/A converters 49 and 50 in FIG.
Two companding A provided by EC54 and the second PCM CODEC55
A/D converter and two companding D/A converters are used to perform A/D and D/
A pair is formed as an integral unit.
The resistors R1 and R2 create an amplification factor k1 (see Figure 5) (k1 = _R2 / _R1 ), and the resistors _R3 and _R4 in the next stage create the following:
An amplification factor k2 (Figure 5) is formed. If k1 and k2 are related to k by 1/k as described above, _R3 and _R4 are determined from k· _R3 /( _R3 + _R4 ) = 1/k.

This is also true for the operational amplifier 57 in the D/A conversion system.
The amplification factor k3 (Fig. 6) is determined by _R7 / _R6 , and k5 is determined by _R7 / _R5 . As a result, the analog conversion output _Aout is (See Figure 6 for A1 and A2.) In the previous example, k3 = 2/
3, k5 = 1/3, but in this example, R ₆ = 1.5R ₇ and R ₅ = 3R ₇ are set.

As shown in FIG. 5, the DSP is configured with the first and second linear conversion units 42 and 43 and the calculation unit 44 (which calculates the average level), and as shown in FIG. 6, the DSP is configured with the first and second companding conversion units 45 and 46, the linear conversion unit 47-1,
These are a subtraction unit 47-2, an amplification unit 48-1 and an addition unit 48-2.
The line 60 is a balancing network for preventing signal leakage in a two-wire to four-wire conversion device (hybrid transformer) not shown in the figure.
The DSP function units 58 and 59 each include the equalizer function (EQL) and attenuator function (ATT), etc. The line sides connected to these DSP function units 58 and 59 are connected to the transmission line via a linear/μ conversion unit (L/μ) 61 and a μ/linear conversion unit (μ/L) 62, respectively.

As described above, according to the first embodiment, particularly the A/D
and D/A converters and DSPs are combined, and the high-resolution input and output of the A/D and D/A converters required by the DSP is handled by the DSP, while the A/D and D/A converters remain the same.
Using its own calculation function, it can generate a cheap amplifier (Fig. 5, 3
8, 40 or 51, 52 in FIG. 6) can be realized.

Second Embodiment Next, a second embodiment of the present invention will be described. This embodiment is characterized in that the clock of a digital signal processed in a DSP or the like is switched from a first clock (receiving clock) to a second clock (transmitting clock) while the digital signal is still in its original form.

FIGS. 13A and 13B are basic block diagrams of a second embodiment of the present invention. FIG. 13A shows the case where one high sampling digital low pass filter is used, while FIG. 13B shows the case where the high sampling digital low pass filter is divided into multiple blocks.

As shown in FIG. 13A, the data series of the first clock passes through a data conversion circuit 63, where the number of data per unit time is multiplied by n (n>1, integer) compared with the original data.
Furthermore, the output of the conversion circuit 63 is passed through a high-sampling digital low-pass filter operating at a sampling rate n times the first clock.
The signal passes through 64 and is input to an interpolation processing unit 65.

The interpolation processing unit 65 calculates and generates conversion data synchronized with the second clock by interpolation based on the timing time difference τ between the first and second clocks detected by the timing difference detection circuit 66, and outputs the converted data.

Also, as shown in FIG. 13B, a high-sampling digital low-pass filter operates at a sampling rate n times the first clock.
64 (Fig. 13A) is decomposed into multiple blocks 67, 68, and 69. The ratio of the sampling rates of adjacent blocks is set to an integer, and the final block 69 operates at a sampling rate n times that of the first clock. The sum of the loss characteristics of each block 67, 68, and 69 is set to be equivalent to that of the original filter 64 in Fig. 13A.

Then, between each block of the high sampling filter, the ratio of the sampling rate of adjacent blocks to one input data (l ₂ ,l ₃ )
In addition, data conversion circuits 70 and 71 are provided which output data of the same amplitude as the input data, in a number equal to the ratio l1 = n/l2 / _l3 of the sampling rate of the first-stage block 67 to the rate of the first clock, compared to the number of data in the original data _per unit _time . This will be described later.

In addition, in FIG. 13B, when the sampling rate of the first stage block 67 is fa, which is the same as the first clock (l ₁ =1),
In this case, the data conversion circuit 63' is not required.

The outline of the operation of the above basic configuration will be explained below.
FIG. 14C is a time chart of the waveforms of the various parts of FIG. 13A.

Hereinafter, the frequency of the first and second clocks is nominally 8K.
The explanation will be given assuming that the frequency is Hz.

In FIG. 13A, as shown in FIG. 14A, the time of the first clock
The data conversion circuit 63 receives, for example, 3.004 KHz sine wave data values _Sn , _Sn+1 , Sn ₊₂ , Sn ₊₃ , ... at _tn , _tn+1 , tn ₊₂ , tn ₊₃ , .... Here, as shown in Figure 14B, the number of data per unit time is n times larger than the original data.
The output of the data conversion circuit 63 is then input to a high sampling digital low pass filter 64 which operates at a sampling rate of 64 kHz, eight times the sampling rate of the first clock. The cutoff frequency of the filter 64 is the cutoff frequency allowed for the data series of the first clock, which is (8/2) kHz = 4 kHz in the case of an audio signal.
At the output of 64, a signal such as that shown in FIG. 14C is obtained.

The time interval of this signal sequence is 1/8 of the time interval when synchronized with the first clock.

Now, in FIG. 14A, the times T _n-1 , T _n , T _n+1 ,
_The data values at T n _{+ 2} , T _{n +3} , . . _. are converted into data values S _n , S
Even if an attempt is made to use Lagrange's interpolation method using _{S n+1} , S _n+2 , S _n+3 , . . . to find the value, it is difficult to do so because the time intervals between each piece of data are wide and the data values change greatly.
However, as in this embodiment, the time interval of the first clock is set to 1/8
If this is the case, the time interval between each piece of data will be narrower and the change in data value between adjacent times will be smaller.
It is possible to find the data values at T _n-1 , T _n , T _n+1 , T _n+2 , T _n+3 , . . .

That is, as shown in Fig. 14C, the timing difference τ between the first clock and the second clock is found by a timing difference detection circuit 66 and input to an interpolation processing unit 65. Then, the interpolation processing unit 65 can find the data value F of the second clock time Tn _{-1 by Lagrange} 's interpolation formula F = [Fm{(τa/n) - _{Δτ} + Fm-1 · Δτ] ÷ (τa/n) using the period τa of the first clock, the difference Δτ between the second clock time Tn+1 and the time of the 1/8 time interval beyond Tn+1, and the 1/8 time interval data values Fm-1 , Fm on both sides of} the second clock time Tn ₊₁ .

In this way, the times T _n-1 , T _n , T _n+1 , T _n+2 ,
The data values at T _n+3 , . . . are determined and output as digital data values for the second clock.

In this way, since digital signals are not converted into analog signals, quantization noise does not occur, and since all processing is done digitally, it is possible to integrate the signal into a small size.

In addition, the high sampling digital low pass filter 6 in FIG.
4 operates at a repetition frequency eight times the sampling frequency of the original data. In other words, eight pieces of data are input and eight pieces of data are output during the repetition period of the sampling frequency of the original data, so the processing volume is eight times that when operating at the sampling frequency of the original data.

For example, if the high sampling digital low pass filter 64 has a sixth order and a second order delay equalizer that suppresses the generation of group delay distortion caused by the filter, the filter becomes eighth order.
In terms of processing volume, the equivalent order is 64th.

The digital filter is 2nd order, y _n = a x _n + b x
Since the difference equation _n-1 + c.xn _-2 - d.yn _-1 - e.yn _-2 is calculated once, the number of multiplications is 5 per period, which is 160 times per period for the 64th order. Therefore, when viewed as a program executed by the digital signal processor (DSP),
The process involves more than 220 steps, including data conversion procedures.

Even if a high-speed digital signal processor with a processing time of 100 ns is used, when one cycle is 125 μs (8 KHz), only a maximum of 1250 steps can be processed, of which 220
Allocating steps to filter calculation for the clock transfer method is undesirable as it reduces the allocation of other processes.

Therefore, as shown in FIG. 13B, the filter is divided into multiple blocks, and processing that can be performed at a low sampling rate is performed by a filter with a low sampling rate, thereby significantly reducing the amount of processing.

For example, the processing in the delay equalizer is related only to the passband, and delays in frequencies above 4KHz, which is the stopband, are not an issue. Therefore, the sampling rate of the original data is 8K.
This can be done with a filter block 67 operating in Hz.

Next, for example, frequency components from 4 kHz to 8 kHz are cut off by a filter block 68 operating at a sampling rate of 16 kHz, and frequency components from 8 kHz to 32 kHz are cut off by a final filter block 69 operating at 64 kHz, the same sampling rate as the high-sampling digital low-pass filter 64 in Figure 13A.

In this example, the sampling rate of the first stage block 67 is the same as the first clock, so the data conversion circuit 63' is not required.

The input side of the filter block 68 is connected to a data conversion circuit that outputs two pieces of data with the same amplitude for one piece of input data.
On the input side of the filter block 69, there is provided a data conversion circuit 71 which outputs four pieces of data with the same amplitude in response to one piece of input data.

By doing this, for example, the sampling frequency is 8KHz
If the blocks 67 and 69 with a sampling frequency of 64KHz are configured with a second-order filter, and the block 68 with a sampling frequency of 16KHz is configured with a fourth-order filter, the total number of multiplications per period is five per second order as mentioned above, and therefore, from the relationship between the order ratio and the sampling rate, it is 5 x 1 + 5 x 2 x 2 + 5 x 2
× 4 = 65 times, which can significantly reduce the amount of calculation.

Even if the filter block 69 is configured as shown in FIG. 13B,
The number of output data is eight times the original data,
This is the same as in the case of the filter in FIG. 13A, and the interpolation processing unit 65 can perform the process of changing from the first clock to the second clock in the same way as in the case of FIG. 13A.

Next, the detailed configuration and operation of each part in FIG. 13A or 13B will be described.

FIG. 15 is a block diagram of the data conversion circuit 63 of FIG. 13A;
FIG. 16 shows the high sampling digital low pass filter 64.
17 is a diagram showing the attenuation of the filter of FIG. 16; FIG. 18 is a flowchart of the program of the interpolation processing unit 65 of FIG. 13A; and FIG. 19 is a timing difference detection circuit of the same.
66 is a block diagram of the principle.

In each figure, 72 is a memory, 73 and 109 are multipliers, 108 is a 10-bit counter, 110 is a 10-bit register, 111 is a switch, 74 to
Reference numeral 77 denotes an adder, 78 to 87 denote data delay memories, and 88 to 107 denote coefficient multipliers.

The data conversion circuit in Fig. 15 is an example of a circuit that outputs the same data eight times in one period. This circuit writes, for example, 16-bit amplitude data input at intervals of 8 kHz in synchronization with the first clock into memory 72 at the first clock, and
The data is output eight times in one cycle using a read clock obtained by multiplying the clock by eight in a multiplier 73.

Figure 16 shows an example of a high sampling digital low-pass filter consisting of four sections of a second-order digital filter with a cutoff frequency of 3.8 kHz.
The first is a low-pass filter that blocks frequencies between 4KHz and 60KHz, and the other second order is a delay equalizer that equalizes the group delay distortion of the filter. The entire filter operates at a sampling rate of 64KHz, performing eight filter calculations per 8KHz period.

The attenuation characteristics are as shown in Figure 17.
The gain of 2 to 3 dB around 3.4 kHz is due to the fact that the input signal is processed as NRZ, and RZ/NRZ correction is performed.

Of course, the filter may be realized by a large transversal filter.

In the interpolation process shown in the operation flowchart of FIG. 18, if the same data is input eight times during τ _a in the period of the first clock (see FIG. 14C), then in step S1
While comparing with the time difference τ between the first and second clocks, m in τ _a m/8 (m = 1 to 8) is increased in order starting from 1. Then, the comparison is stopped when the sign of Δτ = τ _a m/8 - τ becomes positive, and the difference Δτ between T _n+1 in Figure 14C, which is the time of the second clock, and the time 1/8 of the time interval beyond T _n+1 , as well as the value of m, are found. In the case of Figure 14C, it can be seen that m = 5.

Therefore, in step S2, from the data values F _m-1 and F _m when m = 4 and 5, the data value F of the second clock time T _n+1 is calculated using the Lagranche interpolation formula F = [F _m {( _{τ a} /n) - Δτ} + F _m-1 · Δτ] ÷ (τ a /n).

In this way, the time T _n-1 of the second clock in FIG.
The data values at T _n , T _n+1 , T _n+2 , T _n+3 , . . . can be determined.

19 is a diagram showing the principle configuration of a timing difference detection circuit. A detailed embodiment thereof will be described later in the third and fourth embodiments.
This will be explained in the examples.

In the timing difference detection circuit shown in the figure, the first clock is multiplied by, for example, 2 ^×10 in a multiplier 109, and this is input to a 10-bit counter 10
The counter is reset at the rising edge of the first clock.
The counter value of the first clock is 2 ¹⁰ = 102
It indicates the position within a quarter of the time, so for example, if the number is 512, the time is exactly in the middle of the first clock.

Therefore, by turning on switch 111 at the timing of the second clock and inputting the value of counter 108 into 10-bit register 110, the time difference τ between the first clock and the second clock can be calculated with a resolution of 1024 cycles.

Next, a case where the clock transfer method of the present invention is applied to a PCM channel device shown in FIG. 12 will be described.

Fig. 20 is a block diagram of a digital PCM channel apparatus based on the second embodiment. In this figure, parts with the same numbers as those in the basic configuration of the conventional example in Fig. 3 and the second embodiment in Fig. 13A have the same functions.

In the figure, the clock timing is the received PCM signal R
There are a receiving clock RCLK recovered from IN by a receiving timing recovery circuit 115 and a transmitting clock SCLK from a transmitting clock generator 114 of the own station.
LK is a signal input to the receiving register 116, the D/A converter 24, the A/D converter 23,
The receive clock RCLK is input to the digital signal processor (DSP) 118 and the transmit/receive timing difference detection circuit 66, and most functions operate based on the receive clock RCLK. On the other hand, the transmit clock SCLK is input to the transmit register 113 and the transmit/receive timing difference detection circuit 66.

Therefore, in the circuit of Fig. 20, the input signal SIN from the subscriber is picked up by the receiving clock RCLK, and the received PCM signal RIN from the other station is written into the receiving register 116. Then, the signal is read out by the receiving clock RCLK, and
A μ-law companding PCM signal is converted into a 16
The signal is converted into linear data of 128 bits and input to the receiving level setting/equalizer 28. The transmitting side performs corresponding processing in the transmitting level setting/equalizer 27, and the receiving side performs corresponding processing in the receiving level setting/equalizer 28. Furthermore, processing in the precision balancing circuit 29 that spans the transmitting and receiving systems is also performed using the same receiving clock RCLK, so the problems caused by the clock misalignment mentioned above do not occur.

However, since the output signal SOUT must be output at the timing of the transmission clock SCLK, the transmission level setting and equalization circuit 27
The output data sequence is converted into the data conversion circuit 6
3. The aforementioned clock transfer process is performed using a high sampling digital low-pass filter 64, an interpolation processing unit 65, and a (transmission/reception) timing difference detection circuit 66. The signal converted into amplitude data in accordance with the timing of the transmission clock SCLK in this way is converted from a linear signal into a PCM signal with a μ-law companding law by an L/μ converter 112, written into a transmission register, read out by the transmission clock SCLK, and transmitted as an output signal SOUT in a jitter-free state to a multiplexer (not shown).

In the above configuration, the data conversion circuit 63, high sampling digital low-pass filter 64, and interpolation processing unit 65 operate digitally, and therefore can be integrated and miniaturized together with other digitally operated circuits as a digital signal processing unit (DSP) 118. Furthermore, the (transmit/receive) timing difference detection circuit 66 also operates digitally, and therefore can be integrated and miniaturized together with other digitally operated circuits as an interface LSI 119. Of course, other methods of division for integration may be used. Furthermore, although the A/D converter 23 and D/A converter 24 in Fig. 20 have a conventional configuration, significant advantages can be obtained by combining them with the configuration of Fig. 12 shown in the first embodiment described above.

Next, a specific circuit configuration of the technique for dividing a high sampling digital low-pass filter into several selections in order to reduce the number of calculations, as explained in FIG. 13B, will be explained.

FIG. 21 shows the configuration of the high sampling filter block divided into a plurality of selections in FIG. 13B, and FIG. 22 shows the attenuation of each selection in FIG. 21, where 1 to 3 correspond to the 1 to 3 filter blocks in FIG. 21.
21 shows the overall attenuation of the filter shown in FIG.

In FIG. 21, 120 to 123 indicate adders, 124 to 135 indicate data delay memories, and 136 to 154 indicate coefficient multipliers.

The filter block in Figure 21 is a delay equalizer, which is only concerned with the passband and does not have a delay characteristic in the stopband, i.e., frequencies above 4 kHz. Therefore, it operates at the sampling rate of the original data of 8 kHz, and there is no need for a data conversion circuit (see 63' in Figure 13B) in the preceding stage.

The filter block cuts off frequency components between 4 kHz and 8 kHz and operates at a sampling rate of 16 kHz. In this case, a data conversion circuit (see Figure 13B) is required on the input side to output two data of the same amplitude for one data.

The filter block blocks frequency components from 8KHz to 16KHz and operates at a sampling rate of 32KHz.
In this case, two pieces of data with the same amplitude are used for one piece of data.
A data conversion circuit (see Figure 13B) that outputs a single signal is required on the input side.

The filter block blocks frequency components from 16KHz to 32KHz and operates at a sampling rate of 64KHz.
In this case, too, a data conversion circuit that outputs two pieces of data with the same amplitude in response to one piece of data is required on the input side.

With the above configuration, the number of data output from the filter block is eight times the original data, which is the same as the case of the filter in FIG. 16, and the interpolation processing unit (6 in FIG. 13B)
5) can process the transition from the first clock to the second clock.

In this case, the number of multiplications per cycle is 5×1, since there are five coefficient multipliers in the filter block.
The filter block has eight coefficient multipliers and a sampling rate of
Since the sampling rate is 16KHz, it is 8 x 2. In the filter block, there are three coefficient multipliers and the sampling rate is 32KHz, so it is 3 x
4. In the filter block, there are three coefficient multipliers and the sampling rate is 64 kHz, so the total number of multiplications is 3 x 8, or 57. This is significantly less than the 160 times required for the filter in Figure 16.

As described above, according to the second embodiment, it is possible to transfer the data series of the first clock to the data series of the second clock while keeping it digital, thereby eliminating the quantization noise that was a problem in the conventional example of FIG. 4.
In this case, the communication quality does not deteriorate, and integration has the effect of enabling extremely small size.

Furthermore, it can also be integrated together with other digital circuits to make it smaller and less expensive.

Third Example Next, a third example will be described.
The timing difference detection circuit 66 in FIG. 13A or FIG. 20 in the second embodiment is specifically disclosed, and
This refers to the configuration of the transmit register 113 in FIG.

This embodiment is based on the principle and configuration shown in Fig. 19. According to the principle shown in Fig. 19, as already described, the 10-bit counter 108 counts up at the first clock (hereinafter referred to as the reception clock RCLK).
The counter is then reset and operated. The contents of the counter are latched into a 10-bit register 110 at the rising edge of the second clock (hereinafter referred to as the transmission clock SCLK) or the like, and the timing difference τ is detected.

In the above principle, if the latch is performed at the rising edge of the transmission clock SCLK, for example, data τ with a timing difference is generated at that point.
Interpolation processing unit 65 in signal processing unit 118 that operates based on LK
(See FIG. 13A or FIG. 20), the time is not constant when viewed from the signal processing unit 118 side.
It is input at the beginning or end of the interpolation process (see Figure 18), so a buffer circuit is required for time adjustment.

Furthermore, when the period of the transmitting clock SCLK is slightly shorter than that of the receiving clock RCLK, it may be necessary to detect the timing difference twice in one RCLK period. Conversely, when the RCLK period is slightly shorter than that of the SCLK, the rising edge of the SCLK may not fall within the RCLK period.

When the periods of the transmission clock SCLK and the reception clock RCLK are slightly different in this way, the number of input data within one period can be three, 0, 1, or 2, and the occurrence times are not constant, so a buffer circuit is required between the transmission/reception timing difference detection circuit 66 and the signal processing unit 118. This embodiment discloses a specific circuit for the transmission/reception timing difference detection circuit 66 including the buffer circuit.

FIG. 24 shows the data of FIG. 20 in the second embodiment.
A specific circuit configuration of the transmission/reception timing difference detection circuit 66 in the PCM channel device is shown.

In the figure, the l-bit counter 155, latch 156 and multiplier 157 are respectively the 10-bit counter 108 (l=1) shown in FIG.
0) It is the same as the 10-bit latch 110 and the multiplier 109. The first clock and the second clock correspond to the receiving clock RCLK and the transmitting clock SCLK in FIG. 20, respectively.

When viewed from the signal processing unit side (118 in FIG. 20),
As mentioned above, when the time when the timing difference data τ is generated from the latch 156 is not constant, and data from the previous cycle is not processed when data is taken in for the current cycle based on the receiving clock RCLK, there may be cases where the data from the previous cycle remains unprocessed. For this reason, two parallel buffer circuits are provided as shown by 159 and 160 in FIG. 24, and selector switches SW1 to SW6 are provided on the input and output sides of the buffer circuits so that they can be switched between even and odd cycles of the receiving clock RCLK. As a result, one of the buffer circuits 159 and 160 is used to input the data from the latch 156.
When data is being written from one end, the other end is connected to a signal processing circuit, and the data is read out.
The control signal for switching odd cycles is obtained by dividing the receive clock RCLK by 1/2 in the frequency divider 158.

Furthermore, as mentioned above, when the period of the transmission clock SCLK is slightly shorter than the period of the reception clock RCLK, it may be necessary to detect the timing difference twice in one period of the RCLK, and furthermore, it may happen that the data from the previous period comes in while the data from the next period has not yet been processed.
The contents of these are selected by a selector 164.

Furthermore, when the above two-stage configuration is used, information equivalent to an address pointer indicating how many pieces of data are input in one cycle is required, so an input data number memory for storing this information is also required.
As mentioned above, if the period of the receiving clock RCLK is slightly shorter than the period of the transmitting clock SCLK, the rising edge of SCLK may not fall within the period of the RCLK. In such a period, the signal processing unit 118 in FIG. 20 should not perform processing in the interpolation processing unit 65. For this reason, the input data number memory 163 is provided for each buffer.
The memory is reset by a control circuit (not shown) immediately before each connection to the latch circuit.

In response to the operation of the transmission/reception timing difference detection circuit 66 (FIG. 20) specifically shown in FIG. 24, the signal processing section of FIG.
The operation of 118 is as follows: First, the processing of the high sampling frequency low pass filter 64 is always performed. Next, the interpolation processing unit 65 calculates the timing difference data τ
and performs the following processing. That is, the contents of the input data number memory 163 in the currently selected buffer circuit 159 or 160 in Fig. 24 are checked, and if it is zero, the output of the output signal SOUT for transmission is not required, so interpolation processing is not performed. If the number of input data is 1 or more, data is input sequentially from the corresponding memory 161 or 162 while operating the selector 164, and interpolation processing is performed a number of times equal to the number of data,
The output signal SOUT is obtained.

Next, the processing related to the transmission register 113 in FIG. 20, which corresponds to the timing difference detection processing and interpolation processing, will be described.

The output signal SOUT is calculated and generated by the signal processing unit 118, which operates in synchronization with the receiving clock RCLK, and is therefore outputted from the signal processing unit 118 in near synchronization with the receiving clock RCLK. However, as described above, the output signal SOUT is outputted in near synchronization with the transmitting clock SCLK
Since the data must be output to the outside in accordance with the time, a buffer circuit for time adjustment is also required here. This is the function of the transmit register 113 in Figure 20. The requirements for this register are as follows:

The time when data is input from the signal processing unit 118 to the transmission register 113 and the time when the output signal SOUT is output from the same register are independent.
If the period of one clock is slightly different from that of SCLK, the other clock is always moving relative to the other clock, and it is inevitable that the two times will coincide over a long period of time. In this case, a write process will be performed in the transmit register 113 while data is being transferred from the same register to the outside, destroying the transferred data. Therefore, it is necessary to prevent data from being input from the signal processing unit 118 to the same register while the output signal SOUT is being output from the transmit register 113 to the outside.

As mentioned above, the number of pieces of output data from the signal processing unit 118 can be 0, 1, or 2 per period. Generally, when two pieces of data are output per period, they are output consecutively with little time difference, and when there is a period without data output, they are output consecutively with almost no time difference.
After the time equivalent to the period has elapsed, the next data is output.
The data input at such time intervals is sent by the transmission clock.
It is necessary to adjust the time so that the output is synchronized with SCLK.

To satisfy the latter condition, the transmit register 113 in Fig. 24 is composed of a plurality of registers, not specifically described in detail. Furthermore, a decision circuit is provided within the register to determine which of the data in the plurality of registers is to be output. This decision circuit makes a decision using the number of data received from the signal processing unit 118 and the register number that output data in the previous cycle as parameters. Therefore, a counter is also provided to count the number of received data.

To satisfy the former condition, the transmission register 113 is also provided with a control circuit that prevents input data from being sent to the counter while the counter is being reset or while the count result is being transferred.

A specific circuit for the transmission register 113 will be further described in the fourth embodiment described next.

Fourth Embodiment Finally, a fourth embodiment will be described. Like the third embodiment described above, this embodiment specifically discloses the (transmission/reception) timing difference detection circuit 66 in Fig. 13A or 20, and also refers to the configuration of the interpolation processing unit 65 and transmission register 113 in Fig. 20. In this embodiment, the operational relationship between the first clock (reception clock RCLK) and second clock (transmission clock SCLK) described above with respect to the transmission/reception timing difference detection circuit 66 is reversed, making it possible to further simplify the circuit configuration compared to the third embodiment.

FIG. 25 is a circuit block diagram of the transmission/reception timing difference detection circuit 66, and FIG. 26 shows the operation flow of the signal processing unit 118 of FIG. 20 in the second embodiment.

In FIG. 25, the system clock of the second clock generated in the data PCM channel device of FIG. 20 is divided by a frequency divider.
20. In FIG. 25, the signal is divided by 1/ ^2L at 165 to generate the transmission clock SCLK, which is the second clock. This portion corresponds to the transmission clock generator 114 in FIG. ...
A major feature of this system is that the receive clock RCLK, which is the reference clock of the L-bit counter 166 (Fig. 0), is used as the latch signal for the latch circuit 167, and the system clock, which is the second clock synchronized with SCLK, is used as the counter operating clock for the L-bit counter 166.

As described above, the operation of the latch circuit 167 is controlled by the receiving clock RCL
By synchronizing with K, the input time of the timing difference data to the signal processing unit 118 can be made to have approximately the same relationship with the processing in the signal processing unit 118 that operates in synchronization with RCLK.

Another point of this embodiment is that the interpolation processing unit 65 (FIG. 20) which performs the operation of FIG. 26 described later,
The number of interpolated data calculations to be performed within one RCLK-based period is determined as follows: Since the transmission clock SCLK differs in period length by a maximum of ^10-4 , the timing difference between each period typically gradually increases or decreases; when the number of data items per RCLK-based period is zero or around two, the timing difference between adjacent periods changes significantly. By utilizing this characteristic, the interpolation processor 65 can determine the number of interpolated data calculations to be performed within one period from the change in the timing difference between the current period and the previous period.

With the above configuration, the timing difference detection circuit does not require a buffer circuit, and the circuit scale can be significantly reduced.

The operation of the transmission/reception timing difference detection circuit 66 and the interpolation processing in the interpolation processing unit 65 according to the fourth embodiment shown in FIGS. 25 and 26 will now be described in more detail.

First, in Fig. 25, the system clock, which generates the transmission clock SCLK and has a frequency ^2L times higher, is input to an L-bit counter 166 to perform counting. For example, if L = 10 and the SCLK frequency is 8 kHz, the system clock frequency will be 8.192 MHz. In this case, the counter 166 will:
The count value ranges from 0 to 2 ^L −1. The count value returns to 0 according to the SCLK cycle, so
Equivalently, it is reset every cycle based on SCLK.

If the counter value is latched at, for example, the rising edge of the receive clock RCLK, the value will be the timing difference based on SCLK, where one cycle of the transmit clock SCLK is 2 ^L. Generally, the counter 166 can latch the count value without stopping, so the counter will be reset by SCLK as described above.

After the latch operation, the latched data is transferred to an input register (not shown) in the signal processing unit 118 of FIG.
By applying a bit transfer clock to the latch circuit 167, the data can be transferred immediately after the latch operation. Therefore, the time from the latch operation to the transfer is very short, and the transfer can be performed at a constant timing within each cycle based on the receive clock RCLK. This means that the transfer operation is performed in synchronization with the receive clock RCLK.

On the other hand, the signal processing unit 118 receives the reception clock R
This means that the signal processing unit 118 operates based on the CLK.
This means that the difference between the time when various processes are performed and, for example, the rising edge of the receiving clock RCLK is a constant value. Therefore, after the timing difference data is transferred from the latch circuit 167 to the input register in the signal processing unit 118,
The time until this data is actually used is also constant, and the length is equal to or less than the length of each cycle of the transmission clock SCLK.
When data is to be transferred to the input register in 18, there is no unused data remaining in the input register, and a buffer circuit is not required.

Regarding the operation of this embodiment shown in FIGS. 25 and 26,
This will be explained using the timing charts of Figures 27A and 27B.

27A and 27B, the horizontal axis represents time. _t0 , _t1 , _t2 , and so on in the figures represent rising points of the receiving clock RCLK, and _T0 , _T1 , _T2 , and so on in the figures represent rising points of the transmitting clock SCLK, for example.

In addition, among the plots shown in the figure, the receive clock
The plots '.' synchronized with the timings t ₀ , t ₁ , t ₂ . . . of RCLK are original data synchronized with the receiving clock RCLK and input to the data conversion circuit 63 in FIG.

The other plots "-" are the outputs of the high sampling low pass filter 64 in Fig. 20, and correspond to Fig. 14C of the second embodiment. In Fig. 14C, the high sampling is 8 per cycle, but in Fig. 27A or 27B, the high sampling is 4 per cycle for simplicity. Furthermore, in Fig. 27B, the timings _T0 , _T1 , and T2 of the transmission clock SCLK are
Plots synchronous with _T2 , ... are shown by '.' _S0 , _S1 , S
₂ , ... are interpolated by the interpolation processing unit 65 in FIG. 20, and clock transfer to the transmission clock SCLK is performed, and the output signal SO
This is the signal value that should be output as UT.

27A shows an example in which the period of the transmitting clock SCLK (period S) is longer than the period of the receiving clock RCLK (period R). However, since the difference is actually up to ^10-4 , the timing difference between them is exaggerated in the figure for ease of understanding.

Here, since the clock of the L-bit counter 166 in FIG. 25 is synchronized with the transmission clock SCLK, t _n (n0, 1, 2, . . .
The counter indicates zero at each time t0, t1, t2, .... The count value is latched at _t0 , _t1 , _t2 , ... and is transferred to the signal processing unit 118 (Fig. 20) almost simultaneously. The magnitude of the count value at this time, i.e., the transmission clock SC
The timing difference between the receive clock RCLK and LK as a reference is indicated by a double line, and the latch time is indicated by an upward arrow.

In Figure 27A, the length of the horizontal double line gradually shortens, reaches zero, then becomes maximum again, and then gradually shortens again. Also, when viewed with respect to one period of the transmission clock SCLK as the reference, such as the periods _T1 to _T2 or _T6 to _T7 , the arrows indicate that the count value is transferred twice per period. However, when viewed from the perspective of the signal processing unit 118 that receives the transfer (which operates in synchronization with the reception clock RCLK),
As will be described later, in the interpolation process shown in FIG. 26, one
In this case, the timing difference (count value) at _t0 or _t6 is very small, and the timing difference (count value) at _t1 or _t7 is very small.
The timing difference at is approximately equal to the length of one period. This characteristic determines whether or not interpolation is performed, as will be described later.

In Fig. 27A, the time when an output signal is output from an output register _{R0 (} to be described later) in the signal processing unit 118 to a register _R1 in an external output timing adjustment circuit (equivalent to the transmission register 113 in Fig. 20) is indicated by a bar. The output timing adjustment circuit will be described in detail later.
In the figure, for example, the output signal SOUT at time _T5 of the transmission clock SCLK
The timing difference between _T5 and _t5 is detected at _t5 and the signal processing unit
The signal S5 is transferred to 118, where it is subjected to an interpolation calculation, and is obtained as _S5 . This _S5 is obtained at _t5.5 ( _t5
Similarly, SOUT at SCLK time _T6 is obtained as _S6 by detecting the timing difference between _T6 and _t6 at t6, transferring it to the signal processing unit 118, and performing an interpolation calculation. Then, it is output to the output timing adjustment circuit at _t6.5 , _0.5 cycles later. On the other hand, SOUT at SCLK time _T7 is obtained as _S6 by detecting the timing difference between _T7 and _t8 .
The timing difference between this and the output timing signal _S7 is detected at _t8 and calculated by interpolation. This is then output to the output timing adjustment circuit at _t8.5 , 0.5 cycles later.

From this perspective, it can be seen that there is no transmission clock SCLK corresponding to the timing difference equal to approximately one cycle length detected at _t1 or _t7 , and therefore, in this case, it is not necessary to output the output signal SOUT (Fig. 20). In the case of Fig. 27A, while the transmission clock SCLK changes from _T1 to _T10 , the reception clock R
As can be seen from the fact that CLK changes from _t0 to _t11 , the above fact indicates that the S period is greater than the R period, and therefore the number of outputs of the output signal SOUT per unit time is equal to the number of outputs of the received PCM signal RIN (the
This corresponds to the requirement that the number of

Therefore, when the tendency of the timing difference is correlated with the output operation of the output signal SOUT from the signal processing unit 118 to the output timing adjustment circuit, "in the relationship between the timing difference determined as the time from the rising edge of the transmission clock SCLK to the next rising edge of the reception clock RCLK and the period based on the reception clock RCLK, if the timing difference of the previous period is almost zero and the timing difference of the current period is almost one period length,
It becomes clear that the output signal SOUT should not be output to the output timing adjustment circuit. This corresponds well to the fact that the interpolation process described above is performed only once per period at the same timing, and the above control is realized by the operation flowchart in FIG. 26, which will be described later.

Next, FIG. 27B shows the period length (R period) of the receiving clock RCLK.
This is an example in which is greater than the period length (S period) of the transmission clock SCLK. In this case too, the timing difference between and is exaggerated for ease of understanding.

As can be seen from the figure, the timing difference increases over time.
When it reaches a magnitude equal to the period, it becomes zero in the next period,
From there, the movement is repeated, gradually increasing in size.

Here again, for example, the output signal SO at time _T5 of the transmission clock SCLK
UT is calculated as _S5 by detecting the timing difference between _T5 and _t5 at _t5 and transferring it to the signal processing unit ₁₁₈ , where it is subjected to an _{interpolation} calculation.
The SOUT signal at the timing of SCLK _{T6 is output to the output timing adjustment circuit at t6.5 ,} which is the intermediate time between T6 and t6. Next, the timing difference between _T6 and _t6 is detected at _t6 and transferred to the signal processing unit 118, where it is interpolated to obtain _S6 . Then, the SOUT signal is output to the output timing adjustment circuit at _t6.5 , 0.5 periods later.

On the other hand, consider the output signals SOUT of SCLK at _T7 and _T8 . In the same way as in the cases of _T5 and _T6 , SOUT at _{T7 is}
The timing difference between t7 and _t7 is detected at _t7 , and t
However, as can be seen from Fig. 27B, the counter that started counting at T7 returns to zero at _T8 , so that the timing difference between _T7 and _t7 essentially becomes equal to the timing difference between _{T8 and t7} , and this value is transferred to the signal processing unit ₁₁₈ , so the value output to the output timing adjustment circuit at _t7.5 is the output signal at the timing of _T8 of the transmission clock SCLK _.
In this case, the output _S7 at the time corresponding _{to T7} will be insufficient.

To compensate for this, in this embodiment, an output signal _S7 corresponding to _T7 is output to the output timing adjustment circuit before _t7.5 .

The value of the timing difference in this case is the difference between _T7 and _t7 , and can be considered to be substantially one cycle length. This is because the difference between the receive clock RCLK and the transmit clock SCLK is only about ^10-4 to begin with. Therefore, when the tendency of the timing difference is correlated with the number of output signals from the signal processing unit 118 to the output timing adjustment circuit, it becomes clear that the "transmit clock SCLK
The timing difference is determined as the time from the rising edge of the receive clock RCLK to the rising edge of the next receive clock RCLK.
In relation to the period based on LK, when the timing difference of the previous period is approximately equal to one period and the timing difference of the current period is approximately zero, it becomes clear that the transmit signal must be output to the output timing adjustment circuit twice, with the first output calculated as having a timing length of one period and the second output calculated as having a timing difference of zero.

Taking advantage of the above fact, in this embodiment, the processing shown as an operation flowchart in FIG. 26 is carried out by the signal processing unit in FIG.
This is implemented by the interpolation processing unit 65 in 118, and it very simply deals with the problem of the number of output signals from the signal processing unit 118 to the output timing adjustment circuit (=transmission register 113) and the problem of their amplitude.

In Fig. 26, the timing difference of the current period is _τx , and the timing difference of the previous period is _τb . Furthermore, the length of one period based on the transmission clock SCLK is set to ^2L -1 using the counter bit length L. The operation of Fig. 26 is shown below.

First, the interpolation processing unit 65 in FIG. 20 receives, for example, a received clock RC
Operation begins at each timing _t0 , _t1 , _t2 , ... based on LK, and at each timing, highly sampled processed data for the previous cycle is fetched from the high sampling low pass filter 64. For example, in Figure 27A, at timing _t5 , the processed data (plot '.') from _t4 to _t5 is fetched.

Next, the transmission/reception timing difference detection circuit 66 shown in FIG.
(FIG. 20), the timing difference data τ _x is read in via an input register (not shown) in the signal processing unit 118 (FIG. 20) (FIG. 26 S1).

If τ _b ≈0 and τ _x ≈2 ^L −1, no transmission signal is output in that period (S1 → S2 → S3 → S1 in FIG. 26).
2) As mentioned above, this corresponds to the processing at timings such as _t1 or _t7 in FIG. 27A.

On the other hand, if τ _b ≈2 ^L −1 and τ _x ≈0, the transmission signal is output twice in the cycle as follows (S1 → S2 → S4 →
S9 → S10 → S11). The first time, the value is τ _x = 2 ^L - 1, which is the timing difference τ when corrected based on the period of the receiving clock RCLK, so τ = 2 ^L - 1 - τ _x.
= 0. When τ = 0, the output value is
As can be seen from Figure 14C, this is F ₀ itself, and this value is output. The second time, τ _x = 0, that is, τ = 2 ^L −1
In this case, the output value is _Fm itself, and this value is output.
This corresponds to processing at timings such as _t2 or _t7 in the diagram.

In other cases, in Figure 26, S1 → S2 → S3 → S5, or
The process is S1 → S2 → S4 → S5, and in S5, τ = 2 ^L −1 −
τ _x is calculated, and in steps S6 and S7, the same interpolation process as in the second embodiment shown in Fig. 18 is carried out. Then, the output value F found in step S8 is output as the amplitude value of the output signal SOUT.

In S12, the timing difference τ _x of the current period is changed to the timing difference τ _b of the previous period, and is used in the processing of the next period.

As described above, in this embodiment, the (transmission/reception) timing difference detection circuit 66 in FIG. 20 is configured to detect the difference based on the second clock (transmission clock SCLK) as shown in FIG. 25.
The interpolation processing unit 65 in the signal processing unit 118 performs the processing shown in the operation flowchart of Fig. 26. As a result, the transmission clock SCLK and the reception clock RC can be easily generated by simply adding a very simple circuit configuration and simple logical decisions such as those shown in Fig. 26.
It is possible to completely input to the signal processing section information that is important for clock transfer, such as the timing difference with LK and control of the number of data outputs per cycle.

Next, the output timing adjustment circuit will be described.

As mentioned above, the amplitude of the output signal SOUT is processed by the high sampling low pass filter 64 and the interpolation processing unit 65 in the signal processing unit 118 of Fig. 20, and is set to an amplitude value that matches the timing of the transmission clock SCLK. On the other hand, the output timing adjustment circuit described below adjusts the amplitude of the output signal SOUT to the amplitude of the high sampling low pass filter 64 and the interpolation processing unit 65 of the signal processing unit 118 of Fig. 20.
As shown in the figure, the output signal train output from the signal processing unit 118 at irregular time intervals is used as an input signal, and the timing of these signals is adjusted to output them to an external line at regular intervals synchronized with the transmission clock SCLK as shown in the figure. This circuit corresponds to the transmission register 113 in Figure 20 of the second embodiment.

Here, the vertically long rectangles in Fig. 27A or 27B indicate that data is output from the signal processing unit 118 to the output timing adjustment circuit at that time, but the position is not very precise and has a certain width because it is an output from the signal processing unit 118. As can be seen from the relationship with the figure, the output from the signal processing unit 118 in the case of the figure is normally output at a position halfway between the receiving clock RCLK. Looking at the figure, even though it is irregular, the interval between outputs from the signal processing unit 118 is almost equal to the interval between the receiving clock RCLK in most periods, and the interval deviates significantly only when there is no signal output or when two outputs are made in one period. For example, after _t7 in Fig. 27A and the second
_7B , for example. Although the intervals between the above outputs are nearly equal for most of the period, they are intervals synchronized with the receive clock RCLK, not with the transmit clock SCLK, so they must still be output at the exact timing of the transmit clock SCLK, as in FIG. 27A, etc., and there is a point in providing an output timing adjustment circuit.

28 is a diagram showing the configuration of an output timing adjustment circuit for satisfying the above requirements. As described above, this circuit is provided in place of the transmission register 113 in FIG. 20 of the second embodiment.

In the figure, register _R0 in signal processing section 118 is its output register, and normally the result of calculation by interpolation processing section 65 (FIG. 20) in signal processing section 118 is entered in this register. Then, signal processing section 118 outputs data output request pulse 179 indicating that it wants to output to the outside. In response to this, when the output timing adjustment circuit is able to input data, data transfer clock generation section 169 generates transfer clocks 181 of a number equal to the bit length of destination register _R1.
Based on this clock, the contents of register _R0 are output to register _R1 in the output timing adjustment circuit. If data input is not permitted in the data transfer time adjustment unit 168, the generation of the transfer clock 181 from the data transfer clock generation unit 169 is suppressed,
This means that data output from the signal processing unit 118 is awaited. However, if data is left stored in register _R0 , processing will stop when the next data is output to register _R0 in the signal processing unit 118. Therefore, care must be taken not to store data in register _R0 for too long.

The operation of the output timing adjustment circuit in Figure 28 is outlined below. The output signal is sent from register _R0 to register _R1 , and then to register _R2.
are transferred to the continuously connected circuit. After the signal is transferred from register _R0 to register _R1 , a selector 178 selects which of the signals in register _R1 or _R2 will be used as the output signal, and the signal is transferred in parallel to register _R3 . The signal in register _R3 is output as serial data output 187. Meanwhile, the transmission clock SCLK is input to transmission synchronization pulse output section 177, from which it is output as transmission synchronization pulse SYNC. The serial data output 187 and synchronization pulse SYNC are multiplexed and then output to the line as output signal SOUT (Fig. 20).

On the other hand, as for the control signal, first, the data output request pulse 179 is input from the signal processing unit 118 to the data transfer time (timing) adjustment unit 168 as described above. The transmission clock SCLK is also input to this circuit, and within the same circuit,
A transfer prohibition pulse synchronized with the transmission clock SCLK is generated. Then, the data transfer time adjustment unit 168 normally outputs a transfer instruction pulse 180 to the data transfer clock generation unit 169 immediately after the data output request pulse 179 is input. This causes the data transfer clock generation unit 169 to generate a transfer clock 181. On the other hand, the transfer prohibition pulse has a width, and if the data output request pulse 179 is input from the signal processing unit 118 during this time period, the data transfer time adjustment unit 168 does not generate a transfer instruction pulse 180 until the time period has elapsed, and as a result, the transfer clock 181
In other words, the signal input from the signal processing unit 118 is made to wait.
are applied to registers _R0 , _R1 , and _R2 , data is transferred from register _R0 to register _R1 to register _R2 . After the transfer is completed, a data transfer end pulse 182 is generated from a data transfer end pulse generator 170 so that a select signal generator 169 (described later) can count the number of transfer inputs within one period.

The select signal generating unit 171 performs the following operations during the time period when the transfer prohibition pulse is active.

That is, first, the number of signal inputs during the previous period is counted by the counter 17.
2, and further, the select signal 18 from the determination circuit 175
6 to itself. As a result, information as to which signal of register _R1 or _R2 was transferred to register _R3 during the previous period is fed back to the decision circuit 175 itself. Subsequently, the decision circuit 175 operates to calculate a select signal 186 for determining the direction of the selector 178 for the current period. The decision circuit 175 is started in synchronization with a decision circuit start pulse 183 from a decision circuit operation instruction pulse generator 174 which operates based on the transmission clock SCLK.

Next, to count the number of signal inputs in the next period,
The counter 172 is cleared by a counter clear signal 184 from the counter clear signal generating section 173. At the same time, the parallel load pulse 185 from the parallel load pulse generating section 176 clears the registers R _{1 and} R 2 according to the direction of the selector 178.
A signal from either one of registers R1 _{and R2} is transferred in parallel to register _R3 . After the signal transferred to register _R3 is transferred in parallel, a clock pulse (not shown) is immediately applied to the clock terminal, and the signal is output to the outside together with a transmission synchronization pulse SYNC.

The time chart for the above operation is shown in FIG.

Reference numeral 179 in the figure denotes a data output request pulse output from the signal processing unit 118, and the time interval between them is equal to the reception clock RC
It is approximately equal to the period length (R period) of LK.

On the other hand, the transfer inhibit pulse is generated in synchronization with the transmission clock SCLK inside the data transfer time adjustment unit 168. The pulse width must be long enough to complete three processes: serial transfer operation by the transfer clock 181, operation in the decision circuit by the decision circuit start pulse 183, and parallel transfer from registers _R1 / _R2 to _R3 by the parallel load pulse 185. Generally, since the transmission clock SCLK and the reception clock RCLK have slightly different frequencies, in most cases, even when R period > S period or when S period > R period, the first period is the same.
As in the case of I or II in FIG. 29, the data output request pulse 17
9 does not overlap with the transfer prohibition pulse. However, there is a certain probability that they may overlap as in the case of III in the same figure.
In the case of I, the transfer clock 181 is immediately generated from the data transfer clock generator 169, and the signal is transferred.
A transfer end pulse 182 indicating that the transfer has ended is generated from the data transfer end pulse generating unit 170.
When the data output request pulse 179 overlaps with the transfer inhibit pulse as in II, the transfer inhibit pulse becomes inactive as shown at 181 in Figure 29, and then the transfer clock 181 is output and data transfer begins. If there were no transfer inhibit pulse here, data transfer would occur immediately after the data output request pulse 179, and parallel transfers from register _{R1 and R2 to register R3 would occur during the transfer from register R0 → register R1 →} register _R2 . In this case, there is no guarantee what the contents of register _R3 will be.

As described above, the transfer inhibit pulse adjusts the signal input time from the signal processing unit 118 and transfers the data from register R ₁ /R ₂ to register R ₃
This prevents the signal from being destroyed by preventing the transfer time of the signal processor 118 from overlapping with the transfer time from the signal processor 118 to the registers _R1 and _R2 , and at the same time, it plays an extremely important role in preventing the transfer end pulse 182 in Fig. 29 from colliding with the decision circuit start pulse 183 or counter clear signal 184 in the same figure, thereby always accurately knowing the number of input signals in the previous period.

Next, a description will be given of the select signal generating circuit 171 for operating the selector 178. First, it is assumed that the relationship between the sign of the select signal 186 and each register is as follows, in accordance with an actual IC.

As mentioned above, the number of signal inputs in the previous period is three, 0, 1, and 2, and the sign of the select signal 186 in the previous period (0,
In combination with 1), a decision circuit is introduced in which the sign of the select signal 186 input to the selector 178 for the six cases is as follows:

In the above table, A is the select signal of the previous period, B is the number of signal inputs of the previous period, and C is the select signal (output) of the current period.
When the select signal 186 is 0, registers _R1 to _{R3 are}
The signal is transferred to the select signal 186.
This means that a signal is transferred from register _R2 to register _R3 .

When the signal input for the previous period is once per period (S period) based on the transmission clock SCLK (3rd and 4th rows in the table above)
Since the contents of both registers _R1 and _R2 are updated once by this input, continuous signal output can be obtained by outputting the signal of the same register as in the previous cycle without changing the sign of the selector signal.

Next, when the signal input in the previous S cycle is zero (rows 1 and 2 in the table above), the contents of the register remain the same as in the previous cycle. Therefore, if the select signal is the same as in the previous cycle, the same signal as in the previous cycle will be output to the outside, so if the select signal in the previous cycle was 1, it is changed to 0. When the select signal in the previous cycle was 0, there is nothing newer than the contents of register 1, so it remains 0. In this case, the same signal is output twice, causing a small disturbance in the output signal waveform.
However, even if this phenomenon occurs, it does not pose a problem because it occurs only once when the device is started up until a steady state is reached.

If there are two inputs in the previous S cycle (rows 5 and 6 in the table), the contents of the register are updated twice. Therefore, if the select signal is not changed, the signal obtained will be a new signal that is one step ahead of the signal output in the previous cycle. In this case, if the select signal in the previous cycle is 0, change it to 1 to ensure that the correct order of signals is stored in register 3.
However, if the select signal in the previous cycle is 1,
In this case, no signal older than the signal in register 2 is stored, so the select signal for the current cycle also remains at 1. In this case, a signal that has been skipped is output, but this phenomenon occurs only once or twice before the device reaches a steady state when it is operated.

The operation of the timing adjustment circuit described above will be explained with reference to Fig. 27A as follows. In the figure, and represent registers _{R1 and R2} , respectively.
These signal values are the values _S0 , T1, T2, ... to be calculated at the timings _T0 , _T1 , _T2 , ... based on the transmission clock SCLK in the processing data shown in the _figure .
These correspond to _S1 , _S2 , .... For example, in Figure 27A, _S5 is shown between _t5.5 and _t6.5 , which means that the output corresponding to timing _T5 based on the transmission clock SCLK is stored in register _R1 between _t5.5 and _t6.5 . Also, from the same figure, it can be seen that signal _S4 corresponding to _T4 is stored in register _R2 at the same time.

Furthermore, in Fig. 27A, looking at the periodic units (S periods) synchronized with the transmission clock SCLK from _T5 to _T6 , it can be seen that the previous output used signal _S3 from register _R2 (selector signal is 1) and, since there was one input in the previous period, the signal from register _R2 , i.e., signal _S4 corresponding to _T4 , is output at _T6 . Similarly, the previous output in the S periods from _T6 to _T7 also used signal _S4 from register _R2 and there was one input, so the signal from register _R2, i.e., signal _S5 corresponding to _T5 , is output at _T7 .

Since there is no input in the next S period from _T7 to _T8 , the contents of register _R1 remain unchanged as signal _S6 corresponding to _T6 , and register _R2
The contents of the signal _S5 corresponding to _T5 remain unchanged. However, in this case, the select signal generator 171 in FIG. 28 determines that there is no input signal, and the select signal changes to 0. At _T8, the signal of register _R1, that is, the signal corresponding to _T6,
S ₆ is output.

Furthermore, in the next S period from _T8 to _T9 , the signal is output twice, so at the time _T9 , the register _R2 stores the signal _S7 corresponding to _T7.
At this time, the select signal generating unit 171
The register determines that the two signal inputs and the previous select signal are 1 and changes the select signal to 1.
The signal _S7 corresponding to the signal _R2 , that is, _T7, is output.

In this way, the register _R3 outputs to the outside in an orderly manner.
Although the case where the period is greater than the R period was examined, the same applies to the case where the R period is greater than the S period in FIG. 27B.

The decision circuit 175 in FIG. 28 for realizing the logic shown in the table above can be realized with a small-scale circuit using a digital comparator or the like that operates together with the counter 172 for counting the number of signal inputs.

As described above, according to the fourth embodiment, first, the (transmission/reception) timing difference detection circuit employs a method of detecting the timing difference between the transmission clock SCLK and the reception clock RCLK by latching a counter synchronized with the transmission clock SCLK with the reception clock RCLK.
This eliminates the need for a buffer circuit (register), and also provides two advantages: the control circuit is greatly simplified, the circuit scale is reduced, and reliable operation is possible.

Regarding the output timing adjustment circuit, the introduction of a transfer inhibit pulse simplifies the control circuit while ensuring reliable operation. The circuit combining the selector signal generator and registers _R1 and _R2 minimizes the number of registers.
This is highly effective in reducing the circuit size.

As described above, the biggest problem in realizing a digital PCM channel unit is that the receive clock RCLK and the transmit clock SCLK are asynchronous, making it difficult to convert processing in the former system to processing in the latter system. However, this embodiment provides an optimal solution from the viewpoint of the scale of hardware and software, making it easy to implement in an LSI. Therefore, it is possible to realize the best digital PCM channel unit in terms of size, power consumption, reliability and cost.

──────────────────────────────────────────────────── Continued from the front page (56) References: Japanese Patent Application Publication No. 143023 (JP, A) Japanese Patent Application Publication No. 63-67913 (JP, A) Japanese Patent Application Publication No. 6958 (JP, A) Japanese Patent Application Publication No. 101112 (JP, A) Japanese Patent Application Publication No. 213409 (JP, A) Japanese Patent Application Publication No. 93748 (JP, A) Japanese Patent Application Publication No. 16773 (JP, B2) Japanese Patent Application Publication No. 39811 (JP, B2) U.S. Patent No. 4334237 (US, A) U.S. Patent No. 4460890 (US, A) U.S. Patent No. 4,780,892 (US, A) European Patent Application Publication No. 176,946 (EP, A) European Patent Application Publication No. 379,586 (EP, A)

Claims (13)

[Claims] 1. A signal processing device for encoding and decoding between analog and digital signals, comprising: a first input signal and a second input signal;
an A/D conversion means for converting a digital input signal separately in a first and a second A/D conversion system, calculating the average value of the conversion results, and obtaining a digital output signal; a D/A conversion means for converting a digital input signal separately in a first and a second D/A conversion system, detecting a quantization error occurring in the first D/A conversion system and adding it to the digital input signal to the second D/A conversion system, and mixing the conversion results of the first and second D/A conversion systems at a predetermined ratio to obtain an analog output signal; and operating the A/D and D/A conversion means in synchronization with a reception clock of a digital reception signal received from an external line, and performing signal processing on the digital output signal to the A/D conversion means and the digital reception signal on the line side.
a digital signal processing means for obtaining a digital output signal for transmission synchronized with the digital input signal and the receiving clock; and a digital signal clock transfer means for high-sampling the digital output signal for transmission synchronized with the receiving clock, detecting a timing difference between the receiving clock and the transmitting clock, and generating a digital transmission signal synchronized with the transmitting clock from the high-sampling data by interpolation based on the timing difference. [Claim 2] A signal processing device according to claim 1, wherein the A/D conversion means and the D/A conversion means are configured using two PCM CODECs that perform 8-bit companding encoding and decoding, and the digital signal processing means and the digital signal clock transfer means are configured using a DSP (Digital Signal Processor). [Claim 3] An A/D conversion device for converting an analog input signal into a digital output signal, comprising: first and second amplifiers for amplifying the analog signal with different gains, first and second companding D/A converters for converting the outputs of the first and second amplifiers into digital signals, and calculation means for calculating the average value of each of the digital signals. 4. A D/A conversion device for converting a digital input signal into an analog output signal, comprising: a first and a second companding D/A conversion system for converting the digital input signal separately; a quantization error occurring in the first companding D/A conversion system for amplifying the quantization error and adding it to the digital input signal to the second companding D/A conversion system; and a first and a second companding D/A conversion system for converting the digital input signal into an analog output signal.
A signal processing device comprising a companding D/A conversion means for mixing the results of each conversion in an A conversion system at a predetermined ratio to obtain an analog output signal. [Claim 5] An A/D conversion device that converts an analog input signal into a digital output signal, comprising: first and second amplification means that respectively multiply the analog input signal by K1 and K2, where K1 is a real number that satisfies K1>1 and K2 is a real number that satisfies K2×K1=1; first and second companding A/D conversion means that convert each amplified output of each amplification means into first and second digital signals, respectively; and calculation means that calculates an average value of the first and second digital signals and outputs a digital output signal. 6. A D/A conversion device for converting a digital input signal into an analog output signal, comprising: first conversion means for converting said digital input signal into a first quantized digital signal; first D/A conversion means for converting said first quantized digital signal into a first analog signal; and a first D/A conversion means for converting said first analog signal into a K3 quantized digital signal, where K3 is a real number greater than 0.
a first amplifier means for multiplying the quantization error by K5, where K5 is a real number that satisfies K5 + K3 = 1; and an adder means for adding the amplified outputs of the first and second amplifier means to output an analog output signal. Claim 7: Companding D/A converter and DSP (Digital Signal Processor)
an A/D converter including a first amplifier and a second amplifier for amplifying the analog input signal by K1 and K2, respectively, where K1 is a real number satisfying K1>1 and K2 is a real number satisfying K2×K1=1; and a first amplifier and a second companding PCM processor for amplifying the amplified outputs of the amplifiers, respectively.
a first and second companding A/D conversion means for converting the first and second companding PCM codes into first and second linear signals, respectively; and a calculation means for calculating an average value of the first and second linear signals to output a digital output signal, wherein the first and second linear conversion means and the calculation means are formed within the DSP. Claim 8: A companding D/A converter and a DSP (Digital Signal Processor)
a digital-to-analog converter (D/A converter) that converts a digital input signal consisting of a linear PCM code into a first companding P
a first companding means for converting the first companded PCM code into a first analog signal;
a companding D/A conversion means for converting the first analog signal into K3, where K3 is a real number greater than 0;
a first amplifier means for multiplying the quantization noise by K4, where K4 is a real number satisfying K4=K3/(1-K3), and adding the multiplied quantization noise to the digital input signal; a noise adder means for multiplying the quantization noise by K4 and adding the multiplied quantization noise to the digital input signal; a second companding converter means for converting the output of the noise adder means into a second companded PCM code; and a second companding converter means for converting the second companded PCM code into a second analog signal.
a companding D/A converting means; a second amplifying means for multiplying said second analog signal by K5, where K5 is a real number that satisfies K5+K3=1; and an adding means for adding the amplified outputs of said first and second amplifying means to output an analog output signal, wherein said first and second companding converting means, said detecting means, and said noise adding means are formed within said DSP. Claim 9: A companding A/D converter, a companding D/A converter, and a DSP (Dig
a first and second amplifier means for multiplying the analog input signal by K1 and K2, respectively, where K1 is a real number satisfying K1>1 and K2 is a real number satisfying K2×K1=1; and a first and second companding PCM signal processing means for converting the amplified outputs of the amplifier means into the first and second companding PCM signals, respectively.
an A/D conversion device including first and second companding A/D conversion means for converting the first and second companding PCM codes into first and second linear signals, respectively; first and second linear conversion means for converting the first and second companding PCM codes into first and second linear signals, respectively; and calculation means for calculating average values of the first and second linear signals and outputting a digital output signal;
a first companding means for converting the first companded PCM code into a first analog signal;
a companding D/A conversion means for converting the first analog signal into K3, where K3 is a real number greater than 0;
a first amplifier means for multiplying the quantization noise by K4, where K4 is a real number satisfying K4 = K3/(1 - K3), and adding the multiplied quantization noise to the digital input signal; a noise adder means for multiplying the quantization noise by K4 and adding the multiplied quantization noise to the digital input signal; a second companding converter means for converting the output of the noise adder means into a second companded PCM code; and a second companding converter means for converting the second companded PCM code into a second analog signal.
a companding D/A conversion device including: companding D/A conversion means; second amplification means for multiplying the second analog signal by K5, where K5 is a real number that satisfies K5+K3=1; and addition means for adding the amplified outputs of the first and second amplification means to output an analog output signal, wherein the first and second companding A/D converters and the first and second companding D/A converters are configured as one companding A/D converter and one companding D/A converter.
A signal processing device comprising two PCM CODECs each having a D/A converter formed integrally therewith, wherein the first and second linear conversion means, the calculation means, the first and second companding means, the detection means, and the noise addition means are formed within the DSP. 10. A digital signal clock transfer device for converting a first digital data sequence synchronized with a first clock into a second digital data sequence synchronized with a second clock, comprising: data conversion means for converting the first digital data sequence into a data sequence having n times the number of data per unit time of the original data, where n is a natural number greater than 1; a high sampling digital low pass filter operating at a sampling rate n times the first clock for filtering the data sequence from said conversion means; timing difference detection means for detecting a timing difference between said first and second clocks; interpolation means for linearly interpolating the output of said high sampling digital low pass filter based on the timing difference from said timing difference detection means and outputting it as amplitude data for said second digital data sequence; and output timing adjustment means for synchronizing the amplitude data with said second clock and outputting it as said second digital data sequence, wherein said high sampling digital low pass filter is comprised of a plurality of blocks whose ratio of sampling rates is an integer, a data conversion means provided between said blocks for inputting each input data to each block and outputting data of the same amplitude as said input data, the number of which is equal to the ratio of the sampling rates of adjacent blocks; and a signal processing apparatus characterized in that the data conversion means for inputting said first digital data series inputs each data and outputs data of the same amplitude as said input data, the number of which is equal to the ratio of the sampling rate of the first block to the rate of said first clock. 11. A digital signal/clock transfer device for converting a first digital data series synchronized with a first clock into a second digital data series synchronized with a second clock, comprising: data conversion means for converting the first digital data series into a data series having n times the number of data per unit time of the original data, where n is a natural number greater than 1; a high sampling digital low pass filter operating at a sampling rate n times that of the first clock for filtering the data series from the conversion means; timing difference detection means for detecting a timing difference between the first and second clocks; interpolation means for linearly interpolating the output of the high sampling digital low pass filter based on the timing difference from the timing difference detection means and outputting it as amplitude data for the second digital data series; and output timing adjustment means for synchronizing the amplitude data with the second clock and outputting it as the second digital data series, wherein the timing difference detection means comprises: counter means operating on a system clock synchronized with the first clock and having a frequency which is an integer multiple of the frequency of the first clock; and latch means for latching the count value of the counter means in synchronization with the second clock, wherein the interpolation means detects the count value latched for each period synchronized with the first clock as a phase difference between the first clock and the second clock, and calculates and outputs the amplitude data based on the phase difference and the output of the high sampling digital low pass filter. 12. The apparatus according to claim 11, wherein said interpolation means, for each period synchronized with said first clock, does not output said amplitude data in the current period when, as a first case, the phase difference in the previous period is a value near zero and the phase difference in the current period is a value near the period of said second clock, and, as a second case, when the phase difference in the previous period is a value approximately near the period of said second clock and the phase difference in the current period is a value near zero, outputs as said second digital data series in the current period a value corresponding to the first value of the current period among the output of said high sampling digital low pass filter,
a signal processing apparatus which outputs a value corresponding to the last value of the current period as two consecutive amplitude data, and in a third case, in cases other than the first and second cases, interpolates the output of the high sampling digital low pass filter based on the phase difference and outputs the interpolated output as the amplitude data. 13. The apparatus according to claim 12, wherein said output timing adjustment means comprises: first temporary storage means connected to the output side of said interpolation means; transfer control means for transferring amplitude data stored in said first temporary storage means to second temporary storage means cascade-connected to the output side of said first temporary storage means and for transferring amplitude data stored in said first temporary storage means to said second temporary storage means; data transfer time adjustment means for inputting an output request for said amplitude data from said interpolation means operating in a cycle synchronized with said first clock, determining whether or not the input timing of said output request overlaps with a prohibited time which is a predetermined time slot in each cycle synchronized with said second clock, and instructing said transfer control means to perform said transfer operation if said output request timing does not overlap with said prohibited time, and instructing said transfer control means to perform said transfer operation after the prohibited time has elapsed if said output request timing overlaps with said prohibited time; selection means for selecting said amplitude data stored in either said first or second temporary storage means; and third temporary storage means for temporarily storing amplitude data from said selection means and interfacing with an external line. a selection control means for controlling the selection means in synchronization with each period based on the second clock; and a counting means for counting the number of times the amplitude data is input from the interpolation means in each period based on the second clock, wherein the selection control means determines selection information for a current period from a counter value from the counter means at that time and selection information output by the selection control means itself in the period in synchronization with each period, and outputs the selection information to the selection means to control the selection means.