JPH07115201A - Thin film transistor manufacturing equipment - Google Patents

Abstract

(57) [Abstract] [Purpose] Without increasing the number of impurity ion implantations,
Provided is a thin film transistor manufacturing apparatus with excellent productivity and excellent OFF characteristics. [Structure] After forming a gate electrode 3 and implanting impurity ions, the semiconductor layer 1 is divided into a plurality of regions by irradiating an energy beam obliquely from above while rotating the substrate. (Fig. 1 (f))

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for manufacturing a thin film transistor used for a non-linear element in an active matrix type liquid crystal display (LCD), a circuit element constituting a driving circuit or the like.

[0002]

2. Description of the Related Art In recent years, thin film transistors (TFTs) have been used for application to image display devices such as flat panel displays.
The characteristics of thin film transistors used in the above-mentioned active matrix type liquid crystal display device, etc. are high in mobility and the ratio of ON current / OFF current (ON / OFF current). Characteristics, high breakdown voltage, and reduction in element size are required.

Among them, the polycrystalline semiconductor TFT has advantages such as high performance and high reliability as compared with the case of using an amorphous semiconductor film, but on the other hand, there is a disadvantage that a high temperature is required for film formation. Remaining. For this reason, research and application of a crystallization technique of an amorphous semiconductor film by laser light irradiation capable of obtaining a polycrystalline semiconductor film without obtaining a high temperature process have been actively conducted.

Further, when a thin film transistor is formed by using a polycrystalline semiconductor thin film, although a relatively large value of ON current is obtained, many trap levels are localized in the polycrystalline semiconductor thin film. A considerable amount of OFF current flows through this trap level, which deteriorates the data retention characteristic. Therefore, there is an urgent need to keep the OFF current small.

Therefore, in order to realize a high ON current / OFF current ratio and a high breakdown voltage of the TFT, a source / drain region of the thin film transistor is provided on the side close to the gate electrode with a low impurity concentration region of the same conductivity type, Attempts have been made to reduce the OFF current by relaxing the electric field concentration at the PN junction formed between the source region and the drain region.

Conventionally, in order to form such a low impurity concentration region (impurity low activation region), a method of forming a sidewall on a side surface of a gate and performing impurity ion implantation,
A method of patterning a film for limiting the implantation amount by using a mask pattern dedicated to the implantation of impurity ions and implanting the impurity ions, or as disclosed in Japanese Patent Publication No. 38755/1993, an offset region is formed. For example, a method of implanting impurity ions into the thin film transistor included therein has been adopted.

In the case of forming a region in which impurities are implanted at a low concentration by the above method, the following process can be considered.

The first method is to form a sidewall on the side surface of the gate electrode and use the gate electrode and the sidewall as a mask for implanting impurity ions. This manufacturing process will be described with reference to FIG. First, a semiconductor layer 1 and a gate insulating film 2 are sequentially formed on a substrate as shown in FIGS. 2A and 2B, and a gate electrode 3 is formed as shown in FIG. As shown in FIG. 2D, the gate insulating film 2 is patterned by etching, leaving only the lower part of the gate electrode 3. Then, FIG.
As shown in (e), using the gate electrode 3 as a mask, the first ion implantation is performed on the semiconductor layer 1 using impurity ions, and then an insulating film 6 is deposited on the substrate as shown in FIG. 2 (f). As shown in FIG. 2G, the sidewall 1 is formed around the gate insulating film 2 and the gate electrode 3 by etch back.
Form 0. Then, using the gate electrode 3 and the sidewall 10 as a mask, the second ion implantation is performed on the semiconductor layer 1 using the impurity ions of the same conductivity type as the impurity ions used in the first ion implantation. As a result, the channel region 17 is formed in a portion of the semiconductor layer 1 that faces the gate electrode 3 and is not implanted with impurity ions, and the low-concentration impurity regions 4 are formed in portions on both sides adjacent to the channel region 17. High-concentration impurity regions 5 are formed on both outer sides of the low-concentration impurity regions 4 adjacent to the low-concentration impurity regions 4.

The second method uses the resist film as a mask in the step of implanting impurity ions. This manufacturing process is shown in FIG. As shown in FIGS. 3A to 4E, the first ion implantation is performed in the same manner as in the first method, and then the substrate is covered with the ion implantation mask 9 as shown in FIG. 3F. And the ion implantation mask 9 is patterned using the resist pattern. Then, Figure 3
As shown in (g), using the ion implantation mask 9 as a mask, impurity ions of the same conductivity type as the impurity ions used in the first ion implantation are used to perform second ion implantation in the semiconductor layer 1. As a result, the gate electrode 3 is formed on the semiconductor layer 1.
The channel region 17 is formed in a portion facing each other, the low-concentration impurity regions 4 are formed in both side portions adjacent to the channel region 17, and both outer side portions adjacent to the low-concentration impurity region 4 are formed. High concentration impurity region 5 is formed.

The third method is to form an offset gate region, which is described in Japanese Patent Publication No. 3-38755. This manufacturing process is shown in FIG. First, FIG.
As shown in FIG. 4A, the semiconductor layer 1 is formed on the substrate, and then, as shown in FIG. 4B, an ion implantation mask 9 is formed on the semiconductor layer 1 so as to cover the gate electrode formation portion.
Subsequently, using the ion implantation mask 9 as a mask, impurity ions are used for the first ion implantation, and then FIG.
The ion implantation mask 9 is removed as shown in FIG.
The gate insulating film 2 is formed as shown in (d). next,
As shown in FIG. 4E, the gate electrode 3 is formed, and then, using the gate electrode 3 as a mask, the impurity ions of the same conductivity type as the impurity ions used in the first impurity ion implantation are used to form the semiconductor layer 1 in the semiconductor layer 1. A second ion implantation is performed. As a result, the channel region 17 is formed in the semiconductor layer 1 in the portion facing the gate electrode 3, and the low-concentration impurity regions 4 are formed in the portions adjacent to the channel region 17 on both sides. High-concentration impurity regions 5 are formed on both outer side portions adjacent to the region 4.

The fourth method is to implant impurity ions in a state where a contact hole is provided in the interlayer insulating film. This manufacturing process is shown in FIG. As shown in FIGS. 5A to 5D, after the first ion implantation is performed in the same manner as the first method, the insulating film 6 is formed to cover the substrate as shown in FIG. 5E. Then, after the contact hole 7 is formed by patterning the insulating film 6, an impurity having the same conductivity type as the impurity ion used in the first ion implantation is used with the insulating film 6 as a mask as shown in FIG. 5F. A second ion implantation is performed on the semiconductor layer 1 using ions. This allows
Since the portion of the semiconductor layer 1 in which the contact hole 7 is formed is not covered with the insulating film 6, a channel region 17 is formed in the portion of the semiconductor layer 1 facing the gate electrode 3, and both sides of the channel region 17 adjacent to the channel region 17 are formed. The low-concentration impurity regions 4 are formed in the portions, and the high-concentration impurity regions 5 are formed in both outer portions adjacent to the low-concentration impurity regions 4.

[0012]

However, the above-mentioned first to fourth conventional methods have the following problems.

First, in the first method, two steps of burying the insulating film 6 for forming the sidewall 10 and etching back are required, and the ion implantation step must be performed twice. .

In the second method and the third method,
In order to form the resist film, it is necessary to perform patterning with a resist pattern and to form a coating film, and similarly to the first method, the ion implantation step must be performed twice.

Also in the fourth method, similarly, the ion implantation step must be performed twice.

As described above, the conventional method as described above requires two ion implantation steps, and a separate mask for ion implantation must be formed. Therefore, the number of manufacturing steps is large and complicated, and the resulting TFT
However, there is a problem that the manufacturing cost of the product becomes high.

The present invention is intended to solve the above problems, and an object of the present invention is to provide a thin film transistor manufacturing apparatus capable of reducing the number of steps in manufacturing a thin film transistor.

[0018]

In the thin film transistor manufacturing apparatus of the present invention, a semiconductor layer provided with a gate insulating film sandwiched between a gate electrode is divided into a plurality of regions, and the gate of the semiconductor layer is divided into a plurality of regions. A channel region is formed in a portion facing the electrode, and a semiconductor region having low impurity activity is formed in at least one of both side portions adjacent to the channel region. The semiconductor region having low impurity activity is surrounded by the channel region and the semiconductor region having low impurity activity. After the semiconductor film, the gate insulating film, and the gate electrode are sequentially formed in a thin film transistor manufacturing apparatus in which a semiconductor region having a high impurity activity is formed on both sides adjacent to each other, impurity ions are implanted. In particular, the semiconductor layer is divided into a plurality of regions by irradiating the surface of the substrate with an energy beam obliquely from above while rotating the substrate. And to have the above objects can be achieved.

Also, the thin film transistor manufacturing apparatus may be characterized in that the energy beam is a laser beam.

[0020]

In the thin-film transistor manufacturing apparatus of the present invention, an intrinsic semiconductor film, a gate insulating film, and a gate electrode are formed on an insulating substrate or a substrate having an insulating film on the surface, and impurity ions are implanted, followed by insulation. The energy beam is applied obliquely from above while rotating the flexible substrate. Therefore,
After implanting the impurity ions, by irradiating the energy beam obliquely from above while rotating the insulating substrate, activation annealing is performed, and at the same time, the source / drain regions near the gate electrode have the same conductivity type. It is possible to provide a low-activation region, and it is possible to reduce the OFF current. That is, in the low activation region, all of the implanted impurity ions do not sufficiently act as donors and acceptors, resulting in a low concentration region,
It has an LDD structure in appearance. Therefore, it is possible to simultaneously form regions having different impurity concentrations by one-time implantation of impurity ions, and it is possible to omit the steps of film deposition and patterning for limiting the amount of impurity implantation. Also, a dedicated pattern is not required at the time of implanting impurity ions. In particular, by using the laser among the energy beams, only the Si layer can be selectively and efficiently heated, which enables annealing at a low temperature and enables the use of an inexpensive glass substrate.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a manufacturing process in a thin film transistor manufacturing apparatus of the present invention. Figure 1
As shown in (i), in the thin film transistor obtained in this example, the semiconductor layer 1 is formed on the substrate, and the gate electrode 3 is formed on the semiconductor layer 1 with the gate insulating film 2 interposed therebetween. It is provided. The semiconductor layer 1 is divided into five regions, a channel region 17 is formed in a portion facing the gate electrode 3, and low activation impurity regions 4 are formed in portions on both sides adjacent to the channel region 17. Highly activated impurity regions 5 are formed on both outer side portions adjacent to the lowly activated impurity region 4. A contact hole 7 is provided in a portion of the insulating film 6 above the highly activated impurity region 5.

The thin film transistor having the above-mentioned structure is manufactured as follows.

First, as shown in FIG. 1A, an i-Si film (intrinsic silicon film) is deposited to a thickness of about 300 to 1500 angstroms on a substrate or a substrate on which an insulating film is deposited, After that, the island-shaped semiconductor layer 1 is formed by patterning. Then, as shown in FIG. 1B, the gate insulating film 2 made of SiO ₂ or the like is applied to about 1000.
It is deposited to a thickness of about angstrom, and as shown in FIG. 1C, n is formed as a gate electrode 3 on the gate insulating film 2.
-Type or p-type impurity-implanted Si, Ta, N
It is formed to a thickness of about 2000 angstroms using a metal such as b or Al. Subsequently, as shown in FIG. 1D, the gate insulating film 2 is etched into the pattern of the gate electrode 3 by photolithography.

Next, as shown in FIG. 1E, impurity ions are implanted by ion implantation onto the semiconductor layer 1 made of the i-Si film using the gate electrode 3 and the gate insulating film 2 as masks. . Ion implantation conditions include phosphorus (P)
And a trivalent element typified by boron (B) with an acceleration voltage of 10 to 70 KV and a doping amount of 1 ×
Doping was performed under the conditions of 10 ¹⁵ / cm ² to 1 × 10 ¹⁷ / cm ² . As a result, the channel region 17 is formed in the portion of the semiconductor layer 1 covered with the gate insulating film 2 and the gate electrode 3, and the source / drain regions containing impurities are formed in the exposed portion.

Then, as shown in FIG. 1 (f), while rotating the insulating substrate, the insulating substrate is obliquely above the gate electrode 3 from above.
KrF (krypton fluoride) laser light of 100 to 200 mj is focused and irradiated in a square of about 10 mm to activate the impurity ions in the source / drain regions. Regarding the laser light to be irradiated, instead of the KrF laser, Xe
Irradiation with an energy beam using another gas such as a (xenon) laser is also possible. In this way, by irradiating the energy beam obliquely from above while rotating the insulating substrate, the gate electrode 3 in the source / drain region is
Since a shadow due to the gate insulating film 2 and the gate electrode 3 is formed in a portion close to, the irradiation amount of the energy beam is reduced, and a low activation impurity region 4 having the same conductivity type as the source / drain regions is formed. A highly activated impurity region 5 is formed in the outer portion.

Although the insulating substrate is rotated in this embodiment, the laser light irradiation port may be rotated, or both of them may be rotated.

Next, as shown in FIG. 1G, as the interlayer insulating film 6, SiNx, SiO ₂ or the like 3000-4.
After being deposited to a thickness of about 000 Å to cover the entire substrate, the insulating film 6 is etched by using a mask pattern for forming a contact hole as shown in FIG. A contact hole 7 is formed on the formation portion of the highly activated impurity region 5 (source / drain region). Subsequently, as shown in FIG. 1 (i), source / drain electrodes 8 are formed in the contact hole 7 formation portion with a metal such as Al or Mo or a conductive material such as ITO to complete a thin film transistor.

FIG. 6 is a schematic diagram showing the construction of the main part of the thin-film transistor manufacturing apparatus used in this embodiment, particularly the energy beam irradiation.

This apparatus comprises a chamber 13 having a quartz window 14 and a vacuum exhaust system 15 for the chamber 13.
Laser system 1 for irradiating laser light into the chamber 13
It consists of 6. A rotation stage for fixing the insulating substrate 11 and a substrate holder 12 installed therein are built in the chamber 13. The laser system 16 is KrF
A laser oscillator 16a for generating an energy beam such as a laser beam, and mirrors 16b, 16c, 16d
And a beam homogenizing mechanism 16e.

[0030]

As is apparent from the above description, according to the thin film transistor manufacturing apparatus of the present invention, it is possible to simultaneously form regions having different impurity concentrations by a single implantation of impurity ions. It is possible to omit the steps of film deposition and patterning for limiting the amount of impurity implantation, and since a dedicated pattern is not required at the time of implanting impurity ions, the productivity is high and the ON / O
A thin film transistor having a large FF current ratio can be obtained. .

In particular, by using a laser among the energy beams, only the Si layer can be selectively and efficiently heated, which enables annealing at a low temperature and enables the use of an inexpensive glass substrate. became.

[Brief description of drawings]

FIG. 1 is a drawing showing a manufacturing process of a thin film transistor according to the present invention.

FIG. 2 is a drawing showing a manufacturing process of a thin film transistor in a first conventional method.

FIG. 3 is a drawing showing a manufacturing process of a thin film transistor in a second conventional method.

FIG. 4 is a drawing showing a manufacturing process of a thin film transistor in a third conventional method.

FIG. 5 is a drawing showing a manufacturing process of a thin film transistor in a fourth conventional method.

FIG. 6 is a schematic configuration diagram showing a configuration of main parts of a semiconductor manufacturing apparatus according to an embodiment of the present invention.

[Explanation of symbols]

1 semiconductor layer 2 gate insulating film 3 gate electrode 4 low activation impurity region (semiconductor region with low impurity activity) 5 high activation impurity region (semiconductor region with high impurity activity) 6 insulating film 7 contact hole 8 source -Drain electrode 9 Ion implantation mask (film for limiting impurity implantation amount) 10 Side wall 11 Insulating substrate 12 Rotating stage and substrate holder installed on it 13 Chamber 14 Quartz window 15 Vacuum exhaust system 16 Laser system 16a Laser oscillator 16b Mirror 16c Mirror 16d Mirror 16e Beam homogenization mechanism 17 Channel region

Claims (2)

[Claims] 1. A semiconductor layer provided with a gate insulating film interposed therebetween is divided into a plurality of regions with respect to a gate electrode, and a channel region is formed in a portion of the semiconductor layer facing the gate electrode.
A semiconductor region having a low impurity activity is formed on at least one of both side portions adjacent to the channel region, and an impurity activity level is formed on both side portions adjacent to the channel region and the semiconductor region having a low impurity activity. In a thin-film transistor manufacturing apparatus in which a high semiconductor region is formed, the semiconductor film, the gate insulating film, and the gate electrode are sequentially formed, impurity ions are implanted, and then the substrate, the energy beam irradiation port, or both of them. An apparatus for manufacturing a thin film transistor, characterized in that the semiconductor layer is divided into a plurality of regions by irradiating the surface of the substrate with an energy beam obliquely from above while rotating the substrate. 2. The thin film transistor manufacturing apparatus according to claim 1, wherein the energy beam is a laser beam.