JPH07109370B2 - Waveform storage - Google Patents

Description

TECHNICAL FIELD The present invention relates to a waveform storage device used in a recorder, a digital oscilloscope, a waveform analysis device, and the like.

2. Description of the Related Art FIG. 3 shows the configuration of a conventional waveform storage device, which is described in Japanese Patent Publication No. 58-47661.

In FIG. 3, when an analog signal is input, it is converted into n-bit digital data by the analog-digital converter 2 in the cycle of the sample clock generated by the sample clock generator 1, and this digital data is converted into two digital comparators 3. Thus, the maximum value and the minimum value up to the previous time recorded in the two latches 4 are compared.

When the digital data is larger than the maximum value up to the previous time recorded in the latch 4 or smaller than the minimum value up to the previous time, the digital comparator 3 notifies the control logic 5 to that effect, and the control logic 5 The latch 4 to be updated is strobed (signals MAX, MIN) and the new maximum or minimum value is stored in the latch 4.

This operation is repeated in the cycle of the sample clock generated by the sample clock generator 1, and the data in the latch 4 is updated each time a new maximum value or minimum value is detected. That is, the digital comparator 3 and the latch 4 constitute a digital peak detector, and this digital peak detector operates at the cycle of the sample clock generated by the sample clock generator 1.

The recording clock generator 6 updates the address counter 7 by generating a clock pulse having a slower speed than the sample clock generated by the sample clock generator 1,
The memory 8 stores the maximum value and the minimum value stored in the latch 4 in the address area indicated by the address counter 7.
The recording clock generator 6 also updates the control logic 5, and the control logic 5 resets the two latches 4 to restart detection of new maximum and minimum values.

Therefore, in the above conventional example, since the maximum value and the minimum value are stored at a speed slower than the speed at which the maximum value and the minimum value are detected,
The memory 8 having a small capacity can store long-time waveform data.

However, in the above conventional waveform storage device, the digital peak detector including the digital comparator 3 and the latch 4 generates the operation speed of the analog-digital converter 2, that is, the sample clock generator 1. Since the sample clock must operate at the same speed as the sample clock, the digital comparator 3 and the like become expensive when the sample clock is high speed.

In view of the above-mentioned conventional problems, it is an object of the present invention to provide a waveform storage device capable of detecting the maximum value and the minimum value of a signal with an inexpensive structure.

Means for Solving the Problems In order to achieve the above object, the present invention sequentially detects digital data and detects a maximum value or a minimum value, and a maximum value or a minimum value detected by the detecting means. A means for storing the value and a means for detecting the true maximum value or the minimum value of the input signal based on the maximum value or the minimum value stored by the storage means are provided.

Operation According to the present invention, when the number of the means for detecting the maximum value or the minimum value is m, the operating speed of the detecting means is 1 / m of the frequency of the sampling clock.
It is possible to detect the maximum value and the minimum value of the signal with an inexpensive configuration.

Embodiments Embodiments of the present invention will be described below with reference to the drawings. First
1 is a block diagram showing an embodiment of a waveform storage device according to the present invention, and FIG. 2 is a timing chart showing main signals in the waveform storage device of FIG.

In FIG. 1, reference numeral 21 denotes an analog signal input terminal, 22
Is a sample clock generator for generating a sample clock as shown in FIG. 2 (a), and 23 is an analog signal input through the input terminal 21 as shown in FIG. 2 (b).
This is an analog-digital converter that converts into n-bit digital data at the cycle of the sample clock from the sample clock generator 22, and the digital data from the analog-digital converter 23 is converted into digital peak detectors 25-
Distributed to 27.

Reference numeral 24 is a control logic for controlling the digital peak detectors 25 to 27, 30 and the recording clock generator 30 by the sample clock from the sample clock generator 22, and the recording clock generator 30 is a digital peak as described later. Generates timing signals to the detectors 25-27, 30 and
As shown in FIG. 2 (c), the address counter 28 is updated by generating clock pulses that are an integral multiple of the period of the sample clock.

The address counter 28 generates the address of the memory 29 in response to the clock pulse from the recording clock generator 30, and the memory 29 uses the address from the address counter 28 at the timings shown in FIGS. The data from the digital peak detectors 25 to 27 is recorded and output to the digital peak detector 30.

Here, the digital peak detectors 25 to 27 and 30 are respectively a digital comparator 3 and a latch 4 as shown in FIG.
It is composed of

Next, the operation of the above embodiment will be described.

In FIG. 1, the analog-digital converter 23 has a second
The instantaneous value of the analog signal as shown in FIG. 9B is converted into n-bit digital data at the cycle of the sample clock and output.

The control logic 24 outputs a timing signal having a cycle three times as long as the sample clock from the sample clock generator 22 to the digital peak detectors 25 to 27. Values or minimum values are sequentially detected and output to the memory 29.

The memory 29 stores the address from the address counter 28, that is, the maximum value detected by each of the digital peak detectors 25 to 27 at the timing of an integral multiple of the cycle of the sample clock, as shown in FIGS. Alternatively, the minimum value is stored and sequentially output, and the digital peak detector 30 is
The maximum value or minimum value of the data sequentially read from 29 is detected and output to a display or the like.

Therefore, according to the above embodiment, since the digital data converted by the analog-digital converter 23 is sequentially distributed to the three digital peak detectors 25 to 27, the operating speed of the digital peak detectors 25 to 27 is analog to digital. 1/3 of the operating speed of the converter 23 is sufficient, therefore
It can be configured with an inexpensive circuit as compared with the conventional example.

Further, in the above embodiment, the memory 29 is the memory 8 of the conventional example.
Since it has a capacity of 3 times the capacity, it is possible to store a capacity of 3 times when the maximum value or the minimum value is not detected. Therefore, the maximum value or the minimum value of the data read from the memory 29 is By detecting with the digital peak detector 30, the maximum value or the minimum value of the signal can be compressed and displayed.

As described above, according to the present invention, a plurality of detecting means for sequentially capturing digital data and detecting a maximum value or a minimum value, and a means for storing the maximum value or the minimum value respectively detected by the detecting means. And a means for detecting the true maximum value or minimum value of the input signal based on the maximum value or minimum value stored by this storage means, so that the number of means for detecting the maximum value or minimum value is m , The operating speed of this detection means is 1 / m of the frequency of the sampling clock,
Therefore, the maximum value and the minimum value of the signal can be detected with an inexpensive configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a waveform storage device according to the present invention, FIG. 2 is a timing chart showing main signals in the waveform storage device of FIG. 1, and FIG. 3 is a conventional waveform storage device. It is a block diagram which shows an apparatus. 22 …… Sample clock generator, 23 …… Analog digital converter, 24 …… Control logic, 25 to 27,30 …… Digital peak detector, 28 …… Address counter, 29 ……
Memory, 30 ... Recording clock generator.

Claims (2)

[Claims] 1. A digital conversion means for sampling an input signal and converting it into digital data, and a plurality of detection means for sequentially taking in the digital data converted by the digital conversion means and detecting a maximum value or a minimum value, A waveform having means for storing the maximum value or minimum value detected by the detection means, and means for detecting the true maximum value or minimum value of the input signal by the maximum value or minimum value stored by the storage means. Storage device. 2. The waveform storage device according to claim 1, wherein the storage means stores the maximum value or the minimum value at a speed slower than the sampling speed of the digital conversion means.