JPH0697740B2 - Semiconductor drive circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit in a semiconductor device, and more particularly, to a bipolar transistor and an insulated gate electric field suitable for obtaining a high driving ability and a pulse output amplitude greater than a power supply voltage. The present invention relates to a drive circuit using an effect transistor.

[Background of the Invention]

As a conventional driving circuit, there is a circuit disclosed in Japanese Patent Laid-Open No. 59-25423. This circuit is shown in FIG. 1, and its operation and its problems will be described. In the following description, the potential V _{SS of the} power supply 9 is 0V. When the potential of the input terminal 1 is 0V, the p-channel insulated gate field effect transistor 4 becomes conductive, a current flows through the base of the first npn bipolar transistor 7, and the first npn bipolar transistor 7 becomes conductive. On the other hand, the second npn bipolar transistor 8 does not conduct because the base potential is 0V. As a result, a current flows to the output terminal 2 and the potential of the output terminal 2 rises. The potential of the output terminal 2 varies from the voltage V _CC of the positive power supply 3 to the base-emitter forward voltage V of the first npn bipolar transistor 7.
The voltage of input terminal 1, which is the value obtained by subtracting _BE , is the positive power supply V
_When switched to _CC , the voltage of the output terminal 2 is initially V _CC -V _BE , so that the n-channel insulated gate field effect transistor 6 is conducting, and a current flows to the base of the second npn bipolar transistor 8 to output. Attempt to pull down the terminal of terminal 2. On the other hand, the p-channel insulated gate field effect transistor 4 becomes non-conductive, the base current of the first pnp bipolar transistor 7 stops flowing, and the n-channel insulated gate type transistor 5 becomes conductive.
The electric charge accumulated in the base of the npn bipolar transistor 7 is extracted by the n-channel insulated gate field effect transistor, and the pnp bipolar transistor 7 is immediately turned off. As a result, the potential of the output terminal 2 is rapidly lowered. At this time, the potential of the output terminal 2 is the threshold voltage Vt of the n-channel insulated gate transistor 6.
It is determined by h and the base-emitter forward voltage V _{BE of} the second npn bipolar transistor 8, and is given by V _BE + Vth. If this value becomes a negative value, the second npn bipolar transistor 8 is saturated and the high speed is impaired. Therefore, it is described that it is desirable to set this value to be somewhat positive in consideration of variations in manufacturing conditions of semiconductor devices.

As described above, the conventional circuit has a drawback that the amplitude of the potential of the output terminal cannot be made equal to the magnitude of the power supply voltage. In order to eliminate this drawback, it is sufficient to use an insulated gate field-effect transistor to flow current in or out of the output terminal. In that case, to achieve the same high speed as using a bipolar transistor, a large channel length is required. And a transistor having a width is required, which is disadvantageous in terms of integration. As shown in FIG. 2, a circuit configuration described in JP-A-48-35761 in which either bipolar transistor is replaced with an insulated gate field effect transistor is also conceivable. However, even in that case, it is obvious that the above-mentioned drawbacks are not completely eliminated.

That is, the logic amplitude becomes small on the BiP side, and the integration degree decreases on the MOS side.

Further, in FIG. 1, when the voltage of the input terminal 1 is V _CC, a current must be supplied from the input terminal 1 to the base of the npn bipolar transistor 8, so a circuit for supplying a signal to the input terminal 1 is sufficient. It had to be a circuit capable of supplying current.

As described above, the conventional circuit has a drawback that the output swing is smaller than the magnitude of the power supply voltage.

[Object of the Invention]

An object of the present invention is to solve the problems in the above conventional circuit system.
It is an object of the present invention to provide a drive circuit having a high drive capability of a bipolar transistor and capable of outputting a power supply voltage or a voltage higher than that.

A circuit in which a bipolar transistor and an insulated gate transistor are connected in parallel to the output stage of the output buffer circuit is known, for example, in Japanese Patent Laid-Open Nos. 57-212827 and 58-80929. However, these publications do not describe applying positive feedback to the output stage insulated gate transistor (flip-flop).

[Outline of Invention]

In order to achieve the above object, in the present invention, the drive of the load,
The bipolar transistor and the insulated gate field effect transistor are additive. As a result, the bipolar transistor is driven at high speed, and the output of the bipolar transistor is used to drive the insulated gate field effect transistor to compensate the forward voltage V _BE drop between the base and emitter of the bipolar transistor.

Example of Invention

First, a reference example for facilitating understanding of the present invention will be shown. FIG. 3 shows the configuration. First in FIG.
Npn bipolar transistor 28 collector and first P
The source of the channel insulated gate field effect transistor 24 is connected to the positive power source 21, and the drain of the first P channel insulated gate field effect transistor 24 and the drain of the first N channel insulated gate field effect transistor 25 are connected to the above. The first npn bipolar transistor 28 is connected to the base, and the gates of the first P-channel insulated gate field effect transistor 24 and the first N-channel insulated gate field effect transistor 25 are connected to form an input terminal. 1 N-channel insulated gate field effect transistor 25
Of the second NPN bipolar transistor 29 and the collector of the second npn bipolar transistor 29 are connected to the drain of the second Npn bipolar transistor 29.
The source of the channel insulated gate field effect transistor 26 and the source of the second P channel insulated gate field effect transistor 27 are connected to the base of the second npn bipolar transistor 29, and the source of the second P channel insulated gate type transistor is connected. The drain of the field effect transistor 27 and the second
Of the npn bipolar transistor 29 is connected to the load power source 23, and the gates of the second N-channel insulated gate field effect transistor 26 and the second P-channel insulated gate field effect transistor 27 are connected to form an input terminal. And the drain of the third P-channel insulated gate field effect transistor 30 and the drain of the third N-channel insulated gate field effect transistor 31 are connected.
The source of the third N-channel insulated gate field effect transistor 31 is connected to the negative power source 23, and the third P-channel insulated gate field effect transistor 30 and the third N-channel insulated gate field effect transistor 31 are connected. And a circuit in which the gates are connected to form an input terminal, the input terminals of the respective circuits are connected to form a common input terminal 19, the emitter of the first npn bipolar transistor 28 and the second npn bipolar Collector of transistor 29, third N and P channel insulated gate field effect transistor
The output terminal 20 is connected to the drains of 30, 31.

Next, the operation of the circuit shown in FIG. 3 will be described. Here, for convenience of explanation, the potential V _SS of the power supply terminal 23 is set to 0 V, and the terminal 22 is connected to the positive power supply 2
The description will be given assuming that it is connected to 1. When the potential of the input terminal 19 is 0V, the P-channel insulated gate field effect transistors 24 and 27 are conductive, and the N-channel insulated gate field effect transistors 25 and 26 are non-conductive. As a result, the first npn bipolar transistor 28 is connected to the power source 2 at the base.
The second npn bipolar transistor 29 becomes non-conducting because electric current accumulated in the base flows out to the power supply 23 by supplying a current from 1. Therefore, the potential of the output terminal 20 rises. On the other hand, since the third P-channel insulated gate field effect transistor 30 is conductive and the third N-channel insulated gate field effect transistor 31 is non-conductive, the third P-channel insulated gate field effect transistor 30 is turned on.
The current flowing therethrough also contributes to the increase in the potential of the output terminal 20. As a result, the potential of the output terminal 20 is the voltage V of the positive power supply 21.
Until the value obtained by subtracting the base-emitter forward voltage V _BE of the first npn bipolar transistor 28 from _CC is obtained.
The current is increased by the current supplied through the first npn bipolar transistor 28 and the current supplied through the third P-channel insulated gate field effect transistor 30, and thereafter, by the P-channel insulated gate field effect transistor 30. It rises to the potential of terminal 22, V _CC .

When the voltage at input terminal 19 is switched to the positive power supply voltage V _CC ,
The first, second and third P-channel insulated gate field effect transistors 24, 27 and 30 are non-conductive. The first, second and third N-channel insulated gate field effect transistors 25, 26 and 31 are conductive. As a result, the first npn bipolar transistor 28
No longer flows through the base current, and the charge accumulated in the base is transferred to the N-channel insulated gate field effect transistor 25.
The npn bipolar transistor 28 is quickly turned off. On the other hand, since the base current flows to the base of the second npn bipolar transistor 29 through the N-channel insulated gate field effect transistor 26,
The npn bipolar transistor becomes conductive and the potential of the output terminal 20 drops. At this time, since the third N-channel insulated gate field effect transistor 31 is also conducting, the potential of the output terminal is kept at the second npn bipolar transistor 29 until it reaches the base-emitter forward voltage V _BE . Npn bipolar transistor 29 and the second N-channel insulated gate field effect transistor 31 described above are additively lowered, and thereafter, the potential is lowered by the N-channel insulated gate field effect transistor 31 until the potential of the terminal 23 reaches 0V. . Input / output waveforms in the above operation are shown in FIG. The potential of the output terminal 20 is the potential of the terminal 22 or V
_When the potential reaches _SS and reaches a steady state, either one of the P-channel insulated gate field effect transistor 30 and the N-channel insulated gate field effect transistor 31 is in a conductive state. In this reference example, N and P
Channel Insulated Gate Field Effect Transistor 24,25,2
The same input signal was applied to the gates of 6,27,30,31. However, input signals with a time difference may be added if necessary.
However, in that case, make sure that no voltage higher than the base-emitter reverse withstand voltage BV _BE is applied between the base-emitter of the npn transistor 28 and that a negative power supply is applied from terminal 21 or 22.
It is necessary to set the time difference so that a large current does not flow to 23. The source of the P-channel insulated gate field effect transistor 27 is the npn bipolar transistor 29.
Since the base-emitter forward voltage V _BE of
The maximum voltage between the gate and source is only about 0.8V. Therefore, when high speed is required, the P-channel insulated gate field effect transistor 27 is made sufficiently conductive, so that a depletion type insulated gate field effect transistor can be used. However, making the P-channel insulated gate field effect transistor 27 a depletion type may increase the number of steps and increase the cost. In that case, if the operation speed is allowed to be slightly slowed down, the P-channel insulated gate field effect transistor 27 can be omitted and the number of elements can be reduced to achieve cost reduction and high integration. . Further, in this embodiment, npn type bipolar transistors are used as the bipolar transistors 28 and 29,
Although P-channel and N-channel transistors are used as the insulated gate field effect transistors 30 and 31, respectively, the types of these transistors can be changed without changing the gist of the invention by changing the circuit configuration as necessary. It is possible.

In the circuit of FIG. 3, a circuit in which N-channel and P-channel insulated gate field effect transistors are connected in series is used for controlling conduction / non-conduction of npn-type bipolar transistors 28 and 29 and preventing saturation. However, it is needless to say that these can be modified in various ways. Also, in FIG. 3, it is possible to raise the potential of the output terminal 20 to V _CC or more by applying a pulse signal reaching the potential of V _CC or more to the source of the insulated gate field effect transistor 30, that is, the terminal 22. is there. The timing chart shown in FIG. 5 is an example of a pulse signal for raising the potential of the output terminal 20 to V _CC or more. Not limited to the example of FIG. 4, the amplitude of the pulse signal applied to the terminal 22 and the timing of the application of the pulse signal should be set between the emitter and base of the npn bipolar transistor 28 so that the reverse breakdown voltage BV _BE between the base and the emitter of the npn bipolar transistor is not less than that. If no voltage is applied and no current flows back to the terminal 22 through the insulated gate field effect transistor 30, the potential of the output terminal 20 is set to the terminal 22 based on the above-mentioned principle of operation.
Rises to the potential of.

FIG. 6 is also a reference example for facilitating the understanding of the present invention. In the figure, the first npn bipolar transistor 41
Is connected to the positive power supply 36, the emitter of the npn bipolar transistor 41 is connected to the collector of the second npn bipolar transistor 42, and the emitter of the second npn bipolar transistor 42 is connected to the negative power supply 38. P of 1
The source of the channel insulated gate field effect transistor 39 is connected to the collector of the second npn bipolar transistor 42 and the emitter connection point of the first npn bipolar transistor 41 to serve as an output terminal, and the first P channel insulated gate is used. -Type field-effect transistor 39 drain and first N-channel insulated gate field-effect transistor
The drain of 40 is connected to the base of the second npn bipolar transistor 42, the source of the first N-channel insulated gate field effect transistor 40 is connected to the negative power supply 38, and the drain of the first npn bipolar transistor 40 is connected. A circuit in which the base is connected to the gate of the first P-channel insulated gate type field effect transistor 39 and the gate of the first N-channel insulated gate type field-effect transistor 40 to be an input terminal, and the second P-channel insulated gate The source of the second N-channel insulated gate field effect transistor is connected to the positive power supply 36 and the source of the second N-channel insulated gate field-effect transistor 44 is connected to the negative voltage V _SS . 44 drains and the second P
The drain of the channel insulated gate field effect transistor 43 is connected, and the gate of the second N channel insulated gate field effect transistor 44 and the gate of the second P channel insulated gate field effect transistor 43 are connected. As an input terminal, the drain of the third P-channel insulated gate field effect transistor 45 and the drain of the third N-channel insulated gate field effect transistor 46 are connected to be an output terminal, and the N-channel insulated gate field effect transistor is connected. The source of the transistor 46 is connected to the negative power supply 38, and the gate of the third P-channel insulation gate type field effect transistor 45 and the gate of the third N-channel insulation gate type field effect transistor 46 are connected to the second P-channel insulation. The drain of the gate field effect transistor 43 and the second N
Using a circuit connected to the drain of the channel insulated gate field effect transistor 44, the input terminals of each circuit are connected to form a common input terminal 34, and the output terminals of each circuit are connected to form a common output terminal 35. I am trying.

Next, the operation of the circuit shown in FIG. 6 will be described. Here, for convenience of explanation, it is assumed that the potential of the power supply terminal 38 is 0 V and the terminal 37 is connected to the positive power supply 36. When the voltage of the input terminal 34 is the positive power supply voltage V _CC , the first npn bipolar transistor 41 becomes conductive, and the second pn bipolar transistor 42 becomes the first P-channel insulated gate field effect transistor.
39 is non-conductive, and the first N-channel insulated gate field effect transistor 40 is conductive so that it is non-conductive. on the other hand,
Second P-channel insulated gate field effect transistor
43 is non-conductive, and the second N-channel insulated gate field effect transistor 44 is conductive, so that the potential of the terminal 47 drops, the third P-channel insulated gate field effect transistor 45 is conductive, and the third N-channel insulated gate field-effect transistor 45 is conductive. The channel insulated gate field effect transistor 46 becomes non-conductive. As a result, the first np
A current flows through the n-bipolar transistor 41 and the third P-channel insulated gate field effect transistor 45, and the potential of the output terminal 35 rises to the potential of the terminal 37. Since the terminal 37 is assumed to be connected to the positive power source 36 here, the potential of the output terminal 35 reaches V _CC . At this time, until the potential of the output terminal 35 becomes the value obtained by subtracting the base-emitter forward voltage V _BE of the first npn bipolar transistor 41 from the potential V _CC of the positive power supply 36, the first npn bipolar transistor 4
1 and the third P-channel insulated gate field effect transistor 45 contribute to the increase in the potential of the output terminal 35, and thereafter, the third P-channel insulated gate field effect transistor 45.
45 raises the potential of the output terminal 35.

When the voltage of the input terminal 34 is reduced from V _CC to 0V, the first npn
The bipolar transistor 41 becomes non-conductive. Also, the first P-channel insulated gate field effect transistor 39 becomes conductive, the first N-channel insulated gate field effect transistor 40 becomes non-conductive, and a current flows through the base of the second npn bipolar transistor 42. Npn bipolar transistor 42 becomes conductive. On the other hand, the second P-channel insulated gate field effect transistor 43 becomes conductive, and the second N-channel
The channel insulated gate field effect transistor 44 becomes non-conductive, and the potential of the terminal 47 rises. Therefore, the third P-channel insulated gate field effect transistor 45 becomes non-conductive, and the third N-channel insulated gate field effect transistor 46 becomes conductive. As a result, the potential of the output terminal 35 is 0 V due to the second npn bipolar transistor 42 and the third N-channel insulated gate field effect transistor 46.
Be lowered to. At this time, until the potential of the output terminal 35 reaches the base-emitter forward voltage V _BE of the second npn bipolar transistor, the second npn bipolar transistor 42 and the third channel insulated gate field effect transistor 46 are connected. And contribute to the decrease of the potential of the output terminal 35, and thereafter, the potential of the output terminal 35 is decreased by the third N-channel insulated gate field effect transistor 46.
In this embodiment, it is possible to apply a pulse signal having a potential higher than V _{CC to} the terminal 37 to raise the potential of the output terminal 35 higher than V _CC , as in the circuit shown in FIG. .
In addition, if necessary, it is possible to provide a time difference between the input signals applied to the base of the npn bipolar transistor 41 and the insulated gate field effect transistors 39, 40, 43, 44. The fact that the transistor type can be changed without changing the gist of is similar to the reference example shown in the circuit of FIG. In this reference example, the input signal is directly applied to the base of the bipolar transistor 41. Therefore, when the output terminal 35 is at the high level and the input terminal transits to the low level, a voltage higher than the base-emitter reverse withstand voltage BV _BE may be applied between the base-emitter of the bipolar transistor 41. . In that case, it is necessary to adjust the constants of the insulated gate field effect transistors 39 and 41 so that a voltage of BV _BE or more is not applied between the base and the emitter of the bipolar transistor 41.

As described above, in the reference example shown in FIG. 6, the circuit 49 has the function of allowing the output swing to be equal to or higher than the power supply voltage and suppressing the fluctuation of the output potential when the output terminal is in the steady state. On the street. The circuit 49 in FIG.
Since the same input signal as 48 is applied, layout may be difficult due to the configuration of circuit 49, etc.
The input 34 of the circuit 48 and the input 34 of the circuit 49 must be driven by the output of the preceding circuit, and a large output drive capability of the preceding circuit is required. In that case, the circuit 59 of FIG. 7 can be used instead of the circuit 49 of FIG. The circuit shown in FIG. 7 shows a main part of the present invention. The circuit of FIG. 7 has the same configuration as the terminal 34 is connected to the output terminal 35 in the circuit 49 of FIG. 6 by a flip-flop in which the gate and drain of a pair of insulated gate field effect transistors are cross-connected. The operation of FIG. 7 will be described. When the potential of the terminal 50 rises by the circuit including the bipolar transistors 41 and 42 in the preceding stage, the first P-channel insulated gate field effect transistor 54 becomes non-conductive, and the first N-channel insulated gate field effect transistor 55. Becomes conductive. As a result, the potential of the terminal 58 decreases, the second P-channel insulated gate field effect transistor 56 becomes conductive, the second N-channel insulated gate field effect transistor 57 becomes non-conductive, and the potential of the output terminal 50 becomes the potential of the terminal 52. Rise to. When the electric potential of the output terminal 50 becomes high level, the electric potential of the terminal 58 is kept at V _SS and the electric potential of the output terminal 50 is kept stable and is less susceptible to fluctuations. When the input signal of the circuit including the preceding-stage bipolar circuit is switched and the potential of the output terminal 50 is lowered by the preceding-stage circuit, the first P-channel insulated gate type field effect transistor 54 becomes conductive, and the first N-channel insulated gate type. The field effect transistor 55 becomes non-conductive. As a result, the potential of the terminal 58 rises, the second P-channel insulated gate field effect transistor 56 becomes non-conductive, the second N-channel insulated gate field effect transistor 57 becomes conductive, and the output terminal 50
Potential drops to the potential V _{SS of} terminal 52. When the potential of the output terminal 50 becomes low level, the potential of the terminal 58 is kept at V _CC , so that the potential of the output terminal 50 is kept stable and is not susceptible to fluctuation as in the high level. In this way, since this circuit is a flip-flop circuit, it can be held stable once it reaches a steady state, but since it uses bipolar transistors 41 and 42 with high driving capability in the previous stage, it does not switch the input. Sometimes it can be flipped easily. That is, the first P-channel insulated gate type transistor 54 and the first N-channel insulated gate type transistor 55 forming the inverter.
Is driven by the outputs of the bipolar transistors 41 and 42,
As compared with the case of driving with the input signal 34 as shown in FIG. 6, extremely high driving capability is not required for the preceding circuit that drives the input signal 34. As is clear from the above operation, the present circuit 59 can be used not only in the reference example of FIG. 6 but also in addition to various drive circuits including bipolar transistors. Also in this circuit, the positive power supply voltage V _CC
As in the case of the reference example, the potential of the output terminal 50 can be raised to V _CC or higher by applying the pulse signal reaching the above level.

FIG. 8 shows an embodiment in which the circuit of FIG. 7 is applied to a multi-input logic circuit. In FIG. 8, the collector of the npn bipolar transistor 66 and the source of the P channel insulated gate field effect transistor 64 are connected to the positive power source 63, and the drain of the P channel insulated gate field effect transistor 64 and one end of the resistor 65 are connected. The npn bipolar transistor 6
6 is connected to the base, and the gate of the P-channel insulated gate field effect transistor 64 is used as an input terminal.
By connecting N emitters of the n bipolar transistor 66 and the other end of the resistor 65 and using them as output terminals, the collector of the npn bipolar transistor 71 and the source of the P channel insulated gate field effect transistor 69 are connected. The drain of the P-channel insulated gate field effect transistor 69 and the drain of the N-channel insulated gate field effect transistor 70 are connected to the base of the npn bipolar transistor 71 as an output terminal, and the P-channel insulated gate field effect transistor is connected. The gate of 69 and the gate of the N-channel insulation gate type field effect transistor 70 are connected to form an input terminal, and the source of the N-channel insulation gate type field effect transistor 70 and the emitter of the npn bipolar transistor 71 are connected to the negative power source 72. And the circuit 59 shown in FIG. And a common output terminal 62 by connecting the output terminal of the circuit. In this embodiment, the circuit 60 outputs a current to the output terminal 62 and outputs it.
The circuit 61 is a circuit for causing a current to flow from the output terminal 62 and decreasing the potential of the output terminal 62. Further, the circuit 59 keeps the output terminal 62 in a low impedance state to prevent potential fluctuations when the potential of the output terminal 62 rises or falls to reach a steady value, and when necessary, sets the output swing to the power supply voltage or more. It is a circuit for expanding.

The operation of this embodiment will be described. First, a high level signal is applied from the input terminal A ₁ to A _N to make the P-channel insulated gate field effect transistor 64 non-conductive and cut off the base current of the npn bipolar transistor 66 to make it non-conductive. After that, a low level signal is applied to the terminal 68 to make the npn bipolar transistor 71 conductive and raise the potential of the output terminal 62.
The potential of the output terminal 62 drops to the negative power supply voltage V _SS due to the action of the circuit 59. After the potential of the output terminal 62 becomes steady, the terminal 68 is transited to the high level and the npn bipolar transistor 71 is made non-conductive. As long as the input signals A ₁ to A _N are at the high level, the potential of the output terminal 62 is kept at the potential V _SS of the power source 72 by the circuit 59. In this state, when at least one of the input signals A ₁ to A _N becomes low level, the potential of the output terminal 62 rises due to the circuit 60 to which the input signal is applied. At this time, the collector current of the npn bipolar transistor and the current flowing through the resistor 65 flow into the output terminal 62. At the same time, the circuit 59 also contributes to the increase in the potential of the output terminal 62, and the potential of the output terminal 62 reaches V _CC . After reaching V _CC , the potential of the output terminal 62 is stably held by the circuit 59. Further, similarly to the reference example, the potential of the output terminal 62 can be raised to V _CC or higher by the circuit 59.
The example of the logic circuit according to the present invention has been described above. In addition to this, it is needless to say that various logic circuits can be implemented by using bipolar transistors in parallel to flow out current from the output terminal in the same manner. Also here, npn
Although a bipolar transistor was used, it is clear that a similar circuit can be constructed using a pnp bipolar. In the circuit 60 of FIG. 8, the resistor 65 is connected between the base of the npn bipolar transistor 66 and the emitter.
By using the resistor 65, even if the potential of the output terminal 62 shifts to a high level when the P-channel insulated gate field effect transistor 64 is in a non-conducting state, a reverse voltage is generated between the base and the emitter of the bipolar transistor 66. It is possible to prevent the directional voltage from being applied. In some cases, it may be difficult to use a resistor for layout. In that case, an N-channel insulated gate field effect transistor is used, and the drain of the N-channel insulated gate field effect transistor is connected to the base of the npn bipolar transistor. However, the source can be connected to the emitter of the npn bipolar transistor and the gate can be connected to the gate of the P-channel insulated gate field effect transistor 64, and the resistor 65 can be omitted. In the case of FIG. 8, when it is attempted to compensate the output voltage with an input signal as shown in FIG. 6, a circuit for logically operating a multi-input signal to make one output is made, and the output is made into a transistor of an inverter. You will have to fill in 43 and 44. However, in FIG. 8, since the output voltage compensating circuit of FIG. 7 is used, it can be solved by using only one in the final stage.

FIG. 9 shows a fourth embodiment of the present invention. In FIG. 9, a circuit 101 is a circuit for flowing a current through the npn bipolar transistor 88. In the circuit 101, the gates of the P-channel insulated gate field effect transistor 86 and the N-channel insulated gate field effect transistor 87 are connected to serve as input terminals, and the drains thereof are connected to the base of the npn bipolar transistor 88. The collector of the transistor 88 and the source of the P-channel insulated gate type field effect transistor 86 are connected as a power supply terminal, and the emitter of the npn bipolar transistor 88 and the source of the N-channel insulated gate type transistor are connected as an output terminal. . The circuit 102 is a two-input circuit composed of insulated gate field effect transistors 95 to 98.
It is an AND circuit. By using the two circuits, the output of the first circuit 102 is connected to the base of the npn bipolar transistor 99, and the output of the second circuit 102 is connected to the gate of the N-channel insulated gate field effect transistor 100. The circuit 103 is a circuit for controlling the gate voltage of the P-channel insulated gate field effect transistor 93 by a signal applied to the terminals 81 and 82. In the circuit 103, the drain of the first N-channel insulated gate field effect transistor 89 and the source of the first P-channel insulated gate field effect transistor 92 are connected to form a positive power supply terminal, and the N and P channels are connected. The source and the drain of the insulated gate field effect transistor 89 are connected to the source of the second P-channel insulated gate field effect transistor 90 for output, and the drain of the P-channel insulated gate field effect transistor 90 and the 2 N Channel Insulated Gate Field Effect Transistor 91
Of the second N-channel insulated gate field effect transistor is connected to the negative power source 85. In FIG. 9, two circuits 101 and 102, a circuit 103, P-channel insulated gate field effect transistors 93 and 94, N-channel insulated gate field effect transistor 100 and npn bipolar transistor 99 are used.
The collector of the bipolar transistor 88 of the first circuit 101, the source of the P-channel insulated gate field effect transistor 86 and the source of the P-channel insulated gate field effect transistor 93 are connected to the first positive power source 83, and the positive voltage of the circuit 103 is increased. The power supply terminal, the source of the P-channel insulated gate type field effect transistor 86 of the second circuit 101, the collector of the npn bipolar transistor 88, the drain of the N-channel insulated gate type transistor 95 of the second circuit 102 and the P-channel insulated gate. The source of the N-type field effect transistor 94 is connected to the second positive power supply 84, and the source of the N-channel insulated gate type field effect transistor 91 of the circuit 103 and the first and second
Of the P-channel insulated gate field effect transistors 97 and 98 of the circuit 102 of FIG.
Connected to the emitter of 99 and the source of the N channel insulated gate field effect transistor 100 and the negative power supply 85, the first circuit 1
The input terminal 01, the gates of the N and P channel insulated gate field effect transistors 89 and 90 of the circuit 103, and the first and second
The gates of the N and P channel insulated gate field effect transistors 95 and 97 of the circuit 102 of FIG.
1, the gates of the P and N channel insulated gate field effect transistors 92 and 91 of the circuit 103, the input terminals of the second circuit 101, and the N and P channel insulated gate field effect fields of the first and second circuits 102. The gates of the effect transistors 96 and 98 are connected to form the second input terminal 82, and the output terminals of the first and second circuits 101 and the P-channel insulated gate field effect transistor.
The drains of 93, 94, the drain of the N-channel insulated gate type field effect transistor 95 of the first circuit 102, the collector of the npn bipolar transistor 99 and the drain of the N-channel insulated gate type transistor 100 are connected to form an output terminal. The potential V _CC 1 of the first positive power source 83 is set lower than the potential V _CC 2 of the second positive power source 84.

In the above configuration, when a high level signal is applied to the first and second input terminals 81 and 82, the potential of the output terminal 80 becomes the potential V _SS of the negative power source 85, and then the first input terminal 81 is applied. The potential of the output terminal 80 rises to the first positive power supply voltage V _CC 1 at a high speed when the signal being output is changed to the low level. Then second
When the signal applied to the input terminal 82 of is shifted to the low level, the potential of the output terminal 80 rapidly rises to the second positive power supply voltage V _CC 2. Further, at these three output levels, the output terminal 80 is placed in a low impedance state by each of the insulated gate field effect transistors 100, 93, 94, and is less susceptible to potential fluctuations. The above operation will be described below. First,
When a high level input signal is applied to the second input terminals 81 and 82, the P channel insulated gate field effect transistor 86 in the circuit 101 becomes non-conductive and the N channel insulated gate field effect transistor 87 becomes conductive. As a result, the base current of the npn bipolar transistor 88 stops flowing and the np
n Bipolar transistor 88 becomes non-conductive. Also, circuit 1
In 03, the P-channel insulated gate field effect transistors 90 and 92 are non-conductive, and the N-channel insulated gate field effect transistors 89 and 91 are conductive. Therefore, the gate voltage of the P-channel insulating gate type field effect transistor 93 becomes the high level V _CC 2, and the P-channel insulating gate type field effect transistor 93 becomes non-conductive. Further, the P channel insulated gate field effect transistor 94 is also non-conductive. On the other hand, in the circuit 102, the N-channel insulated gate field effect transistors 95 and 96 are conductive and the P-channel insulated gate field effect transistors 97 and 98 are non-conductive. Therefore, the npn bipolar transistor 99 and the N-channel insulated gate field effect transistor 100 are both conductive, and the potential of the output terminal 80 drops to V _SS . At this time, the N-channel insulated gate field effect transistor 100 is used.
Are connected to each other, the output terminal 80 is kept in a low impedance state. Next, when the potential of the first input terminal 81 transits to the low level, the npn bipolar transistor of the first circuit 101.
88 is conducting. In addition, since the insulated gate field effect transistors 81 and 92 in the circuit 103 are non-conductive and 90 and 91 are conductive, P
The channel insulated gate field effect transistor 93 becomes conductive. On the other hand, the bipolar transistor 8 of the second circuit 101
8 and P channel insulated gate field effect transistor 94
Remains non-conducting. Further, the AND circuit 102 renders the npn bipolar transistor 99 and the N-channel insulated gate field effect transistor 100 non-conductive. As a result, the potential of output terminal 80 rises to V _CC 1. At this time, since the P-channel insulated gate field effect transistor 93 is conducting, the output terminal 80 low is kept in the impedance state. When the potential of the second input terminal 82 is subsequently changed to the low level, the insulated gate field effect transistors 89 and 91 of the circuit 103 are made non-conductive and 92, 90 are made conductive. Yotsutte P
The gate potential of the channel insulated gate field effect transistor 93 becomes a high level V _CC 2 and the P channel insulated gate field effect transistor 93 becomes non-conductive. On the other hand, in addition to the npn bipolar transistor 88 of the first circuit 101, the npn bipolar transistor 88 and the P-channel insulated gate field effect transistor 94 of the second circuit 101 become conductive. On the other hand, both the npn bipolar transistor 99 and the N-channel insulated gate field effect transistor 100 remain non-conductive. As a result, the potential of the output terminal 80 rises to the second positive power supply voltage V _CC 2. At this time, since the P-channel insulated gate field effect transistor 94 is conducting, the output terminal 80 is kept in a low impedance state.

As described above, according to the embodiment shown in FIG. 9, there are three stages of output levels, V _SS , V _CC 1, and V _CC 2, and it is difficult for potential fluctuations to occur at each output level, resulting in high driving capability. It is possible to realize a drive circuit having Although this embodiment shows a circuit having two inputs and three output levels, V _SS , V _CC 1, and V _CC 2, the number of inputs, the logical relationship between input and output, and the number of output levels are limited to this. It can be set without a problem. Also, it goes without saying that a similar circuit can be constructed by using pnp type bipolar transistors. In FIG. 9, the sources of the insulated gate field effect transistors 93 and 94 are connected to the power source. It can be set to a value.

As is clear from the above-described embodiments, according to the present invention, the bipolar transistor and the insulated gate field effect transistor drive the load in an additive manner so that the bipolar transistor has a high driving capability. It is possible to realize a drive circuit in which the output swing is the power supply voltage or higher and the potential variation of the output portion is hard to occur. Further, since the output of the bipolar transistor is used to drive the insulated gate field effect transistor, an extremely high driving capability is not required for the preceding circuit that drives the input signal. The drive circuit having such characteristics can be used for various purposes, and is particularly suitable as a word line drive circuit for a semiconductor memory device. Here, a case will be described in which the circuit of FIG. 3 which is a reference example of the present invention is applied to the word line drive circuit of the dynamic type and static type semiconductor memory devices.

FIG. 10 shows an example of the structure in which the circuit 32 of FIG. 3 is used in the word line drive circuit of the dynamic semiconductor memory device in which the memory cell is composed of the insulated gate field effect transistor.
FIG. 12 shows a configuration example of the flip-flop type static semiconductor memory device in which the circuit 32 is used in the word line drive circuit. In FIG. 10 and FIG. 12, terminal 110 is an address input terminal, ADR is an address signal, 111 is an address buffer, 112 is a decoder, 113 and 114 are decoder output lines 115,
116 is a decoder input line, 126 is a bit line precharge circuit, 32 is a word line drive circuit, WL1 and WL2 are word lines, BL, ▲
A black dot represents a bit line, and a chip 117 represents a semiconductor memory device. Further, in FIG. 10, CS is a chip selection signal, φ _R is a word line reset signal, φ _P is a precharge signal SA is a sense amplifier, and C _S is a memory cell capacity. The read operation of the dynamic semiconductor memory device shown in FIG. 10 will be described below with reference to the timing chart of FIG. Before the read operation is started, the chip selection signal CS is at high level. Therefore, the word line reset signal φ _R and the precharge signal φ _P generated by using CS are at low level and high level, respectively. In this state, the output of the decoder 112 is kept at a high level by the word line reset signal φ _R , and as a result, all the word lines are kept at a low level.
Further, the N channel insulated gate field effect transistors 122, 123, 124 are turned on by the precharge signal φ _P, and the potentials of the bit lines BL, ▲ ▼ are both set to the reference potential which is about half the power source voltage V _CC . At the same time as the chip select signal CS transits to the low level and the read operation is started, the address signal ADR is applied. Then, in response to the chip selection signal CS, the precharge signal φ _P changes to the low level, and then the word line reset signal φ _R changes to the high level. As a result, the decoder 112 operates according to the address buffer output, and the potential of only the selected word line rises. Tentatively
It is assumed that word line WL1 in FIG. 12 is selected. At this time, WL2
The potentials of the non-selected word lines are held at a low level. When the potential of the word line WL1 rises, the N-channel insulated gate field effect transistor 120 becomes conductive. As a result, the potential of the bit line BL slightly rises or falls below the reference potential depending on whether or not charges are stored in the memory cell capacitance C _S. On the other hand, since the potential of the bit line {circle over ()} remains at the reference potential, a slight difference occurs in the potential of the bit line BL, {circle over ()}. This difference is amplified by the sense amplifier SA. The potential difference between the bit line pair BL, {circle around (1)} is amplified to a necessary and sufficient level, transmitted to a subsequent output circuit (not shown), and read out of the chip 117. The potential of the bit line BL increased in the above process is passed through the N-channel insulated gate field effect transistor 120 and the memory cell capacitance C
Written to _S again. After that, the chip select signal transits to the high level and the word line reset signal φ _R becomes the low level. As a result, the potentials of all word lines become low level, and all N-channel insulated gate field effect transistors connected to the memory cell capacitors become non-conductive. After that, when the precharge signal φ _P changes to the high level, the bit line BL, ▲
The potential of ▼ transits to the reference potential and becomes the state before the read operation again.

As described above, in the read operation, the potentials of all the word lines before and after the operation or the unselected word lines during the operation must be kept at a low level, and if the potential of these word lines fluctuates for some reason, the memory The N-channel insulated gate field effect transistor connected to the cell capacitor becomes conductive and malfunctions or destroys information in the memory cell. This potential variation of the word line is likely to occur especially when the potential difference between the bit line pair is increased by the sense amplifier SA. That is, since the potential of the bit line fluctuates at high speed and with a large amplitude by the sense amplifier SA, a relatively high voltage is coupled to the word line via the capacitance between the bit line and the word line due to the voltage fluctuation. Is. Although only a pair of bit lines are shown in FIG. 10, the above-mentioned widening is carried out simultaneously for all bit lines in the chip, so that the coupling voltage cannot be ignored.

This phenomenon becomes a problem especially in terms of noise when realizing a highly integrated and constrained dynamic semiconductor memory device. Regarding the above circumstances, ITOH, K. And SUNAMI, H.: 'H
igh−density one−device dynamic MOS memory cell
s ′, IEE PROC., vol.130, pt.I.No.3, JUNE1983, pp127−13
There are details in 5. If the selected word line cannot be driven at high speed and with high amplitude, the signal level of the information read out to the bit line becomes small, which may cause an unstable operation or the information rewritten in the memory cell. As the signal level decreases, soft error due to α rays becomes a problem. As described above, in order to realize a high-speed dynamic type semiconductor memory device, it is necessary to drive the word line at a high speed with a high amplitude and keep the word line potential stable. Next thirteenth
The operation of the static semiconductor memory device shown in FIG. 12 will be described with reference to the timing chart of FIG. In the static semiconductor memory device, all the word line potentials are not set to the low level in advance and the bit line potential is set to the reference level as in the dynamic semiconductor memory device. One method is to switch the potentials of a selected word line and a non-selected word line simultaneously according to an input signal. This is because, in the static semiconductor memory device, since the memory cell itself has an information holding capacity and a sufficient current supply capacity, stable operation can be realized even with the above method. As described above, in the static semiconductor memory device, it is not necessary to set all word line potentials to low levels in advance. However, the word line is still susceptible to potential fluctuations, though not as much as the dynamic type semiconductor memory device, and it is necessary to drive the word line at high speed and with high amplitude in order to achieve high speed operation of the semiconductor memory device.

As described above, the word line drive circuit of the semiconductor memory device has a high drive capability, is less susceptible to potential fluctuations, and has a large output swing. It is possible to realize various semiconductor memory devices.
Although the above description has been made only for the read operation, the same applies to the write operation. Further, although the drive circuit shown in FIG. 3 is used in FIGS. 10 and 11, it is also possible to use variously modified circuits such as the circuit shown in FIG. 6 within the scope of the present invention, if necessary. .

Although some embodiments have been described above, the present invention is not limited to the above embodiments, and it is needless to say that various modifications can be made without departing from the scope of the invention.

〔The invention's effect〕

As described above, according to the present invention, the same load is additively driven by the bipolar transistor and the insulated gate field effect transistor. Therefore, transiently, the large driving capability of the bipolar transistor is sufficiently exerted, The insulated gate field effect transistor can compensate the forward voltage V _BE drop between the base and emitter of the bipolar transistor. Further, since the insulated gate field effect transistor is driven by using the output of the bipolar transistor, it is possible to obtain a drive circuit which does not require extremely high drive capability in the preceding circuit which drives the input signal.

[Brief description of drawings]

1 and 2 are diagrams showing the configuration of a conventional circuit, FIG. 3 is a reference diagram for facilitating understanding of the present invention, and FIGS. 4 and 5 are diagrams for explaining the operation of the circuit of FIG. FIG. 6 is a reference diagram for facilitating understanding of the present invention, FIG. 7, FIG.
FIG. 9 is a diagram showing a configuration of an embodiment of the present invention, FIG. 10, FIG.
FIG. 11 is a diagram showing a configuration example when the present invention is applied to a semiconductor memory device, and FIGS. 11 and 13 are diagrams for explaining the operation of FIG. 10 and FIG. 1,10,19,34, A ₁ ~ A _N , 81,82 …… Input, 2,11,20,35,50,62,
80 …… Output, 4,13,24,27,19,39,43,45,54,56,64,69,86,
90,92,94,97,98 …… P channel insulated gate field effect transistor, 5,6,14,16,25,26,31,40,44,46,55,57,7
0,87,89,91,95,96,100,121,122,123,124 …… N channel insulated gate field effect transistor, 7,8,15,28,29,4
1,42,66,71,88,99 …… Bipolar transistor.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Noriyuki Homma Inventor Noriyuki Honma 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Central Research Laboratory, Hitachi, Ltd. (72) Kunihiko Yamaguchi 1-280 Higashi Koigakubo, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory (72) Inventor Kiyoo Ito 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Central Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-58-21919 (JP, A)

Claims (9)

[Claims] 1. A first circuit including a first bipolar transistor driven in a non-saturated region in a semiconductor device and connected to a reference potential, and a second circuit including a first insulated gate field effect transistor. And a base of the first bipolar transistor is the first bipolar transistor.
In response to the input signal of the first circuit, a current path is formed between the collector and the emitter of the first bipolar transistor between the first potential and the output of the first circuit, and the first insulated gate The source of the type field effect transistor is connected to the second potential, the first potential and the second potential have the same polarity with respect to the reference potential, and the absolute value of the second potential is the first potential. The signal inverting means having the above size, the drain of the first insulated gate field effect transistor is connected to the output of the first circuit, and the input is connected to the output of the first circuit. Further comprising: a gate of the first insulated gate field effect transistor connected to the output of the signal inverting means, and the first bipolar transistor in response to the input signal of the first circuit. Semiconductor driver circuit, characterized in that allowed to conduct the first insulated gate field effect transistor when conducting. 2. The semiconductor drive circuit according to claim 1, wherein the first circuit includes a second bipolar transistor, and the second circuit includes a second insulated gate field effect transistor. A base of the second bipolar transistor is responsive to the input signal, and a collector-emitter of the second bipolar transistor forms a current path between the reference potential and the output of the first circuit. The source of the second insulated gate field effect transistor is connected to the reference potential, the drain of the second insulated gate field effect transistor is connected to the output of the first circuit, and the signal inverting means is provided. A gate of the second insulated gate field effect transistor is connected to the output of the first insulated gate field effect transistor, and the first insulated gate field effect transistor is responsive to the input signal of the first circuit. The first insulated gate field effect transistor is turned on, the second bipolar transistor is turned off, and the second insulated gate field effect transistor is turned off when the bipolar transistor is turned on. And semiconductor drive circuit. 3. The semiconductor drive circuit according to claim 2, wherein the first circuit has a gate based on the second bipolar transistor in response to an input signal of the first circuit. A third insulated gate field effect transistor for supplying a current is further included, wherein the third insulated gate field effect transistor is turned off when the first bipolar transistor is turned on. Semiconductor drive circuit. 4. The semiconductor drive circuit according to claim 1, wherein the first circuit includes a plurality of bipolar transistors, and a collector-emitter between each of the plurality of bipolar transistors is provided. Forming a current path between the first potential and the output of the first circuit, the input signal consisting of a plurality of signals, and a signal corresponding to each signal of the bases of the plurality of bipolar transistors. A semiconductor drive circuit characterized by being applied to each. 5. The semiconductor drive circuit according to claim 4, wherein a logical operation output of the plurality of signals is output to the output of the first circuit. 6. The semiconductor drive circuit according to claim 5, wherein the logical operation output selects a word line that selects a memory cell of a semiconductor memory. 7. The semiconductor drive circuit according to claim 1, wherein the second potential is larger in absolute value than the first potential. Drive circuit. 8. The semiconductor drive circuit according to claim 7, wherein the first bipolar transistor is of npn type, and its emitter is connected to the output of the first circuit. The insulated gate field effect transistor of No. 1 is a p-channel type semiconductor drive circuit. 9. The semiconductor drive circuit according to claim 1, wherein the signal inverting means includes one p-channel type insulated gate field effect transistor and one n-channel type insulation. A semiconductor drive circuit comprising an inverter composed of a gate type field effect transistor.