JPH0697672B2 - Semiconductor device manufacturing yield prediction method - Google Patents

Description

The present invention relates to a semiconductor device manufacturing yield prediction method,
In particular, the present invention relates to a method of calculating the probability of occurrence of a defective semiconductor device due to a crystal defect and predicting the manufacturing yield of the semiconductor device based on the calculation result.

<Prior Art> Generally, in a manufacturing process of a semiconductor device, a predetermined semiconductor device is realized on a semiconductor substrate by repeating epitaxial growth, diffusion and the like. However, if the semiconductor substrate has a crystal defect, the crystal defect of the semiconductor substrate continues in the epitaxial layer grown on the substrate, and the crystal defect also occurs in the epitaxial layer. Crystal defects occur not only during epitaxial growth but also during heat treatment during impurity diffusion. When a semiconductor element is formed in a semiconductor layer having such crystal defects,
When the leakage current caused by the crystal defects is generated and is extremely large, the entire semiconductor device is defective.

Therefore, in the manufacturing process of semiconductor devices, so-called dilt etching is performed with an etching solution containing hydrofluoric acid and chromic acid after epitaxial growth and after the completion of the diffusion process, and the traces generated in the crystal defect portions are observed with a microscope to determine the amount of crystal defects generated. And the amount of defective products was predicted.

<Problems to be Solved by the Invention> However, in order to generate traces of crystal defects by the Gilt etching, the semiconductor wafer in the process of manufacturing must be destroyed by etching, and if inspection is performed for each lot, it will be used for inspection. A large number of wafers are destroyed, which raises a problem that the manufacturing cost of a semiconductor device as a product increases.

Further, in the above-mentioned conventional method, since the generation of defective products was predicted by visually observing the traces of crystal defects, it was not possible to quantitatively predict the generation of defective products, but the data could not be predicted quantitatively. There was also a problem that the process control based on it could not be performed.

Therefore, it is an object of the present invention to provide a yield prediction method capable of quantitatively predicting the generation amount of defective products based on nondestructive inspection.

<Means and Actions for Solving Problems> According to the present invention, the first region, the second region, and the third region forming the semiconductor element are each multiplied by a predetermined number in the monitor pattern region of the semiconductor wafer on which the semiconductor device is formed. First obtained
A monitor element including a fourth region of conductivity type, a fifth region of second conductivity type, and a sixth region of first conductivity type is formed, and a monitor region is formed between the fourth region and the sixth region. A reverse voltage below the breakdown voltage of the junction surface is applied. Since a reverse-biased pn junction is formed between the fourth region, the fifth region, and the sixth region, the leakage current is not measured in the region having no crystal defect.
However, if a crystal defect occurs in any of the fourth, fifth, and sixth regions, the diffusion rate of impurities increases along the crystal defect, so that the sixth region is formed in the fifth region. Then, the impurities of the first conductivity type connect the fourth region and the sixth region, and a current path is formed between the fourth region and the sixth region. Therefore, by measuring the leakage current flowing through the current path, the amount of crystal defects generated per unit area can be calculated from the leakage current, and the leakage current value generated in the semiconductor element can be predicted based on the calculation result. The yield of semiconductor devices is predicted based on the predicted value.

<Embodiment> FIG. 1 is a cross-sectional view of a monitor element according to an embodiment of the present invention. Such a monitor element is formed in each of monitor pattern regions 2 of a semiconductor wafer 1. In the area other than the monitor pattern area 2 of the semiconductor wafer 1, a large number of integrated circuits composed of bipolar transistors are formed.
The monitor element shown in FIG. 1 has a semiconductor substrate 11 of the first conductivity type and a buried layer 12 of the second conductivity type formed on the semiconductor substrate 11.
After growing the second conductivity type epitaxial layer 13 thereon,
A first conductivity type base region 14 is diffused and formed in the epitaxial layer 13, and then an emitter region 15 is diffused and formed in the base region 14. The buried layer 12, the epitaxial layer 13, the base region 14, and the emitter region 15 are formed at the same time as the corresponding layers or regions of the bipolar transistor forming the integrated circuit. Moreover, the buried layer 12 and the base region
14, the emitter region 15 has an occupied area that is a predetermined number of times larger than the occupied area of the buried layer, the base region, and the emitter region of a typical bipolar transistor that constitutes the integrated circuit.

After the monitor element having such a structure is formed in the same step as the bipolar transistor forming the integrated circuit, a positive voltage is applied to the buried layer 12 from the epitaxial layer 13 and a negative voltage is applied to the emitter region 15. Here, if the first conductivity type is n-type and the second conductivity type is p-type, a reverse bias occurs between the base and the emitter, and if there is no crystal defect, the buried layer 12 and the emitter region 15 are formed.
No current path is formed between and. However, if the crystal defect 16 is generated in the epitaxial layer 13, the diffusion rate becomes abnormally high along the crystal defect 16 during the diffusion of the emitter region 15, so that the emitter region 15 penetrates the base region 14 and the buried layer 12 is formed. Reach the vicinity of. As a result, a current path is formed along the crystal defect 16, and the buried layer 12 and the emitter region 15 are formed.
Leakage current flows between and. Therefore, the leakage current is measured by the ammeter 17, and the measured value is divided by the area occupied by the monitor element to calculate the leakage current value per unit area. Since the leakage current value per unit area is proportional to the amount of crystal defects generated per unit area, the leakage current amount generated in the bipolar transistor forming the integrated circuit based on the leakage current value per unit area can be extended. Can predict the generation amount of crystal defects, and can predict the generation amount of defective products by comparing with the specifications required for the integrated circuit.

In the above-described embodiment, the case where the integrated circuit is constituted by the bipolar transistor has been described as an example. However, like the complementary field effect transistor, the second conductivity type well is formed in the first conductivity type semiconductor substrate. It can be applied even when the first conductivity type source / drain regions are formed in the well.

Further, even when crystal defects occur during thermal diffusion or ion implantation, the profile of the impurity region collapses and a current path is generated. Therefore, it is possible to predict the generation amount of crystal defects by measuring the leakage current value as in the above embodiment.

<Effect> As described above, according to the present invention, the leakage current of the monitor element can be measured before the assembly process of the semiconductor device, and the generation amount of crystal defects can be predicted based on the measurement result. The generation amount of defective products can be predicted nondestructively, the manufacturing cost of the semiconductor device is not increased, and accurate process control can be performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a monitor element used in a prediction method according to an embodiment of the present invention, and FIG. 2 is a plan view showing a semiconductor wafer on which the monitor element is formed. 1 ... semiconductor wafer, 2 ... monitor pattern area, 13 ... fourth area, 14 ... fifth area, 15 ... sixth area.

Claims (1)

[Claims] 1. A first region of a first conductivity type, a second region of a second conductivity type formed in the first region, and a third region of a first conductivity type formed in the second region. In a method for predicting a manufacturing yield of a semiconductor device including a semiconductor element having a semiconductor device, the occupied area of the first region, the occupied area of the second region, and the third area in a monitor pattern region of a semiconductor wafer on which the semiconductor device is formed are provided.
Forming a monitor element including a fourth region of the first conductivity type, a fifth region of the second conductivity type, and a sixth region of the first conductivity type, each of which is obtained by multiplying an area occupied by the region by a predetermined value; Measuring a leakage current between the fourth region and the sixth region by applying a reverse voltage between the fourth region and the sixth region, the reverse voltage being equal to or lower than the breakdown voltage of the junction surface with the fifth region; A step of calculating a crystal defect per unit area from the leakage current, a step of predicting a leakage current value generated in the semiconductor element based on the calculation result, and a step of predicting the yield of the semiconductor device based on the predicted value. A semiconductor device manufacturing yield prediction method including.