JPH0695644B2 - Decoding device for run-length limited code - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding device for a run length limited (Run Lengfh Limited) code used for transmitting and recording digital signals.

Conventional technology When recording high-density digital data on a magnetic tape or disk, usually run length limited code (hereinafter
RLL code) is used.

The RLL code is a code that limits the number of consecutive bits of the same binary value to d or more and k or less, and has such a property.
The code is obtained by converting an m-bit data word (bit length T) into an n-bit code word larger than m.

In the RLL code thus obtained, the length required to identify 1 bit (detection window width) The minimum inversion interval Tmin = d · T _ω .

Generally, in a recording / reproducing system, high frequency components are cut off, so that waveform interference occurs. It is desirable that Tmin be large in order to suppress this waveform interference.

Further, in order to suppress the influence due to time base fluctuation such as waveform interference and jitter, it is preferable that T _ω be large, and in addition, k be small in order to obtain a self-clocking function.

Conventionally, various RLL codes have been developed from the above viewpoint.

On the other hand, when using the RLL code, a decoding device that restores an n-bit code word into an m-bit data word is indispensable on the receiving or reproducing side.

In a conventional decoding device that directly restores an n-bit code word into an m-bit data word, the memory capacity V ₁ when a ROM is used for decoding is V ₁ = 2n · m. However, since the memory capacity V'essentially required for decoding is V '= 2 m · m, the memory utilization efficiency E is defined by the equation (1) as follows:
difference between n and _{m E = V 2 / V 1} = 2m - as n ...... (1) becomes larger, the utilization efficiency of the memory is exponentially worse.

For example, as shown in Table 1, d = 3, k = 7, m = 5, n = 12, and T _ω
In the case of RLL code of = 0.417T, it becomes as follows.

First, it is shown that the RLL code in Table 1 satisfies d = 3 and k = 7. As is clear from Table 1, 1 that satisfies d = 3 and k = 7
There are 32 2-bit codewords, and 32 (= 2
⁵ ) One-to-one correspondence is possible with the data word of the word.

In Table 1, the code words of the table pattern starting with 1 and the back pattern in which 1 of the table pattern is replaced by 0 and 0 is replaced by 1 are also shown. Correspondence between these code words and data words Makes one set of the front pattern and the back pattern to correspond to one data word. Then, the front pattern and the back pattern are selected as follows.

The number 1 of consecutive bits of the same binary value at the left end of the code word is 2
If F = 0,3 or more, the value F is set to F = 1. If the number of consecutive bits r of the same binary value at the right end of the codeword is 2 or less, E = 0,3 or more, E = 1. Using the value E and the value LB indicating the last bit of the code word, Y is set to Y = 0 when the code word is the front pattern and Y = 1 when the back pattern is the back pattern.

Assuming that E of the codeword transmitted immediately before is E ₁ , LB is LB ₁ , and F of the codeword to be transmitted is F ₂ , the codeword to be transmitted from the next is expressed by the following equation (2). Switch the back pattern.

However, "" is an exclusive OR, "." Is a logical product,
"-" Represents negation.

For example, No. 1 in Table 1 is used as the code word transmitted one before.
Suppose the codeword of the table pattern of. At this time, E ₁ = 1 and LB ₁
= 1. Next, if the codeword to be transmitted from now on is the No. 2 codeword in Table 1, F ₂ = 1. Therefore, from equation (2) It means that the code word to be transmitted from now on is the back pattern. As a result, as shown in FIG. 3, even if the code words are connected to each other, the number of consecutive bits having the same binary value is 3 or more and 7 or less even in the connection part underlined.

Similarly, regarding the connection between the code words in Table 1,
As long as equation (2) is obeyed, it can be seen that the connection portion always satisfies the restriction of d = 3 and k = 7.

RLL with d = 3, k = 7, m = 5, n = 12 shown in Table 1 above
When decoding the code, according to the conventional general method,
Volume V ₁ of the ROM for decoding is necessary ^{_{V 1 = 2 12 · 5 =}} 20480 bits.

The value columns in Table 1 will be described in the examples.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As described above, in an RLL code decoding device with d = 3, k = 7, m = 5, and n = 12, in order to identify code words having only 32 types at most, It uses all 12 bits. This causes the capacity of the ROM in the decoding device to become unnecessarily large.

It is generally known that increasing the code word length n can improve any of the above d, k, and T _ω . However, due to the ROM capacity of the decoding device, it was virtually impossible to use an RLL code with a large n.

Means for Solving the Problems In order to solve the above problems, the present invention aims to reduce the capacity of a ROM in a decoding device, divides n bits into a plurality of blocks, and temporarily divides each divided block. It is characterized by performing a two-step decoding operation of decoding and decoding a data word based on a combination of the results of the temporary decoding.

Operation According to the above configuration, for example, an n-bit codeword is divided into two blocks of n ₁ bits and n ₂ bits as shown in FIG. In addition, the number of bit patterns generated in this block of n ₁ bits is , N the number of bit patterns that occur in a _2- bit block And

At this time, the P ₁ bit patterns appearing in the n ₁ -bit block can be distinguished from each other by using the Q ₁ bit, and similarly, the P ₂ bit patterns appearing in the n ₂ -bit block include the Q ₂ bit. Can be distinguished from each other.

Therefore, in this case, n-bit codewords can be distinguished from each other by Q ₁ + Q ₂ bits. At this time, if both the means for temporarily decoding the bit pattern of the n _1- bit block into Q ₁ bits and the means for temporarily decoding the bit pattern of the n ₂ -bit block into Q ₂ bits are ROM, the decoding is required. ROM
The total capacity V ₂ of V is given by the following equation (3).

Generally, an n-bit codeword is divided into L small blocks, and the divided ni (1iL, The number of bit patterns that appear in a block of bits Then, the Pi bit patterns can be distinguished from each other by Qi bits, and therefore the total capacity of the ROM in the decoding device is given by the equation (4).

Therefore, if V _L <m · 2n, the ROM in the decoding device
Capacity is less than before. Since the first term of equation (4) is the ROM capacity required for temporary decoding, and the second term of equation (4) is the ROM capacity required for final decoding, If not set, the effect of reducing the ROM capacity is small.

On the other hand, the Pi bit patterns appearing in the ni-bit block can be distinguished from each other by Qi bits, but in order to make the Qi-bit information more effective, it is desirable that Pi be as close to a power of 2 as possible.

In summary, the following (i) and (ii) are guidelines for dividing an n-bit codeword.

(Ii) Pi2 ^Q i Example Next, with reference to examples, required for decoding apparatus according to the present invention
We show in detail that the total capacity of ROM is smaller and easier than before.

The RLL code used in this embodiment is d = 3, k = 7, shown in Table 1.
m = 5 and n = 12, thus Have the following characteristics.

The code word length of this RLL code is n = 12. In this embodiment, n = 12 is divided into two blocks of n ₁ = 6 and n ₂ = 6,
At this time, the bit pattern appearing in the first block of n ₁ = 6 bits and the bit pattern appearing in the second block of n ₂ = 6 bits are as shown in Table 2.

As is clear from Table 2, since the number of bit patterns of the first block P ₁ = 4 and the number of bit patterns of the second block P ₂ = 13, the above Q ₁ = 2, Q ₂ = 4. The values (hexadecimal notation) representing each bit pattern in Table 2 using Qi (i = 1,2) bits are R ₁ and R _{2 in} Table ₂ .

Therefore, the total ROM capacity required for the decryption device is given by the formula (3)
Becomes more ^{_{V 2 = 2 · 2 6 +4}} · 2 6 +5 · 2 6 = 704 bits.
This is about 1/29 of the ROM capacity V ₁ = 20480 bits required for the conventional decoding device.

For the back pattern input, the leading bit of the code word is 0, so that the back pattern can be easily detected. Therefore, in the case of the back pattern, it is returned to the front pattern and then sent to the decoding device of the present invention.

Next, the circuit configuration of the decoding device of the present invention will be described in detail with reference to the block diagram shown in FIG.

First, the code word that is reproduced is a serial-parallel converter 1 (S / P) and a 12-bit D flip-flop 2
(DFF) holds in codeword units. Then, the first bit of the 12-bit code word held in the D flip-flop 2 is sent to one input terminal of the 12-input exclusive OR gate 4 through the inverter 3, or the 12-input The output of the D flip-flop 2 is directly sent to the other input terminal of the exclusive OR gate 4.

By doing so, the code words of the table pattern always appear at the outputs of the twelve 2-input exclusive OR gates 4.

Next, of the code words of the table pattern appearing at the output terminals of the 12 2-input exclusive OR gates 4, the upper 6 bits, that is, the first block of the code words is sent to the address terminal of the ROM5,
On the other hand, the lower 6 bits, that is, the second block of the code word, is stored in the ROM6.
Send to the address terminal of.

As a result, the output of ROM5 corresponds to 6 bits of input
The bit value R ₁ appears and the output of ROM 6 shows the 4-bit value R ₂ corresponding to the 6 bits of the input.

Finally, when R ₁ and R ₂ having a total of 6 bits are sent to ROM 7, the output is shown in the value section of Table 1. Input R ₁ and
The data word corresponding to R ₂ appears, which is the output of the decoding device.

As described above, the circuit configuration of the present embodiment is extremely simple, and further, the ROM capacity is significantly reduced as compared with the conventional one, which is extremely useful in practice.

The present invention is effective not only for the RLL code used in this embodiment but also for all RLL codes, and the block division of the code word is not limited to two divisions, and even if it is three divisions or more.
Not only can the effect of reducing the total ROM capacity be maintained, but for RLL codes with a long codeword length, a larger R can be obtained by dividing the RLL code into three
Has the effect of reducing the total capacity of the OM.

EFFECTS OF THE INVENTION As described in detail above, according to the present invention, in an RLL code decoding device, an n-bit codeword is divided into a plurality of blocks, temporary decoding is performed for each divided block, and the result of the temporary decoding is By performing the two-step decoding operation of obtaining the final decoded value by using it, the total capacity of the ROM required for the decoding can be significantly reduced as compared with the conventional one with a simple circuit configuration. For example, for an RLL code with d = 3, k = 7, m = 5, n = 12,
The total ROM capacity can be reduced to approximately 1/29 that of conventional products.

As described above, by using the run-length limited code decoding apparatus according to the present invention, not only the decoding apparatus can be made smaller than the conventional one, but also the decoding apparatus can be made smaller, so that the RLL code having a longer code word length suitable for higher density recording can be obtained. Can be used, which is extremely effective in practice.

Although the effect of the present invention has been shown in this specification with the capacity of the ROM as one guideline, it goes without saying that the same effect can be obtained when the decoding device does not use the ROM and only the logic circuit is used for decoding. .

[Brief description of drawings]

FIG. 1 is an explanatory view of a code word divided into two parts, FIG. 2 is a block diagram of a decoding circuit in an embodiment of the present invention, and FIG. 3 is an explanatory view of connection between code words. 1 ... serial-parallel converter, 2 ... D flip-flop, 3 ... inverter, 4 ... exclusive OR gate, 5,6 ... ROM, 7 ... ROM.

Claims (6)

[Claims] 1. An m-bit data word is converted into an n-bit code word, and the number of consecutive bits of the same binary value in a bit string generated by the connection of the converted n-bit code words is d.
In a decoding device for a run-length limited code, which reverse-converts an n-bit run-length limited code limited to k or less into an m-bit data word, this n-bit is given to an integer value L of 2 or more, With respect to the positive integer value Qi, a dividing unit that divides into L blocks each of which has ni bits
The number of bit patterns pi that appears in an ni-bit block is 2 _Q i
^-1 and less than or equal to 2 _Q i, all of the output of the provisional decoding means and the provisional decoding means for outputting the information of the _Q i bit for distinguishing each ni bit as an output to the input of the ni bit And a final decoding means for outputting a data word corresponding to the n-bit code word on the basis of the input, and a decoding device for a run-length limited code. 2. When a code word starting with 1 is called a table pattern and a code word starting with 0 is called a back pattern, the dividing means also has a means for converting the code word to be decoded into a table pattern. A decoding device for a run-length limited code according to claim 1. 3. i, ni, Qi, m and Run length limited of Qi · 2ni <m · 2 _Q and the pi is a power of two in the ni so that the close values, and the claims paragraph 1, wherein the choosing i against Code decoding device. 4. The dividing means comprises a serial-in / parallel-out shift register and a D flip-flop, the temporary decoding means is a memory having the ni bit input and the Qi bit output, and the final decoding means is 4. The run length limited code decoding device according to claim 3, which is a memory for bit input and m bit output. 5. The decoding device for run-length limited code according to claim 4, wherein the memory is a Read Only Memory. 6. For run-length limited codes with d = 3, k = 7, m = 5 and n = 12, said L = 2, n ₁ =
6, n ₂ = 6. Claim 4
A run length limited code decoding device according to the above item.