JPH0693231B2 - Pseudo-fault generation method for cache memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an information processing apparatus having a function of generating a pseudo fault in order to test an error processing function of a cache memory in which the same address has a plurality of levels. .

[Conventional technology]

Conventionally, this type of information processing apparatus has the configuration shown in FIG. The cache memory 3 described here is a 4-level case. In the normal operation, that is, the operation other than testing the error handling function using the pseudo fault, the contents of the levels 0, 1, 2, and 3 of the degrade register 4 are all "0", and all the levels of the cache memory 3 are Is used, and the output of the inverter gates 81 to 84 becomes "1". Further, the contents of the pseudo failure instruction flag 6 in the diagnostic control unit 1 are also
The contents of each level of the pseudo fault indication level register 7 are all "0", indicating that there is no pseudo fault, and AND gate
Pseudo fault indication signals 16 to 19 of each level, which are outputs of 12 to 15
Becomes "0". As a result, the outputs of the parity check circuits 31 to 34 are the OR circuits 35 to 38 and the AND circuits 41 to 4 respectively.
It is input to EIF45 to 48 of each level through 4 as it is. Therefore, the data of each level operates in a checkable state.

Next, in order to confirm whether or not the error processing function that operates when a parity error occurs at any level in the read of the cache memory 3 is normal, a pseudo fault, that is, a read data is forced to have a parity error, or
The operation when the test is performed by forcibly turning on the EIF will be described. When the diagnostic control unit 1 puts "1" in the pseudo failure indication level register 7 at a level where a pseudo failure is to occur, for example, level 0 and "1" in the pseudo failure indication flag 6, the AND gate 12 The output level 0 pseudo fault instruction signal 16 is "1". Since the contents of the other levels of the pseudo fault instruction level register 7 are "0" and the contents of the degrade level register 4 are all "0", the levels 1 to 3 pseudo fault instruction signals 17 to 19 are "0", the inverter gate 81 ~ 84
Is "1" and the outputs of the parity check circuits 31 to 34 are "0", the outputs of the OR gate 35 and the AND gate 41 are "1", and the level 0EIF is "1". As a result, a level 0 parity error is reported, and the error processing function operates. Therefore, it is possible to test whether the operation is normal. After the level 0 parity error is generated, the diagnostic control unit 1 puts "1" into the level 0 of the degraded level register 4 and always sets the output of the AND gate 41 to "0", and does not report the level 0 parity error. To do so.

Although not shown, the output of the degrade level register 4 is also sent to the hit control of the cache memory 3, and the level which is "1" in the degrade level register 4 is controlled so as not to hit. After the level 0 of the cache memory 3 is cut off by inserting "1" into the level 0 of the degrade level register 4, the diagnostic control unit 1
Performs the same as for level 0 for levels 1, 2, and 3 and tests at which level the error processing function operates normally even if a parity error occurs. Here, the case where the cache memory has four levels has been described.
As shown by the levels 0 to 3 pseudo failure instruction signals 16 to 19 in the figure, as many interfaces as the levels are provided between the diagnostic control unit 1 and the cache storage device 2.

[Problems to be solved by the invention]

In the above-mentioned conventional pseudo failure generation method, the number of levels of the pseudo failure instruction level register and the number of pseudo failure instruction signals between the diagnostic control unit and the cache storage device must be the same as the number of cache storage levels. However, if there are many levels of cache storage, it has the drawback of leading to an increase in hardware and interfaces. Therefore, this is inconvenient when it is desired to minimize the hardware and interfaces of functional circuits that are not related to normal operation and processing speed.

[Means for solving problems]

According to the pseudo failure generation method of a cache storage device of the present invention, in order to test the error processing function of a cache storage in which the same address has a plurality of levels, in an information processing device having the function of generating a pseudo failure, It has means for instructing at which level among a plurality of levels the pulse width is caused, and means for obtaining the level at which the pseudo fault is caused from the pulse width of the instruction.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention. Similar to the prior art, the cache memory 3 is shown as having four levels.

The content of the pseudo failure instruction flag 6 in the diagnostic control unit 1 is "0" except when the pseudo failure is tested and the error processing function is tested. Therefore, the pseudo failure instruction signal 11 is "0", the pseudo failure instruction acceptance Flag 9 also becomes "0" and AND gates 72, 61-6
The outputs of 4 are all "0". Since the contents of the degrade level register 4 are all "0", the outputs of the inverter gates 81 to 84 are all "1", and the outputs of the parity check circuits 31 to 34 are the OR gates 35 to 38 and the AND gates 41 to 4 respectively.
It goes through 4 and is output to EIF45 to 48 of each level as it is. Therefore, the data of each level operates in a checkable state.

Next, a case where a pseudo fault is caused to test the error processing function will be described. As an initial state for generating a pseudo fault for testing the error processing function, the outputs of the parity check circuits 31 to 34 of each level are all "0", the contents of the downgrade register 4 are all "0", and the pseudo fault instruction flag 6 Is "0", pseudo fault reception counter 5, pseudo fault instruction reception flag 9, and pseudo fault transmission counter 8 are all "0"
Is. If the number of bits of the pseudo fault transmission / reception counters 8 and 5 is k, k = log _{2 in the} n-level cache memory.
Calculated by n.

Now, assume that a pseudo fault occurs at level 0. “0” “0” (indicating level 0) is set in the pseudo fault instruction level register 7 and the pseudo fault instruction flag 6 is set to “1”. At this time, since the value of the pseudo fault instruction level register 7 is "0""0" and the content of the pseudo fault transmission counter 8 is also "0""0", the comparator 10
Output is "1". Therefore, since the reset condition of the pseudo fault instruction flag 6 is satisfied, the machine clock is set to 1
As the clock advances, the value of the pseudo fault instruction flag 6 changes from "1" to "0", and the pseudo fault instruction signal 11 becomes "1" for only one machine cycle. Therefore, since the pulse of "1" is generated only for one machine cycle in which the pseudo fault instruction acceptance flag 9 becomes "1", the output of the inverter gate 71 is "1" when the pseudo fault instruction acceptance flag 9 is "1". Therefore, the output of the AND gate 72 becomes "1". At this time, the content of the pseudo fault reception counter is "0" and "0", so the AND gate with inverted output 5
Both 1,52 non-inverted output side is "0", both inverted output sides are "1"
And the outputs of AND gates 61 to 64 are "1" and "0" respectively.
It becomes “0” and “0”. And the degraded level register 4
The contents of all are "0", so the outputs of the inverter gates 81 to 84 are all "1", the outputs of the AND gates 61 to 64 pass through the OR gates 35 to 38, and the AND gates 41 to 44, and the EIF45 of each level. Since it is output to ~ 48, only level 0 EIF becomes "1" and is processed as a level 0 parity error.

Here, "1" is put into the level 0 of the degradation level register 4. Although not shown, the output of the degrade level register 4 is also sent to the hit control of the cache memory 3, and the AND gate 41 is always set to "0" and works to suppress the level 0 hit.

It is assumed that a pseudo fault occurs in level 2 after disconnecting level 0. Level 0 of degraded level register 4
Set to the above-mentioned initial state except that "1" is entered. In this state, "1" is set in the pseudo failure instruction flag 6 and "1""0" indicating level 2 is entered in the pseudo failure instruction level register 7. At this time, the pseudo fault transmission counter 8 which is the output of the pseudo fault instruction flag 6 is set. In this state, the contents of the pseudo fault transmission counter 8 become "0" and "1" after one machine cycle, and become "1" and "0" after one machine cycle. At this time, since the contents of the pseudo fault instruction level register 7 and the pseudo fault transmission counter 8 match, the output of the comparator 10 becomes "1", and the reset condition of the pseudo fault instruction flag 6 is satisfied. Therefore, the pseudo failure indication flag 6 becomes "0" after one more machine cycle, and the total of 3
The pseudo fault instruction signal 11 becomes "1" during the machine cycle.

When this signal is sent to the cache memory device 2, as shown in FIG. 2, the output of the inverter gate 71 becomes "0" for 3 machine cycles, while the output of the pseudo fault instruction acceptance flag 9 is 1 machine. Since only three machine cycles are delayed by one cycle and become "1", the output of the AND gate 72 is "1" for the same period as the last one machine cycle among the three machine cycles in which the pseudo failure instruction acceptance flag 9 is "1". Becomes Since the output of the pseudo fault instruction reception flag 9 is a setting condition of the pseudo fault reception counter 5, it is counted up for 3 machine cycles, that is, "1" and "1". During this period, the output of the AND gate 72 described above becomes "1" and the AND gates 61 to 64 are enabled only when the content of the pseudo fault reception counter 5 is "1""0". , AND gate 63 only becomes "1", and AND gates 61, 62, 64 remain "0". Therefore, the outputs of OR gates 35 to 38 are "0" and "0".
Since it is "1" and "0" and only level 0 of the degraded level register 4 is "1", only AND gate 43 of AND gates 41 to 44 becomes "1" and EIF47 of level 2 becomes "1". , A level 2 error occurs.

From the above, it can be seen that pseudo faults of level 0 and level 2 could be set arbitrarily. The same can be said for levels 1 and 3, and pseudo faults can be set at any level.

〔The invention's effect〕

As described above, the present invention is configured to have a means for instructing at which level of a plurality of levels a pseudo obstacle is caused by a pulse width, and a means for obtaining a level causing a pseudo obstacle from the pulse width of the instruction. As a result, there is an effect that a pseudo fault can be caused by one pseudo fault instruction signal regardless of the number of cache storage levels. Moreover, there is an effect that a pseudo fault can be caused at any level.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing an example of the operation of FIG. 1, and FIG. 3 is a diagram showing a prior art. 1 ... Diagnostic control unit, 2 ... Cache storage device, 3 ... Cache storage, 4 ... Degrade level register, 5 ... Pseudo fault reception counter, 6 ... Pseudo fault instruction flag, 7 ... Pseudo fault instruction Level register, 8 ... counter for sending pseudo fault, 9 ... Flag for accepting pseudo fault instruction, 10 ... Comparator, 11 ...
Pseudo-fault indication signal, 31 to 34 ... Parity check circuit, 35
~ 38 …… OR gate, 41∼44 …… AND gate, 45 …… Level 0 EIF, 46 …… Level 1 EIF, 47 …… Level 2 EIF, 48 ……
Level 3 EIF, 51 to 52 ... AND gate with inverted output, 61 to 6
4,72 …… And gate, 71,81〜84 …… Inverter gate.

Claims (1)

[Claims] 1. An information processing apparatus having a function of generating a pseudo fault for testing an error processing function of a cache memory in which the same address has a plurality of levels, causes the pseudo fault at any one of the plurality of levels. A pseudo failure generation method for a cache storage device, comprising: means for instructing whether the pulse width is a pulse width and means for determining a level causing a pseudo failure from the pulse width of the instruction.