JPH0693495B2 - Semiconductor device protection circuit - Google Patents
Semiconductor device protection circuitInfo
- Publication number
- JPH0693495B2 JPH0693495B2 JP60280842A JP28084285A JPH0693495B2 JP H0693495 B2 JPH0693495 B2 JP H0693495B2 JP 60280842 A JP60280842 A JP 60280842A JP 28084285 A JP28084285 A JP 28084285A JP H0693495 B2 JPH0693495 B2 JP H0693495B2
- Authority
- JP
- Japan
- Prior art keywords
- effect transistor
- semiconductor device
- voltage
- protection circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、Ｃ−MOSFETなどからなる半導体装置の保護
回路に係り、特に、静電破壊およびラッチアップによる
破壊の防止に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection circuit for a semiconductor device including a C-MOSFET and the like, and more particularly to prevention of electrostatic breakdown and breakdown due to latch-up.
従来、Ｃ−MOS回路では、第２図に示すように、ｐチャ
ネルエンハンスメントMOS電界効果トランジスタ（以下
単にpMOSFETという）２にｎチャネルエンハンスメントM
OS電界効果トランジスタ（以下単にnMOSFETという）４
を直列に接続するとともに、共通に接続した各ゲートに
対して抵抗６を介して入力端子（ピン）８が形成されて
いる。Conventionally, in a C-MOS circuit, as shown in FIG. 2, a p-channel enhancement MOS field effect transistor (hereinafter simply referred to as pMOSFET) 2 has an n-channel enhancement M.
OS field effect transistor (hereinafter simply referred to as nMOSFET) 4
Are connected in series, and an input terminal (pin) 8 is formed for each of the commonly connected gates via a resistor 6.
そして、入力端子８に加わる高電圧（数KV）の静電気に
よる破壊からpMOSFET2およびnMOSFET4を保護するため、
入力端子８とpMOSFET2のソースとの間にはダイオード10
がカソードを高電位側にして接続され、また、入力端子
８とnMOSFET4のソースとの間にもダイオード12が接続さ
れている。Then, in order to protect the pMOSFET 2 and the nMOSFET 4 from being destroyed by static electricity of high voltage (several KV) applied to the input terminal 8,
A diode 10 is connected between the input terminal 8 and the source of pMOSFET2.
Is connected with the cathode on the high potential side, and the diode 12 is also connected between the input terminal 8 and the source of the nMOSFET 4.
このようなダイオード10、12による保護回路は、静電破
壊およびラッチアップによる破壊からpMOSFET2およびnM
OSFET4を保護するために一般的に用いられているが、通
常、nMOSFET4のソースを接地側に設定し、pMOSFET2とnM
OSFET4のソース間に電圧VDDを印加するための電源14
は、その出力部のトランジスタ16で示すように、矢印Ａ
で示す方向に高インピーダンスとなるため、ダイオード
10による保護は殆ど期待できない。The protection circuit consisting of such diodes 10 and 12 protects pMOSFET2 and nM from the damage due to electrostatic breakdown and latch-up.
It is commonly used to protect OSFET4, but usually the source of nMOSFET4 is set to ground and pMOSFET2 and nM
Power supply 14 for applying voltage V DD between the sources of OSFET4
Is the arrow A as indicated by the transistor 16 at its output.
Since the impedance becomes high in the direction indicated by, the diode
Little protection can be expected from 10.
そこで、このような半導体装置において、入力端子（ピ
ン）に加わる高電圧からゲート酸化膜を保護した保護回
路の提供を目的とする。Therefore, in such a semiconductor device, it is an object to provide a protection circuit in which a gate oxide film is protected from a high voltage applied to an input terminal (pin).
この発明の半導体装置の保護回路は、第１図に例示する
ように、ｐチャネル電界効果トランジスタ（pMOSFET2）
とｎチャネル電界効果トランジスタ（nMOSFET4）とから
なる相補型回路を備える半導体装置の保護回路であっ
て、前記相補型回路のゲート入力部と接地点との間にｐ
チャネル電界効果トランジスタ（pMOSFET18）を設置す
るとともに、接地側をアノードにしたダイオード（12）
を設置し、前記ｐチャネル電界効果トランジスタのゲー
トに前記相補型回路の駆動電圧を加え、ゲート入力電圧
が前記相補型回路の駆動電圧を越える高電圧になったと
き、前記ｐチャネル電界効果トランジスタを導通状態に
して前記相補型回路を保護するようにしたことを特徴と
する。A protection circuit for a semiconductor device according to the present invention has a p-channel field effect transistor (pMOSFET2) as shown in FIG.
A protection circuit for a semiconductor device comprising a complementary circuit composed of an n-channel field effect transistor (nMOSFET4) and a p-type gate between a gate input portion of the complementary circuit and a ground point.
A diode (12) with a channel field-effect transistor (pMOSFET18) installed and an anode on the ground side
And a drive voltage of the complementary circuit is applied to the gate of the p-channel field effect transistor, and when the gate input voltage becomes a high voltage exceeding the drive voltage of the complementary circuit, the p-channel field effect transistor is turned on. It is characterized in that the complementary circuit is protected by making it conductive.
この発明の半導体装置の保護回路は、相補型回路のゲー
ト入力部と接地側との間に設置したｐチャネル電界効果
トランジスタ（18）が、ゲート入力電圧が前記相補型回
路の駆動電圧を越える高電圧（たとえば、電圧VDDとnMO
SFETのスレシュホールド電圧VTHとを加えた電圧）にな
ったとき導通状態になるので、その導通状態によって、
ゲート入力部に加わる電荷を接地側に放流するので、pM
OSFETおよびnMOSFETの高電圧入力による破壊から保護す
ることができる。In the protection circuit for a semiconductor device according to the present invention, a p-channel field effect transistor (18) installed between the gate input portion of the complementary circuit and the ground side has a high gate input voltage exceeding the driving voltage of the complementary circuit. Voltage (eg voltage VDD and nMO
SFET threshold voltage V TH + voltage), it becomes conductive.
Since the charge applied to the gate input section is discharged to the ground side, pM
It can protect the OSFET and nMOSFET from damage due to high voltage input.
以下、この発明の実施例を図面を参照して説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は、この発明の半導体装置の保護回路の実施例を
示す。FIG. 1 shows an embodiment of a protection circuit for a semiconductor device according to the present invention.
この半導体装置の保護回路は、第１図に示すように、nM
OSFET2とnMOSFET4とからなる相補型回路のゲート入力部
と接地側との間に、第２図に示すダイオード10に代える
ゲート入力電圧が前記相補型回路の駆動電圧を越える高
電圧になったとき導通状態になる能動素子としてpMOSFE
T18を設置したものである。この場合、pMOSFET18は、ソ
ース側を入力端子８側、ドレイン側を接地側、ゲートを
pMOSFET2のソースと共通に電源14側に接続されている。As shown in FIG. 1, the protection circuit of this semiconductor device has an nM
Conduction between the gate input of the complementary circuit consisting of OSFET2 and nMOSFET4 and the ground side when the gate input voltage replacing the diode 10 shown in FIG. 2 becomes a high voltage exceeding the driving voltage of the complementary circuit. PMOSFE as active device
It has T18 installed. In this case, the pMOSFET 18 has a source side on the input terminal 8 side, a drain side on the ground side, and a gate on the side.
It is connected to the power supply 14 side in common with the source of pMOSFET 2.
したがって、入力端子８に対して、pMOSFET2とnMOSFET4
との相補型回路に加えられる駆動電圧VDDを越える高電
圧が印加された場合、その値が電圧VDDとpMOSFET18のス
レシュホールド電圧VTHとを加えた電圧（VDD＋VTHQ18）
を越えているとき、pMOSFET18は導通状態となり、入力
端子８に加わる静電電荷を接地側に放流する。Therefore, for input terminal 8, pMOSFET2 and nMOSFET4
When a high voltage exceeding the drive voltage V DD applied to the complementary circuit with is applied, its value is the voltage that is the voltage V DD and the threshold voltage V TH of the pMOSFET 18 (V DD + V THQ18 )
When it exceeds, the pMOSFET 18 becomes conductive, and the electrostatic charge applied to the input terminal 8 is discharged to the ground side.
このような保護動作は、電源14のインピーダンスには全
く無関係に行われるので、静電破壊およびラッチアップ
による破壊からpMOSFET2およびnMOSFET4を確実に保護で
きる。Since such a protection operation is performed regardless of the impedance of the power supply 14, the pMOSFET 2 and the nMOSFET 4 can be reliably protected from electrostatic breakdown and breakdown due to latch-up.
この場合、pMOSFET18が導通した場合、静電電荷による
電流は、直接接地側に放流されて、基板のバルク内に持
ち込むことがないので、ラッチが生じ難い構成を実現で
きる。In this case, when the pMOSFET 18 becomes conductive, the current due to the electrostatic charge is not discharged directly to the ground side and is not brought into the bulk of the substrate, so that the configuration in which the latch hardly occurs can be realized.
以上説明したように、この発明によれば、ｐチャネル電
界効果トランジスタとｎチャネル電界効果トランジスタ
とからなる相補型回路のゲート入力部とゲート入力部と
接地点との間にｐチャネル電界効果トランジスタを設置
するとともに、接地側をアノードにしたダイオードを設
置し、ｐチャネル電界効果トランジスタのゲートに相補
型回路の駆動電圧を加え、ゲート入力電圧が相補型回路
の駆動電圧を越える高電圧になったとき、ｐチャネル電
界効果トランジスタを導通状態にしてゲート入力部に加
わる電荷を接地側に放流することができるので、高電圧
入力による破壊から半導体装置を保護でき、しかも、電
荷は直接接地側に放流されるため、基板のバルク内に持
ち込まれることがなく、ラッチの発生をも防止でき、信
頼性の高い半導体装置を提供することができる。As described above, according to the present invention, the p-channel field effect transistor is provided between the gate input section and the gate input section of the complementary circuit including the p-channel field effect transistor and the n-channel field effect transistor, and the ground point. When a diode with the ground side as the anode is installed and the driving voltage of the complementary circuit is applied to the gate of the p-channel field effect transistor, the gate input voltage becomes a high voltage exceeding the driving voltage of the complementary circuit. Since the p-channel field effect transistor can be made conductive and the charge applied to the gate input portion can be discharged to the ground side, the semiconductor device can be protected from being destroyed by the high voltage input, and the charge can be directly discharged to the ground side. Therefore, it is prevented from being brought into the bulk of the substrate, and it is possible to prevent the occurrence of latches, and it is a highly reliable semiconductor. It is possible to provide a location.
第１図はこの発明の半導体装置の保護回路の実施例を示
す回路図、第２図は従来の半導体装置の保護回路を示す
回路図である。 ２…pMOSFET ４…nMOSFET 12…ダイオード 18…pMOSFET。FIG. 1 is a circuit diagram showing an embodiment of a protection circuit for a semiconductor device of the present invention, and FIG. 2 is a circuit diagram showing a protection circuit for a conventional semiconductor device. 2 ... pMOSFET 4 ... nMOSFET 12 ... diode 18 ... pMOSFET.
Claims (1)
ネル電界効果トランジスタとからなる相補型回路を備え
る半導体装置の保護回路であって、 前記相補型回路のゲート入力部と接地点との間にｐチャ
ネル電界効果トランジスタを設置するとともに、接地側
をアノードにしたダイオードを設置し、前記ｐチャネル
電界効果トランジスタのゲートに前記相補型回路の駆動
電圧を加え、ゲート入力電圧が前記相補型回路の駆動電
圧を越える高電圧になったとき、前記ｐチャネル電界効
果トランジスタを導通状態にして前記相補型回路を保護
するようにしたことを特徴とする半導体装置の保護回
路。1. A protection circuit for a semiconductor device comprising a complementary circuit composed of a p-channel field effect transistor and an n-channel field effect transistor, wherein a p-channel is provided between a gate input part of the complementary circuit and a ground point. A field-effect transistor is installed, a diode whose ground side is an anode is installed, and a driving voltage of the complementary circuit is applied to the gate of the p-channel field-effect transistor, and a gate input voltage is the driving voltage of the complementary circuit. A protection circuit for a semiconductor device, characterized in that the p-channel field effect transistor is turned on to protect the complementary circuit when a high voltage is exceeded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60280842A JPH0693495B2 (en) | 1985-12-13 | 1985-12-13 | Semiconductor device protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60280842A JPH0693495B2 (en) | 1985-12-13 | 1985-12-13 | Semiconductor device protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62139349A JPS62139349A (en) | 1987-06-23 |
| JPH0693495B2 true JPH0693495B2 (en) | 1994-11-16 |
Family
ID=17630743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60280842A Expired - Lifetime JPH0693495B2 (en) | 1985-12-13 | 1985-12-13 | Semiconductor device protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0693495B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR920009015A (en) * | 1990-10-29 | 1992-05-28 | 김광호 | Protection circuit of semiconductor chip |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL176322C (en) * | 1976-02-24 | 1985-03-18 | Philips Nv | SEMICONDUCTOR DEVICE WITH SAFETY CIRCUIT. |
-
1985
- 1985-12-13 JP JP60280842A patent/JPH0693495B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62139349A (en) | 1987-06-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |