JPH0693445B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming metal wiring by electroless plating.

[Conventional technology]

According to the conventional method of forming a metal wiring by electroless plating, first, a plating film is deposited on a required portion of the metal wiring composed of the Si substrate 704, the diffusion layer 703, the conductive film 705, and the interlayer insulating film 701 as shown in FIG. As a catalyst nucleus of, a layer 712 made of a metal such as palladium or zinc (hereinafter referred to as a catalyst metal) is previously deposited by vapor deposition, sputter chemical vapor deposition (CVD method) or in a solution containing catalyst metal ions. It is formed by ion substitution or the like, followed by electroless plating, and electroless plating metal film 706 is formed on the catalyst metal 712 as shown in FIG.
(Hereinafter, referred to as a plating film) was formed, and then unnecessary portions of this plating film 706 were removed.

[Problems to be Solved by the Invention] In the above-mentioned conventional method, it is necessary to previously form a catalyst metal used as a catalyst nucleus for plating film deposition by vapor deposition, sputtering, or an ion substitution method. There are drawbacks.

(1) Since the plating film is formed on all the portions where the catalyst metal is present, a step of removing an unnecessary portion is required after forming the plating film.

(2) When depositing a catalytic metal in a contact hole having a high aspect ratio, the catalytic metal is not deposited uniformly, the plating film is likely to be uneven, and it is difficult to obtain stable electrical characteristics. Embedded yield is reduced.

[Means for solving problems]

A method of manufacturing a semiconductor device of the present invention has a step of contacting a first semiconductor region of one conductivity type on a semiconductor substrate to form a second semiconductor region of another conductivity type, and the semiconductor substrate having a catalytic action. By irradiating the first semiconductor region and the second semiconductor region with light in a state of being immersed in a solution containing metal ions, the first semiconductor region or the second semiconductor region having the catalytic action can be obtained. And a step of selectively forming the second metal layer on the first metal layer by electroless plating.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a vertical sectional view of an embodiment of the present invention. Si substrate 10
The interlayer insulating film 101 and the n-type diffusion layer 103 on the upper part of the contact hole 102 are used as the bottom portion of the contact hole 102, and as shown in FIG. 2, for example, W, Mo, Ti and their silicides are formed on the bottom portion of the contact hole 102. The conductive film 105 is formed by a selective growth method using a chemical vapor deposition method. This conductive film 105 is used for the purpose of preventing the plating film deposited by electroless plating and the Si substrate 104 from contacting, diffusing and reacting.

Next, as shown in FIG. 4, an electroless plating solution 407 composed of, for example, sodium hypophosphite as a reducing agent, sodium citrate as a complexing agent, Ni as a metal ion to be reduced, and this electroless plating. The initial catalytic metal film 107 is formed by immersing the Si substrate 404 in an electroless plating bath composed of a constant temperature bath 408 used for the purpose of keeping the temperature of 407 constant at 90 ° C. and irradiating the Si substrate with light by a lamp 409. Plating.

An enlarged view of the contact hole portion during plating is shown in FIG. In this example, the n-type diffusion layer 103 is formed on the bottom of the contact hole.
Are formed, and a pn junction is formed together with the P-type Si substrate 104. Light having a wavelength of, for example, 8000Å is applied to the Si substrate through the conductive film 105 or the interlayer insulating film 101 at 10 cm / cm ^2.
Irradiation with an intensity of mW generates electron-hole pairs in the P-n junction. When the electrons move from the n-type diffusion layer 103 to the P-type Si substrate 104, a current flows from the P-type Si substrate 104 to the n-type diffusion layer 103. This is deposited on the conductive film 105 as the initial catalytic metal film 1
Let 07 be the plating current for forming by the plating method.

After forming the catalytic metal film 107 by this method, an alloy such as Cu, Ni and Ni-P, Ni-B, or Co and Co-
By immersing the Si substrate 104 in an electroless plating solution in which an alloy such as WP is used as a deposition metal, the plating film 106 is formed inside the contact hole 102 at a film forming rate of several hundred to several thousand Å / min.
It is possible to perform electroless plating for selectively depositing on. When the plating film is similar to the initial catalytic metal film 107, it is not necessary to change the electroless plating solution to be dipped. If electroless plating is immediately performed on the diffusion layer without light irradiation, the plating film is not formed because the catalytic metal film 107 and its substitute are not present. Here catalytic metal film 10
As the metal used for 7, a metal having a lower standard electrode potential than the metal used for the conductive film 105 and a high adsorptivity for the metal used for the conductive film 105 is used. Further, the plating film 106 formed in this way is S
The conductive film 105 need not be used if it has a low reactivity with i. In this case, as the metal used for the catalytic metal film 107, one having a lower standard electrode potential than Si and a high adsorptivity to Si is used.

FIG. 5 is a vertical sectional view of another embodiment of the present invention. The basic structure is the same as that of the first embodiment, but two contact holes are provided.
An n-type diffusion layer 503 is provided at the bottom of 502a and 502b, and P is provided between the two.
The P type diffusion layer 510a, the interlayer insulating film 501, the base electrode 511, and the P type diffusion layer 510b and the Si substrate 504 under the n type diffusion layer have a PnP junction bipolar transistor structure. . When the Si substrate is irradiated with light and electroless plating is performed as in the one embodiment, a current flows from the P-type diffusion layers 510a and 510b to the n-type diffusion layer 503, and the initial catalytic metal film is formed on the conductive film 505.
It becomes a plating current for forming 512 by the plating method. By this method, it is possible to form a metal wiring inside the contact hole as in the embodiment as shown in FIG.

〔The invention's effect〕

In the method for forming a metal wiring in a contact hole of the present invention, a substrate is irradiated with light to generate a plating current, and the metal is selectively deposited by utilizing this current. Therefore, a catalytic metal film is provided, and then this is selected. The process of removing it became unnecessary. Further, the selection range of the catalytic metal film and the wiring material is widened, and since the same metal can be used, the reaction between them can be prevented, stable electric characteristics can be obtained, and the process can be further shortened. effective.

The present invention has a high throughput as compared with the conventional sputter method or CVD method which is a metal wiring forming technique in a contact hole, and if the bottom of the contact hole is a semiconductor device having a P-n junction of an n-type diffusion layer, a MOS It goes without saying that it is applicable regardless of the type of bipolar or the like and the type of semiconductor substrate.

[Brief description of drawings]

1, 2 and 3 are longitudinal sectional views showing a manufacturing process according to one embodiment of the present invention, and FIG. 4 is a longitudinal sectional view of an apparatus used in one embodiment of the present invention and another embodiment. , Fifth
FIG. 6 and FIG. 6 are vertical sectional views showing a manufacturing process according to another embodiment of the present invention, and FIGS. 7 and 8 are vertical sectional views showing a metal wiring forming process in a contact hole by a conventional electroless plating method. Is. 101,501,701 ... Interlayer insulation film, 102,502,702 ... Contact hole, 103,503,703 ... n-type diffusion layer, 104,404,504,7
04 …… Si substrate, 105,505 …… conductive film, 106,506,706 …… plating film, 107,512 …… catalytic metal film, 407 …… electroless plating solution, 408 …… constant bath, 409 …… lamp, 510a, 510b
…… P-type diffusion layer, 511 …… Base electrode, 712 …… Catalyst metal.

Claims (1)

[Claims] 1. A step of contacting a first semiconductor region of one conductivity type on a semiconductor substrate to form a second semiconductor region of another conductivity type, and a solution containing metal ions having a catalytic action on the semiconductor substrate. By irradiating the first semiconductor region and the second semiconductor region with light in a state of being immersed in the substrate, an electron-hole pair is generated at a P-N junction between the first and second semiconductor regions. And selectively forming the first metal layer having the catalytic action on the first semiconductor region or the second semiconductor region by an electric current based on the movement of the first semiconductor region and the first metal layer by electroless plating. Second on the metal layer of
And a step of forming a metal layer, the method for manufacturing a semiconductor device.