JPH0691227B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0691227B2 JPH0691227B2 JP59023178A JP2317884A JPH0691227B2 JP H0691227 B2 JPH0691227 B2 JP H0691227B2 JP 59023178 A JP59023178 A JP 59023178A JP 2317884 A JP2317884 A JP 2317884A JP H0691227 B2 JPH0691227 B2 JP H0691227B2
- Authority
- JP
- Japan
- Prior art keywords
- mos
- cmos
- soi
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device.
従来例の構成とその問題点 近年、絶縁基板上に形成された相補型MOS（Ｃ−MOS）が
重要視されてきた。Configuration of Conventional Example and Problems Thereof In recent years, a complementary MOS (C-MOS) formed on an insulating substrate has been emphasized.
以下、図面を参照しながら、従来のSOI−CMOSについて
説明を行う。Hereinafter, a conventional SOI-CMOS will be described with reference to the drawings.
第１図は従来のSOI−CMOSの模式的断面図を示すもので
ある。第１図において、１は絶縁基板、２はＰチャンネ
ル型MOS（Ｐ−MOS）、３はＮチャンネル型MOS（Ｎ−MO
S）、４はゲート電極、５は配線である。FIG. 1 is a schematic sectional view of a conventional SOI-CMOS. In FIG. 1, 1 is an insulating substrate, 2 is a P-channel type MOS (P-MOS), 3 is an N-channel type MOS (N-MO).
S), 4 is a gate electrode, and 5 is a wiring.
以上のように絶縁基板１上に作られたSOI−CMOSは、基
板との寄生容量が小さいため高速動作が可能である。さ
らに、ラッチアップがない，高耐圧，ソフトエラーに強
い、といった特長を持っている。The SOI-CMOS formed on the insulating substrate 1 as described above can operate at high speed because of its small parasitic capacitance with the substrate. Furthermore, it has features such as no latch-up, high breakdown voltage, and resistance to soft errors.
しかし、上記のような構造のSOI−CMOSを製作するに
は、絶縁基板上に単結晶を成長させてMOSのチャネル領
域を形成しなければならない。ところが、絶縁基板上に
良質の単結晶を成長させるのは、困難である。However, in order to manufacture the SOI-CMOS having the above structure, it is necessary to grow a single crystal on an insulating substrate to form a MOS channel region. However, it is difficult to grow a good quality single crystal on an insulating substrate.
発明の目的 本発明は上記欠点に鑑み、単結晶基板に形成したＣ−MO
SをSOI−CMOSにするための半導体装置の製造方法を提供
するものである。SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks, the present invention is directed to a C-MO formed on a single crystal substrate.
A method of manufacturing a semiconductor device for making S into SOI-CMOS.
発明の構成 この目的を達成するために本発明の半導体装置の製造方
法は、単結晶基板に作ったＣ−MOSを絶縁基板に接着
し、前記単結晶基板の不必要な部分を除去することから
構成されている。According to the method for manufacturing a semiconductor device of the present invention, in order to achieve this object, a C-MOS formed on a single crystal substrate is adhered to an insulating substrate and unnecessary portions of the single crystal substrate are removed. It is configured.
この構成により、絶縁基板上に単結晶を成長させるプロ
セスが不必要になり、容易にSOI−CMOSを製作すること
が出来る。With this configuration, a process for growing a single crystal on an insulating substrate is unnecessary, and an SOI-CMOS can be easily manufactured.
実施例の説明 以下、図面を用いて、本発明の一実施例を詳細に説明す
る。Description of Embodiments An embodiment of the present invention will be described in detail below with reference to the drawings.
先ず、第２図に示すように、標準的なＣ−MOS半導体プ
ロセスで、Ｎ型シリコン基板11にＣ−MOSを形成する。
第２図において、12はＰ−MOS、13はＮ−MOS、14はゲー
ト電極、15は配線である。First, as shown in FIG. 2, a C-MOS is formed on the N-type silicon substrate 11 by a standard C-MOS semiconductor process.
In FIG. 2, 12 is a P-MOS, 13 is an N-MOS, 14 is a gate electrode, and 15 is a wiring.
次に、第３図に示すように、第２図のＮ型シリコン基板
11に形成されたＣ−MOSをガラス基板のような絶縁体21
に接着する。さらに、第３図に示すようにＣ−MOSの活
性領域だけが残るように、Ｎ型シリコン基板11の不必要
な領域を研磨または、エッチングにより除去する。Next, as shown in FIG. 3, the N-type silicon substrate of FIG.
The C-MOS formed on 11 is an insulator 21 such as a glass substrate.
Glue to. Further, as shown in FIG. 3, unnecessary areas of the N-type silicon substrate 11 are removed by polishing or etching so that only the active areas of the C-MOS remain.
次に、第４図に示すようにホトリソグラフイによるレジ
ストパタン41を用いて、不必要なシリコンをエッチング
してＰ−MOS42,N−MOS43を島状に分離する。Next, as shown in FIG. 4, using a resist pattern 41 by photolithography, unnecessary silicon is etched to separate the P-MOS 42 and N-MOS 43 into islands.
最後に、第５図に示すように、保護膜51で素子を保護し
て、SOI−CMOSが完成する。Finally, as shown in FIG. 5, the element is protected by the protective film 51 to complete the SOI-CMOS.
以上のように本実施例によれば、標準的なシリコン基板
に形成されたＣ−MOSを、SOI−CMOSに変えることができ
る。As described above, according to this embodiment, the C-MOS formed on the standard silicon substrate can be changed to the SOI-CMOS.
なお、本実施例ではSOI−CMOSであったが、SOI−CMOS,S
OI−PMOSでもよい。Although the SOI-CMOS is used in this embodiment, the SOI-CMOS, S
It may be OI-PMOS.
発明の効果 以上のように本発明は、単結晶基板に形成されたＣ−MO
Sを絶縁基板に接着して、単結晶基板の不必要な部分を
除去してSOI−CMOSを製造することができ、その実用的
効果は大なるものがある。EFFECTS OF THE INVENTION As described above, the present invention provides a C-MO formed on a single crystal substrate.
It is possible to manufacture an SOI-CMOS by adhering S to an insulating substrate and removing an unnecessary portion of the single crystal substrate, and its practical effect is great.
第１図は従来のSOI−CMOSの模式的断面図、第２図〜第
５図は、本発明の一実施例のSOI−CMOSの製造工程を示
す断面図である。 12,42……Ｐ−MOS、13,43……Ｎ−MOS、14……ゲート電
極、15……配線、21……絶縁基板、51……保護膜。FIG. 1 is a schematic sectional view of a conventional SOI-CMOS, and FIGS. 2 to 5 are sectional views showing a manufacturing process of an SOI-CMOS of an embodiment of the present invention. 12,42 ... P-MOS, 13,43 ... N-MOS, 14 ... gate electrode, 15 ... wiring, 21 ... insulating substrate, 51 ... protective film.
Claims (1)
接着する工程と、素子領域だけが残るように結晶基板を
研磨またはエッチングにより除去する工程と、素子を島
状に分離する工程からなることを特徴とする半導体装置
の製造方法。1. A process of adhering an insulating substrate to a surface of an element formed on a crystal substrate, a step of removing the crystal substrate by polishing or etching so that only an element region remains, and a step of separating the element into islands. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59023178A JPH0691227B2 (en) | 1984-02-09 | 1984-02-09 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59023178A JPH0691227B2 (en) | 1984-02-09 | 1984-02-09 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60167364A JPS60167364A (en) | 1985-08-30 |
| JPH0691227B2 true JPH0691227B2 (en) | 1994-11-14 |
Family
ID=12103382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59023178A Expired - Lifetime JPH0691227B2 (en) | 1984-02-09 | 1984-02-09 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691227B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW214603B (en) * | 1992-05-13 | 1993-10-11 | Seiko Electron Co Ltd | Semiconductor device |
| JP3526058B2 (en) * | 1992-08-19 | 2004-05-10 | セイコーインスツルメンツ株式会社 | Semiconductor device for light valve |
| KR100632136B1 (en) * | 1996-03-12 | 2006-11-30 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | Method of manufacturing a hybrid integrated circuit |
-
1984
- 1984-02-09 JP JP59023178A patent/JPH0691227B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60167364A (en) | 1985-08-30 |
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