JPH0691525B2 - Timing playback device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an improvement of a timing recovery device in a system for performing data transmission using a two-wire type transmission line.

In a digital communication system, for example, a digital bidirectional transmission system using a two-line transmission line such as a subscriber line, the timing thereof must be properly maintained in order to properly transmit and receive the transmitted digital information. .

In the reproduction on the receiving side of such timing, it is desired that the circuit used therefor can be configured relatively easily, and it is also required that the timing reproduction is not difficult due to noise such as an echo component. To be done.

[Conventional technology]

In a conventional timing reproducing apparatus in a digital bidirectional four-wire / two-wire data transmission system using a two-wire transmission line, as shown in FIG. 5, the master side 1 (station side) and the slave side 2 (subscription) are also connected. Both parties also reproduce the required timing signal by extracting the phase information and the frequency information from the received signal.

That is, the master side 1 transmits the transmission data to the drive circuit 1a,
It inputs to the hybrid circuit 1b via ..., and transmits to the subscriber line 3 from here. On the other hand, the data received from the slave side 2 via the subscriber line 3 is input to the subtraction circuit 1d by the hybrid circuit 1b. Since the subtraction circuit 1d cancels the echo generated by the impedance mismatch between the hybrid circuit 1b and the subscriber line 3, it is an echo canceller.
Line equalizer 1f that performs subtraction with the echo cancellation signal from 1c
To enter. The signal equalized by the line equalizer 1f is the comparator 1g
"1", "0" is determined by the flip-flop 1h for synchronization
To enter.

On the other hand, the output of the comparator 1g is input to the timing reproduction circuit 1i. In the timing reproduction circuit 1i, the phase and frequency of the clock from the clock source 1j are matched with the timing component extracted from the comparator 1g and input to the flip-flop 1h.

As a result, synchronized reception data is obtained from the flip-flop 1h. The slave side 2 also performs the same operation to transmit and receive data.

[Problems to be solved by the invention]

According to this method, especially on the master side 1, the timing reproduction circuit 1i controls both the phase and the frequency, so that the scale of the required circuit becomes large. Further, since the timing reproduction is performed during the data transmission, there is a problem that the influence of the residual echo strongly appears in the timing component, which makes correct timing reproduction difficult.

[Means for solving problems]

The present invention provides a timing reproducing device that solves the above-mentioned problems, and the means includes a clock pulse output circuit in the master side transmission device 1 and outputs a reception signal via an echo canceller. In the line-to-two-wire data transmission system, the master side transmission device 1 is provided with phase information extraction means 1k for obtaining phase information from the received signal.
And a timing reproducing device for adjusting the clock phase of the clock pulse output circuit to the timing reproduced based on the phase information from the phase information extracting means 1k and fixing the clock phase of the clock pulse output circuit to the coincident phase.
1i is provided, the slave side transmission device 2 is provided with timing deviation extraction means 2k for obtaining timing deviation information of the timing signal from the received signal transmitted from the master side transmission apparatus 1, and timing reproduction based on the timing deviation information. A timing reproduction device 2i is provided, and in the master-side transmission device 1, the phase information extraction means 1k and the timing reproduction device 1i fix the clock phase of the clock pulse output circuit to the slave only during the training period. The transmission signal is transmitted only from the side transmission device 2 and is generated by the reception signal output in this transmission.

[Action]

The signal A transmitted from the master-side transmission device 1 of the four-wire / two-wire data transmission system is received by the slave-side transmission device 2, and timing deviation information is extracted from the signal and used for reproduction of the timing signal. It Then, a signal synchronized with the reproduced timing signal is transmitted to the master side. Therefore, the reception frequency component of the reception signal B received by the master-side transmission device 1 is equivalent to the frequency component on the master side.

The timing reproduction in the master side transmission apparatus 1 will be described. The output of the line equalizer as shown in FIG. As a result, the output (phase information) Ci as shown in FIG. 2 (b) is obtained from the phase information output means 1k.

In this state, the transmission signal is transmitted only from the slave side transmission device 2 for the training period from time t ₁ to time t ₂ .
It is transmitted to the master side transmission device 1. Master side transmission device 1
Then, the phase information Ci is extracted from the phase information output device 1k which is received by the master side transmission device 1 and receives the transmission signal from the master side transmission device 1. The phase information Ci is supplied to the timing signal reproduction device 1i.

Further, at the time t ₁ , the training signal is input to the timing reproducing apparatus 1i, and as shown in FIG. 2 (d), the timing signal and the phase information Ci extracted from the phase information output means 1k are input. The responding timing reproduction device 1i controls the output phase output from the master-side transmission device 1.

On the other hand, at time t ₂ , when the training signal is turned off, the phase information Ci is cut off, so the timing reproduction device 1i
Now stop the phase control. Therefore, the phase is fixed to the phase immediately before the training signal is turned off. Here, since the training signal is constantly input to the timing reproduction device 2i in the slave transmission device 2, phase control and frequency control are always performed.

As described above, in the four-wire to two-wire data transmission system using the echo canceller system, the phase control is performed in the state where there is no residual echo, so that stable timing reproduction can be performed while enjoying the reduction of the circuit scale. You can

〔Example〕

 The present invention will be described below based on examples.

FIG. 3 shows an embodiment of the present invention, which is a master in a four-wire two-wire data transmission system similar to the conventional four-wire two-wire data transmission system shown in FIG. FIG. 4 is a diagram showing an example of a timing reproduction circuit provided in the side transmission device, and FIG. 4 is a time chart thereof. In the figure, 10 and 15 are 1/2 frequency dividing circuits, 11 is a selector, 12 and 16 are AND gates, 13 is a frequency dividing circuit, 14 is a differentiating circuit, and 17 is a switch.

First, before the training is started, the output pulse of the 1/2 divider circuit 10 (φ _{1 in} the signal state of FIG. 4) determined by the signal level S (see FIG. 4 (e)) determined by the circuit state of the selector is selected. It is selected in 11 and output as φ. Then, the pulse train C ₀ (see FIG. 4 (g)) is supplied to the frequency dividing circuit 13 of a predetermined frequency division ratio, for example, 1/48, via the AND gate 12, and is then frequency-divided. .

Then, when the training is started, the switch 17 is closed by the training signal Tr, and the signal Ci is input to the differentiating circuit 14 as shown in FIG. 4 (c). And differentiator 14
Then, a signal D as shown in FIG. 3 (d) is generated. This signal switches the output level S of the 1/2 frequency divider 15 to a high level as shown in FIG. 4 (e). As a result, the selector 11 selects and outputs the pulse train φ ₀ (see FIG. 4 (a)).

On the other hand, the AND gate 16 generates a pulse I as shown in FIG. 4 (h) to generate the pulse train φ ₀ selected as described above.
Of the first pulse of the output signal from the AND gate 12 (see FIG. 4 (i))
Adjust the phase of the output pulse train from 1i. In the example shown,
The phase is delayed. Further, if the signal C ₀ is at a low level in the time range in which the signal Ci is generated and the signal D is generated, the pulse train φ ₀ is not blocked and, as a result, the phase of the output pulse train C ₀ from the timing recovery circuit 1i. Is advanced.

Timing recovery circuit 1i
When the phase adjustment of is completed, the training signal Tr is turned off, the switch 17 is opened, and the signal Ci is maintained at the low level. As a result, the output pulse train of the 1/2 frequency divider 10 determined by the selection of the selector 11 when the phase adjustment is completed is supplied to the frequency dividing circuit 13, and the output pulse train C ₀ of the desired phase is output from the frequency dividing circuit 13 to the timing recovery circuit. It is output as a 1i output pulse train, and its phase is fixed to the desired phase described above.

On the other hand, in the present invention, the switch 17 is always closed by the training signal Tr on the slave side. Therefore, since the signal Ci is constantly input, the phase and frequency are constantly controlled.

〔The invention's effect〕

As described above, according to the present invention, the circuit size on the master side can be reduced, and the phase control is performed in the state where there is no noise in the received signal, for example, the residual echo component found in the echo canceller system, so that a stable timing component Playback is possible.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is its time chart, FIG. 3 is a detailed diagram of a phase (frequency) adjusting circuit used in the present invention, and FIG. 4 is a time chart used for explaining FIG. 5 is a transmission system diagram to which the present invention is applied. In the figure, 1 is a master side, 2,2 'is an original oscillator, 1'is a slave side, 1i and 2i are timing recovery circuits, 1k is a phase information extraction circuit, 2k is a frequency information extraction circuit, and 10 and 15 are 2 minutes. 1 is a frequency dividing circuit, 11 is a selector, 12 and 16 are AND gates, 13 is a frequency dividing circuit, and 14 is a differentiating circuit.

Front page continued (72) Inventor Kazuo Murano 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) References Japanese Patent Publication Sho 56-16580 (JP, B2)

Claims (1)

[Claims] 1. A four-wire to two-wire data transmission system in which a master side transmission device (1) has a clock pulse output circuit and outputs a reception signal via an echo canceller, wherein the master side transmission device (1) A phase information extracting means (1) for obtaining phase information from the received signal.
k), and the clock phase of the clock pulse output circuit is matched with the timing reproduced based on the phase information from the phase information extraction means (1k), and the clock phase of the clock pulse output circuit is fixed to the coincident phase. A timing reproduction device (1i) is provided, and a slave side transmission device (2) is provided with timing deviation extraction means (2k) for obtaining timing deviation information of a timing signal from a received signal transmitted from the master side transmission device (1). A timing reproduction device (2i) for performing timing reproduction based on the timing deviation information, and the phase information extraction means (1k) and the timing reproduction device (1i) in the master side transmission device (1). The clock phase of the clock pulse output circuit is fixed by using the slave transmission device 2 only during the training period. Only transmits a transmission signal, the timing reproducing apparatus, characterized in that give rise by the received signal output at this transmission.