JPH0691454B2 - Output buffer circuit - Google Patents

Description

The present invention relates to an output buffer circuit provided in a semiconductor integrated circuit, and in particular, a two-stage CMOS inverter has a common output line. The present invention relates to a MOS (insulated gate type) output circuit connected to.

(Prior Art) Conventionally, an output buffer circuit of an LSI is configured as shown in FIG. 6 (a) or FIGS. 7 to 10, respectively. That is, the output buffer circuit of FIG. 6 (a) is, V _DD
P-channel transistor P ₁ whose source is connected to the power supply
The drain of the N-channel transistor N ₁ whose source is connected to the V _SS power supply (ground potential) is connected to the output line 61.
And a gate connected to each other and tangentially connected to the signal input line 62. The output buffer circuits shown in FIGS. 7 to 10 have a first CMOS inverter IV ₁ to which an input signal is directly input and a second CMOS inverter IV _{1 to which the} input signal is input via a delay circuit 70 or 80 or 90 or 100. The CMOS inverter IV ₂ is connected so that the output line 61 is common. In this case, the delay circuit 70 in FIG.
Is composed of one delay element DL, the delay circuit 80 in FIG. 8 is composed of a plurality of delay elements DL ... In series, and the delay circuit 90 in FIG. 9 is composed of a plurality of delay elements DL. The delay circuit 100 in FIG. 10 is a CMOS delay circuit in which a P-channel transistor P whose gate is connected to the V _SS potential and an N-channel transistor N whose gate is connected to the V _DD potential are connected in parallel. Circuit.

However, the output buffer circuit of FIG. 6 (a) has parasitic inductances La, Lb, Lc due to the power lines 63, 64 and the output line 61.
And a resonance circuit composed of the load capacitance C of the output line 61 causes voltage oscillations in the power supply lines 63 and 64 and the output line 61 when the output circuit is driven, causing an undershoot in the output signal shown in FIG.
Overshoot phenomenon occurs. As a result, there is a problem in that it causes fluctuations in the power supply voltage and causes malfunctions and latch-up phenomena of other elements connected to the same power supply line as the output circuit.

The output buffer circuits shown in FIGS. 7 to 10 are
Since driving by dividing the load in two stages by the first CMOS inverter IV ₁ and the second with the CMOS inverter IV _2, overshoot, but undershoot phenomenon is somewhat inhibited, the second CMOS inverter IV ₂ P-channel transistor P ₂ ,
Since a common delay circuit is connected to each gate of the N-channel transistor N ₂ , when the output of the output circuit is inverted, the P
A period occurs in which the channel transistor P ₂ and the N channel transistor N ₂ are simultaneously turned on, and a through current flows between the V _DD power supply and the V _SS power supply. Then, since the power supply voltage fluctuates due to this shoot-through current, there is a problem that malfunction of other elements is induced.

(Problems to be Solved by the Invention) As described above, according to the present invention, there is another problem in which a power supply is shared due to a power supply voltage fluctuation caused by an overshoot, an undershoot phenomenon and a shoot-through current at the time of output inversion. It was made to solve the problem of inducing malfunctions of elements, etc.It is possible to suppress overshoot, undershoot phenomenon and shoot-through current at the time of output reversal, and to induce malfunctions of other elements sharing the power supply. It is an object to provide an output buffer circuit that can be prevented.

[Object of the Invention] (Means for Solving Problems) An output buffer circuit of the present invention has first and second CMOS inverters to which an input signal of a high level potential or a low level potential is input. The first CMOS inverter has a gate connected to an input node, a source connected to a first power supply line for applying a high level potential, a drain connected to an output node, and a gate connected to the first MOS transistor. A second one connected to the input node, the source of which provides a low level potential
And a drain connected to the output node. Also,
The second CMOS inverter has a source connected to the first power supply line and a drain connected to the output node.
And a fourth MOS transistor having a source connected to the second power supply line and a drain connected to the output node.

A first delay circuit is connected between the input node and the gate of the third MOS transistor. A second delay circuit is connected between the input node and the gate of the fourth MOS transistor.

When the input signal changes from the high level potential to the low level potential, the delay amount of the first delay circuit becomes larger than the delay amount of the second delay circuit, and the input signal changes from the low level potential. When changing to a high level potential, the second
The delay amount of the delay circuit is larger than the delay amount of the first delay circuit.

(Operation) By appropriately setting the delay amounts of the first delay circuit and the second delay circuit, it is possible to suppress the overshoot and the undershoot phenomenon at the time of output reversal, and increase the rise time and the fall time. It can be set freely, and moreover, the through current of the second CMOS inverter can be suppressed. Therefore, fluctuations in the power supply potential on the first and second power supply lines can be suppressed, and there is no risk of causing malfunction of other elements sharing the power supply with the output buffer circuit. It can also contribute to lower power consumption of the integrated circuit.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

Figure 1 is an output buffer circuit provided in LSI, IV ₁
Is a P-channel MOS transistor P ₁ and an N-channel MOS transistor between the V _DD power supply end and the V _SS power supply end (ground potential).
This is a first CMOS inverter in which N ₁ is connected in series and each gate is connected in common and connected to the signal input node 10. IV ₂ is also P between the V _DD power supply end and the V _SS power supply end
A second CMOS inverter in which a channel MOS transistor P ₂ and an N channel MOS transistor N ₂ are connected in series. A first delay circuit is provided between the signal input node 10 and each gate of the P-channel transistor P ₂ and the N-channel transistor N ₂ of the second CMOS inverter IV _2.
11 and the second delay circuit 12 are connected, and the output nodes of the _two CMOS inverters IV ₁ and IV ₂ are commonly connected and connected to the signal output node 13.

A CMOS delay circuit is used for each of the two delay circuits 11 and 12, and the first delay circuit 11 has a gate.
The P-channel transistor P ₃ to which the V _SS potential is applied and the N-channel transistor N ₃ to which the V _DD potential is applied to the gate are connected in parallel, and the second delay circuit 12 is connected to the gate.
The P-channel transistor P ₄ to which the V _SS potential is applied and the N-channel transistor N ₄ to which the V _DD potential is applied to the gate are connected in parallel.

The delay time of the first delay circuit 11 is the transistors P ₃ , N ₃
And the delay time of the second delay circuit 12 depends on the ON resistance of the transistors P ₄ and N ₄ , and each delay time becomes a desired value having a predetermined magnitude relationship. Thus, the sizes of the above transistors P ₃ , N ₃ , P ₄ , and N ₄ are set. In this example, the size of the transistor P ₃ is set larger than the size of the transistor P ₄ , and the size of the transistor N ₄ is set larger than the size of the transistor N ₃ .

Next, the operation of the output buffer circuit will be described. Now
When the signal input node 10 is lowered from the V _DD potential to the V _SS potential, the P-channel transistor P ₁ is turned on in the first CMOS inverter IV ₁ , and the load is charged with a small driving force by the transistor P _1. Signal output node 13 is at V
_Starts rising from the _SS potential. At this time, in the second CMOS inverter IV ₂ , first, the N-channel transistor N ₄ of the second delay circuit 12 on the N-channel gate side is turned on, so that the N-channel transistor N ₂ is rapidly turned off. After this, the first delay circuit 11 on the P-channel gate side
By turning on the P-channel transistor P ₃ of the above, the P-channel transistor P ₂ is turned on. At this time, the P-channel transistor P _{3 of} the first delay circuit 11 is
The ON resistance increases due to the back gate bias effect as the gate potential of the P-channel transistor P ₂ decreases, so that the decrease of the gate potential becomes gradual. Further, the N-channel transistor N ₃ of the first delay circuit 11 works to finally bring the gate potential to a complete low level. As a result, the output potential of the output node 13 rises gently, and the charge / discharge current (output current) at that time can be small. That is, the input / output characteristic of the output buffer circuit and the voltage change of each part in the above operation are shown by a solid line in FIG. 2 (a), and the time change of the output current is shown by a solid line in FIG. 2 (b). As shown in. For comparison, the transfer characteristics and output current characteristics of the conventional output buffer circuit shown in FIG. 6 (a) are shown by dotted lines.

Conversely, when the input node 10 is raised from the V _SS potential to the V _DD potential, the N-channel transistor N ₁ is turned on in the first CMOS inverter IV ₁ , and this transistor
The output node 13 is discharged with a small driving force by N ₁ , and the output node 13 starts to drop from the V _DD potential. At this time, in the second CMOS inverter IV ₂ , first, the P-channel transistor P ₃ of the first delay circuit 11 on the P-channel gate side is turned on, so that the P-channel transistor P ₂ is rapidly turned off. After that, the N-channel transistor N ₄ of the second delay circuit 12 on the N-channel gate side is turned on, so that the N-channel transistor N ₂ is turned on. At this time, since the on-resistance of the N-channel transistor N ₄ of the second delay circuit 12 increases due to the back gate bias effect as the gate potential of the N-channel transistor N ₂ increases, the increase of the gate potential is gentle. It becomes something. In addition, the second delay circuit
Twelve P-channel transistors P ₄ serve to finally bring the gate potential to a completely high level. As a result, the output potential of the output node 13 rises gently, and the charge / discharge current at that time can be small.

That is, according to the output buffer circuit of the above embodiment, the overshoot of the output node and the power supply line, which occurs in proportion to the charge / discharge current of the load, as compared with the output buffer circuit of the conventional example,
The undershoot phenomenon can be suppressed. Moreover, it is possible to prevent a shoot-through current between the V _DD power supply and the V _SS power supply when the output potential is inverted, and it is possible to reduce power consumption. Moreover, since the final output current amount is the sum of the output currents of the two-stage CMOS inverter, there is no loss due to the two-stage circuit division, and a large output current can be obtained.

The present invention is not limited to the above embodiment,
Inserting delay circuits having different delay amounts on the input sides of the P-channel gate and the N-channel gate of the second CMOS inverter IV ₂ to control the gate voltages of the P-channel gate and the N-channel gate independently of each other. By means of this, various modifications can be made to suppress the rise time (Rise time) and the fall time (Fall time) of the output waveform. That is, for example, as in the output buffer circuit shown in FIG. 3, the signal input node 10 and the second CMOS inverter
Insert a P-channel transistor P ₅ whose gate is connected to the V _SS potential between IV _{2 and} the P-channel gate, and gate between the signal input node 10 and the N-channel gate of the _second CMOS inverter IV _2. An N-channel transistor N ₅ connected to the V _DD potential may be inserted. In addition, when applied to an output buffer circuit in a semi-custom IC such as a gate array, as shown in FIG. 4 or 5, a delay in which a plurality of delay elements having a unit delay time are connected in series or in parallel is used. A circuit is provided, and the rise time and fall time of the output waveform can be easily set freely by selecting the number of elements.
In the output buffer circuit of FIG. 4, P ₆ ... Is a P-channel transistor which is a delay element connected in series on the P-channel gate input side, and N ₆ ... Is connected in series on the N-channel gate input side. It is an N-channel transistor which is a delay element. Further, in the output buffer circuit of FIG. 5, P ₇ ... Are P-channel transistors which are delay elements connected in parallel with each other on the P-channel gate input side, and N ₇
Is an N-channel transistor which is a delay element connected in parallel with each other on the N-channel gate input side.

In the output buffer circuits of FIGS. 3 to 5, the same parts as those in FIG. 1 are designated by the same reference numerals.

[Effects of the Invention] As described above, according to the output buffer circuit of the present invention, it is possible to suppress the overshoot, the undershoot phenomenon, and the shoot-through current at the time of output inversion, and prevent the malfunction of other elements sharing the power supply. can do.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the output buffer circuit of the present invention, and FIGS. 2 (a) and 2 (b) show the transfer characteristics and output current characteristics of the circuit of FIG. FIGS. 3 to 5 are circuit diagrams showing other embodiments, FIG. 6 (a) and FIGS. 7 to 10 are circuit diagrams showing conventional output buffer circuits, respectively. FIG. 6 (b) is a waveform diagram showing an example of the input / output voltage of the circuit of FIG. 6 (a). 10 ... Signal input node, 11 ... first delay circuit, 12 ...
Second delay circuit, 13 ...... signal output node, IV _1, IV ₂ ......
CMOS inverter, P _{1 to} P ₇ ... P-channel transistor,
N _{1 to} N ₇ N-channel transistors.

Claims (2)

[Claims] 1. A first MOS transistor having a gate connected to an input node, a source connected to a first power supply line for applying a high level potential, and a drain connected to an output node.
And a first CMOS inverter including a second MOS transistor having a gate connected to the input node, a source connected to a second power supply line for applying a low level potential, and a drain connected to the output node. And a third MOS transistor having a source connected to the first power supply line and a drain connected to the output node, and a source connected to the second power supply line and a drain connected to the output node A second CMOS inverter composed of a fourth MOS transistor, and a P-channel transistor connected to the gate of the input node and the gate of the third MOS transistor, to which a low level potential is applied, and a gate. It is connected in parallel with an N-channel transistor to which a high level potential is applied.
A first delay circuit composed of a CMOS circuit and a P-channel transistor connected between the input node and the gate of the fourth MOS transistor and having a low level potential applied to the gate, and a high level potential applied to the gate. N-channel transistor connected in parallel
A second delay circuit composed of a CMOS circuit, wherein the size of the P-channel transistor of the first delay circuit is larger than the size of the P-channel transistor of the second delay circuit, and the second delay circuit is provided. An output buffer circuit, wherein the size of the N-channel transistor of the circuit is larger than that of the N-channel transistor of the first delay circuit. 2. When the input signal supplied to the input node changes from a high level potential to a low level potential, the delay amount of the first delay circuit is larger than the delay amount of the second delay circuit. Claim: When the input signal changes from a low level potential to a high level potential, the delay amount of the second delay circuit is larger than the delay amount of the first delay circuit. The output buffer circuit according to item 1.