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JPH0687492B2 - Thin film capacitor and manufacturing method thereof - Google Patents

Thin film capacitor and manufacturing method thereof

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Publication number
JPH0687492B2
JPH0687492B2 JP2057058A JP5705890A JPH0687492B2 JP H0687492 B2 JPH0687492 B2 JP H0687492B2 JP 2057058 A JP2057058 A JP 2057058A JP 5705890 A JP5705890 A JP 5705890A JP H0687492 B2 JPH0687492 B2 JP H0687492B2
Authority
JP
Japan
Prior art keywords
film
layer
ruthenium
silicon
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2057058A
Other languages
Japanese (ja)
Other versions
JPH03257857A (en
Inventor
正吾 松原
洋一 宮坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2057058A priority Critical patent/JPH0687492B2/en
Publication of JPH03257857A publication Critical patent/JPH03257857A/en
Publication of JPH0687492B2 publication Critical patent/JPH0687492B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は小型電子回路に用いる薄膜コンデンサに関す
る。
Description: TECHNICAL FIELD The present invention relates to a thin film capacitor used in a small electronic circuit.

(従来の技術) 集積回路技術の発達によって電子回路がますます小型化
しており、各種電子回路に必須の回路素子であるコンデ
ンサの小型化も一段と重要になっている。誘電体薄膜を
用いた薄膜コンデンサが、トランジスタ等の能動素子と
同一の基板上に形成されて利用されているが、能動素子
の小型化が急速に進む中で薄膜コンデンサの小型化は遅
れており、より一層の高集積化を阻む大きな要因となっ
てきている。これは、従来用いられている誘電体薄膜材
料かSiO2,Si3N4等のような誘電率がたかだか10以下の
材料に限られているためであり、薄膜コンデンサを小型
化する手段として誘電率の大きな誘電体薄膜を開発する
ことが必要となっている。化学式ABO3で表されるベロブ
スカイ型酸化物であるBaTiO3,SrTiO3,PbZrO3およびイ
ルメナイト型酸化物LiNbO3あるいはBi4Ti3O12等の強誘
電体に属する酸化物は、上記の単一組成並びに相互の固
溶体組成で、単結晶あるいはセラミックにおいて100以
上10000にも及ぶ誘電率を有することが知られており、
セラミック・コンデンサに広く用いられている。これら
材料の薄膜化は上述の薄膜コンデンサの小型化に極めて
有効であり、かなり以前から研究が行われている。それ
らの中で比較的良好な特性が得られている例としては、
プロシーディング・オブ・アイ・イー・イー・イー(Pr
oceedings of the IEEE)第59巻10号1440−1447頁の所
載の論文があり、スパッタリングにより成膜および熱処
理を行ったBaTiO3薄膜で16(室温で作成)から1900(12
00℃で熱処理)の誘電率が得られている。
(Prior Art) With the development of integrated circuit technology, electronic circuits are becoming smaller and smaller, and miniaturization of capacitors, which are circuit elements essential for various electronic circuits, is becoming more important. Thin film capacitors using dielectric thin films are used by being formed on the same substrate as active elements such as transistors, but miniaturization of thin film capacitors has been delayed due to rapid miniaturization of active elements. , Has become a major factor preventing further high integration. This is because the dielectric thin film material or SiO 2 which has been used conventionally, Si 3 N 4 dielectric constant such as is limited to at most 10 or less of the material, a dielectric as a means to reduce the size of the thin film capacitor It is necessary to develop a dielectric thin film with a high rate. BaTiO 3, SrTiO 3, PbZrO 3 and ilmenite type oxides LiNbO 3 or Bi 4 Ti 3 O strong oxide belonging to the dielectric, such as 12, which is a Berobusukai type oxide represented by the chemical formula ABO 3, the above-described single It is known that the composition and mutual solid solution composition have a dielectric constant of 100 or more and 10000 in a single crystal or ceramic,
Widely used in ceramic capacitors. Thinning of these materials is extremely effective for miniaturization of the above-mentioned thin film capacitor, and research has been conducted for quite some time. Among these, as an example where relatively good characteristics are obtained,
Proceeding of Eye Eee (Pr
There is a paper published in Volume 59, No. 10, pp. 1440-1447, which uses a BaTiO 3 thin film deposited by sputtering and heat-treated from 16 (prepared at room temperature) to 1900 (12
A dielectric constant of (heat treatment at 00 ° C) is obtained.

現在の高集積回路に広く用いられている電極材料は多結
晶シリコンあるいはシリコン基板自体の一部に不純物を
高濃度にドーピングした低抵抗シリコン層である。以下
これらを総してシリコン電極と呼ぶ。シリコン電極は微
細加工技術が確立されており、すでに広く用いられてい
るため、シリコン電極上に良好な高誘電率薄膜が作製で
きれば、集積回路用コンデンサへの利用が可能となる。
しかしながら従来技術では例えばIBM・ジャーナル・オ
ブ・リサーチ・アンド・ディベロップメント(IBM Jour
nal of Research and Development)1969年11月号686−
695頁に所載のSrTiO3膜に関する論文が、ジャーナル・
オブ・バキューム・サイエンス・アンド・テクノロジー
(Journal of Vacuum Science and Technology)第16巻
2号315−318頁に所載のBaTiO3に関する論文が報告され
ている。
The electrode material widely used in the present highly integrated circuits is polycrystalline silicon or a low resistance silicon layer in which a part of the silicon substrate itself is highly doped with impurities. Hereinafter, these are collectively called a silicon electrode. Since a fine processing technology has been established for silicon electrodes and is already widely used, if a good high-dielectric-constant thin film can be formed on silicon electrodes, it can be used for capacitors for integrated circuits.
However, in the prior art, for example, IBM Journal of Research and Development (IBM Jour
nal of Research and Development) November 1969 686−
A paper on SrTiO 3 film on page 695 is published in
A paper on BaTiO 3 is reported in Journal of Vacuum Science and Technology, Vol. 16, No. 2, pp. 315-318.

(発明が解決しようとする課題) 上記のように高誘電率を得るためには高い成膜温度を必
要とするが、従来シリコン電極上に作製されているBaTi
O3等の誘電体薄膜は約100Åの二酸化シリコン(SiO2
に等価な層が界面に形成されていまうと報告されてい
る。この界面層は誘電率が低い層であるため、結果とし
てシリコン上に形成した高誘電率薄膜の実効的な誘電率
は大きく低下してしまい。高誘電率材料を用いる利点が
ほとんど損なわれていた。
(Problems to be Solved by the Invention) As described above, a high film formation temperature is required to obtain a high dielectric constant, but BaTi that is conventionally formed on a silicon electrode
Dielectric thin film such as O 3 is about 100 Å silicon dioxide (SiO 2 )
It is reported that a layer equivalent to is formed at the interface. Since this interface layer is a layer having a low dielectric constant, as a result, the effective dielectric constant of the high dielectric constant thin film formed on silicon is greatly reduced. Most of the benefits of using high dielectric constant materials have been compromised.

(課題を解決するための手段) 本発明はシリコン電極上に導電層、誘電体、上部電極が
順次形成された構造の薄膜コンデンサにおいて、導電層
がシリコン上に形成される第1層とその上に形成される
第2層とから構成され、第1層がルテニウム、ルテニウ
ムシリサイド、酸化ルテニウムから選ばれる少なくとも
1種以上の材料であり、第2層が白金、パラヂウム、ロ
ジウムの高融点貴金属から選ばれる少なくとも1種類以
上の材料であることを特徴とする薄膜コンデンサと所定
温度で第1導電層を酸化する工程を備えた製造方法であ
る。
(Means for Solving the Problems) The present invention relates to a thin film capacitor having a structure in which a conductive layer, a dielectric, and an upper electrode are sequentially formed on a silicon electrode, and a conductive layer is formed on the first layer and the first layer. And a second layer formed on the first layer, wherein the first layer is at least one material selected from ruthenium, ruthenium silicide and ruthenium oxide, and the second layer is selected from high melting point noble metals such as platinum, palladium and rhodium. And a step of oxidizing the first conductive layer at a predetermined temperature.

(実施例1) 以下、本発明の実施例について図面を参照して説明す
る。
Example 1 Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図は本実施例の薄膜コンデンサの構造図である。単
結晶シリコン1の表面の一部にリンを高濃度にドーピン
グして低抵抗層2が形成され、その上に層間絶縁膜とし
て酸化シリコン膜3が形成されている。酸化シリコン膜
の一部は、低抵抗層を通じて下部電極を引き出すための
コンタクトホールが2箇所形成されており、一方のコン
タクトホールは多結晶シリコン膜4で埋められ、もう一
方のコンタクトホールはAl膜5で埋められている。従っ
て、Al膜5は下部電極の端子となる。下部電極膜4はコ
ンタクトホールを埋めると共にその一部が酸化シリコン
膜上へ形成されてもよい。下部電極膜4上には導電層第
1層6、第2層7が形成され、その上にBaTiO3膜8が形
成され、その上には上部電極としてAl9が形成されてい
る。
FIG. 1 is a structural diagram of the thin film capacitor of this embodiment. A low resistance layer 2 is formed by heavily doping phosphorus on a part of the surface of the single crystal silicon 1, and a silicon oxide film 3 is formed thereon as an interlayer insulating film. In a part of the silicon oxide film, two contact holes for drawing out the lower electrode through the low resistance layer are formed, one contact hole is filled with the polycrystalline silicon film 4, and the other contact hole is an Al film. Filled with 5. Therefore, the Al film 5 becomes a terminal of the lower electrode. The lower electrode film 4 may fill the contact hole and be partially formed on the silicon oxide film. Conductive layer first layers 6 and second layers 7 are formed on the lower electrode film 4, a BaTiO 3 film 8 is formed thereon, and Al 9 is formed thereon as an upper electrode.

導電層は直流マグネトロンスパッタ法で第1層の酸化ル
テニウム、第2層の白金を順に作製した。Arガス雰囲
気、4×10-3Torr、基板温度100℃で行い、白金、酸化
ルテニウムの膜厚はいずれも1500Åとした。酸化ルテニ
ウムの成膜にはRuO2組成の焼結体ターゲットを用いた。
BaTiO3膜は化学量論組成の粉末ターゲットを用い、高周
波マグネトロンスパッタ法で3000Åの膜厚のものを作製
した。Ar−O2混合ガス中、1×10-2Torr、基板温度600
℃でスパッタ成膜した。上部電極には5000ÅのAlを直流
スパッタ法により成膜した。本コンデンサの有効面積は
250μmである。つぎに導電層として本方法の白金、
酸化ルテニウムを用いた場合、高融点貴金属である白金
膜だけを用いた場合、更に導電層を形成しない場合のBa
TiO3膜の特性の違いについて述べる。第2図において
(a)は本方法の白金と酸化ルテニウムの多層膜を用い
た場合のBaTiO3膜の、(b)は膜厚3000Åの白金膜を用
いた場合の、(c)は膜厚3000Åでシート抵抗100Ω/c
m2の多結晶シリコン膜を用いた場合のBaTiO3膜の膜厚に
よる誘電率の変化を調べたものである。本方法の多層膜
を用いた場合のBaTiO3膜の誘電率はその膜厚に依存せず
一定であるのに対し、白金膜あるいは多結晶シリコン膜
を用いた場合には誘電体膜の膜厚が小さくなるにつれて
誘電率が著しく減少してしまう。
As the conductive layer, ruthenium oxide as the first layer and platinum as the second layer were sequentially manufactured by the DC magnetron sputtering method. Ar gas atmosphere, 4 × 10 −3 Torr, substrate temperature 100 ° C., and the film thickness of platinum and ruthenium oxide were 1500 Å. A RuO 2 composition sintered body target was used for the ruthenium oxide film formation.
The BaTiO 3 film was prepared by a high-frequency magnetron sputtering method with a stoichiometric powder target to a film thickness of 3000 Å. 1 × 10 -2 Torr in Ar-O 2 mixed gas, substrate temperature 600
The film was formed by sputtering at ℃. 5000 Å Al was deposited on the upper electrode by DC sputtering. The effective area of this capacitor is
It is 250 μm 2 . Next, platinum of this method as a conductive layer,
When using ruthenium oxide, when using only a platinum film which is a high melting point noble metal, and when not forming a conductive layer, Ba
The difference in the characteristics of the TiO 3 film will be described. In FIG. 2, (a) is a BaTiO 3 film when a platinum and ruthenium oxide multilayer film of this method is used, (b) is a platinum film having a film thickness of 3000 Å, and (c) is a film thickness. Sheet resistance 100Ω / c at 3000Å
This is an examination of changes in the dielectric constant depending on the film thickness of the BaTiO 3 film when a polycrystalline silicon film of m 2 is used. When the multilayer film of this method is used, the dielectric constant of the BaTiO 3 film is constant irrespective of its film thickness, whereas when the platinum film or polycrystalline silicon film is used, the film thickness of the dielectric film is As becomes smaller, the permittivity decreases significantly.

多結晶シリコン膜での誘電率の低下は従来報告されてい
る通り、誘電体と電極の界面におけるシリコンの酸化層
の形成、あるいは誘電体膜成長初期の低誘電率層の形成
が原因である。(b)の白金膜での場合には誘電体膜成
膜後のX線回折により白金のシリサイド化が確認され
た。これは600℃での誘電体の成膜時にシリコンが白金
と反応し、シリサイド化合物を形成しながら最表面に達
したことを意味している。従って、電極の最表面にはシ
リコンが存在し、多結晶シリコン膜の場合と同様な状態
で低誘電率層を形成したものと考えられる。これに対し
て、同じくX線回折によれば、白金と酸化ルテニウムの
多層膜では誘電体の成膜後も白金がシリサイド化せず元
の状態で存在している。即ち、シリコンは酸化ルテニウ
ム層でその拡散が抑えられて白金層に達しておらず、前
述のようなシリコンの酸化による低誘電率層の形成が起
こらなかったと考えられる。
As previously reported, the decrease in the dielectric constant of the polycrystalline silicon film is due to the formation of a silicon oxide layer at the interface between the dielectric and the electrode or the formation of a low dielectric constant layer at the initial stage of the dielectric film growth. In the case of the platinum film of (b), silicidation of platinum was confirmed by X-ray diffraction after forming the dielectric film. This means that silicon reacts with platinum at the time of forming a dielectric film at 600 ° C. and reaches the outermost surface while forming a silicide compound. Therefore, it is considered that silicon exists on the outermost surface of the electrode and the low dielectric constant layer is formed in the same state as in the case of the polycrystalline silicon film. On the other hand, according to the same X-ray diffraction, in the multi-layer film of platinum and ruthenium oxide, platinum remains in the original state without being silicidized even after the dielectric film is formed. That is, it is considered that the diffusion of silicon was suppressed by the ruthenium oxide layer and did not reach the platinum layer, and the formation of the low dielectric constant layer due to the oxidation of silicon as described above did not occur.

白金と酸化ルテニウムとの密着性を向上させることを目
的に、一般に行われているように白金と酸化ルテニウム
との間にチタンなどの密着層を挿入した構造としても本
発明の効果が損なわれることはない。また、白金の代わ
りにパラヂウム、あるいはロヂウムの高融点貴金属を用
いても同様な結果が得られることを確認した。
For the purpose of improving the adhesion between platinum and ruthenium oxide, the effect of the present invention is impaired even if the structure is such that an adhesion layer such as titanium is inserted between platinum and ruthenium oxide as is generally done. There is no. It was also confirmed that similar results could be obtained by using a high melting point noble metal such as palladium or rhodium instead of platinum.

(実施例2) 実施例1の薄膜コンデンサにおいて、導電層の第1層に
ルテニウムシリサイドを用い、BaTiO3膜の誘電率の膜厚
依存性を調べた。ルテニウムシリサイドはRu/Si=1/1組
成の焼結体ターゲットを用いて直流スパッタ法で成膜
し、膜厚1500Åとした。
Example 2 In the thin film capacitor of Example 1, ruthenium silicide was used for the first conductive layer, and the film thickness dependence of the dielectric constant of the BaTiO 3 film was examined. Ruthenium silicide was deposited by direct current sputtering using a sintered target of Ru / Si = 1/1 composition to a film thickness of 1500Å.

実施例1と同様にBaTiO3膜の誘電率はその膜厚に依存せ
ず本来の値約220が得られた。但し、誘電体膜成膜後の
X線回折によれば、酸化ルテニウムの場合とは異なり、
白金がシリサイド化していることが確認された。このこ
とから、ルテニウムシリサイドは少なくとも酸化ルテニ
ウムのようにシリコンの拡散を抑止する効果はなくシリ
コンは電極の最表面まで達するが、その上に形成された
誘電体膜の膜質は実施例1(b)の白金膜上に形成され
た膜とは異なると考えられる。
Similar to Example 1, the dielectric constant of the BaTiO 3 film did not depend on the film thickness, and the original value of about 220 was obtained. However, according to X-ray diffraction after forming the dielectric film, unlike the case of ruthenium oxide,
It was confirmed that platinum was silicided. From this, ruthenium silicide does not have the effect of suppressing diffusion of silicon at least like ruthenium oxide, and silicon reaches the outermost surface of the electrode. It is considered that the film is different from the film formed on the platinum film.

本実施例でルテニウムシリサイドの代わりにルテニウム
を用いた場合にも同様な結果が得られることを確認し
た。
In this example, it was confirmed that similar results were obtained when ruthenium was used instead of ruthenium silicide.

(実施例3) 実施例1の薄膜コンデンサにおいて、導電層の第2層に
白金、パラヂウム、ロヂウムの高融点貴金属からなる合
金膜、あるいは多層膜を用いた。表1に本実施例で用い
た材料をまとめた。
(Example 3) In the thin film capacitor of Example 1, an alloy film made of a high melting point noble metal of platinum, palladium, or rhodium, or a multilayer film was used for the second layer of the conductive layer. Table 1 summarizes the materials used in this example.

本実施例においても実施例1と同様に、BaTiO3膜の誘電
率はその膜厚に依存せず約220の値が得られ、界面での
低誘電率層の形成を防止できた。また、X線回折によっ
て、第2層の高融点貴金属の合金あるいは多層膜がシリ
サイド化していないことを確認した。
Also in this example, as in Example 1, the dielectric constant of the BaTiO 3 film did not depend on the film thickness, and a value of about 220 was obtained, and formation of the low dielectric constant layer at the interface could be prevented. In addition, it was confirmed by X-ray diffraction that the second melting point noble metal alloy or the multilayer film was not silicided.

(実施例4) 実施例2と同様に導電層の第1層にルテニウムシリサイ
ドを直流スパッタ法で1500Å成膜した後、500℃、酸素
ガス雰囲気で熱処理してルテニウムシリサイド膜を酸化
し、しかる後に、実施例1と同様に白金、BaTiO3、Alを
形成した。
(Example 4) As in Example 2, after ruthenium silicide was deposited on the first layer of the conductive layer by 1500 Å by the DC sputtering method, the ruthenium silicide film was oxidized by heat treatment at 500 ° C in an oxygen gas atmosphere. Then, platinum, BaTiO 3 , and Al were formed in the same manner as in Example 1.

実施例1、2と同様にBaTiO3膜の誘電率はその膜厚に依
存せず約220の値が得られた。誘電体成膜後のX線回折
によれば白金はシリサイド化しておらず、その点で実施
例2の結果と異なる。即ち、ルテニウムシリサイドを酸
化した膜はシリコンを多量に含有するにもかかわらず、
白金へのシリコンの拡散を抑止している。ルテニウムシ
リサイド膜を酸化する温度としては400℃以上が必要で
ある。ルテニウムシリサイド膜のシート抵抗は酸化温度
に依存し、400℃から600℃までは約10Ω/□であるが、
630℃から増加し始め、700℃より高温で酸化すると著し
く増大して100Ω/□以上となる。薄膜コンデンサにお
いて電極の抵抗は小さいほどよく、従って、ルテニウム
シリサイドの酸化処理温度は400℃以上、700℃以下がよ
い。
As in Examples 1 and 2, the BaTiO 3 film had a dielectric constant of about 220 regardless of the film thickness. According to X-ray diffraction after forming the dielectric film, platinum is not silicidized, which is different from the result of Example 2. That is, although the film obtained by oxidizing ruthenium silicide contains a large amount of silicon,
It suppresses the diffusion of silicon into platinum. The temperature for oxidizing the ruthenium silicide film needs to be 400 ° C. or higher. The sheet resistance of the ruthenium silicide film depends on the oxidation temperature and is about 10Ω / □ from 400 ℃ to 600 ℃.
It starts to increase from 630 ℃, and when oxidized at temperatures higher than 700 ℃, it increases remarkably and reaches 100Ω / □ or more. In a thin film capacitor, the smaller the resistance of the electrode, the better. Therefore, the oxidation treatment temperature of ruthenium silicide is preferably 400 ° C or higher and 700 ° C or lower.

本実施例において作製されたルテニウム−シリコン酸化
物膜は、実施例1で作製された酸化ルテニウム膜よりも
シリコン電極との密着性に優れていることが特徴であ
る。例えば本実施例と同様にシリコン基板上に膜厚1500
Åのルテニウム−シリコンから成る酸化物膜を形成して
その上にBaTiO3膜2μmをスパッタ成膜しても膜の剥離
は起こらなかったが、実施例1のようにシリコン電極上
に膜厚1500Åスパッタ成膜した酸化ルテニウム膜の上に
3500Å以上のBaTiO3を成膜すると、酸化ルテニウムとシ
リコン電極の間で全面剥離を生じた。
The ruthenium-silicon oxide film produced in this example is characterized in that it has better adhesion to the silicon electrode than the ruthenium oxide film produced in Example 1. For example, a film thickness of 1500 is formed on a silicon substrate as in the present embodiment.
Even if an oxide film made of ruthenium-silicon of Å was formed and a BaTiO 3 film of 2 μm was sputter-deposited on the oxide film, the film was not peeled off, but the film thickness was 1500 Å on the silicon electrode as in Example 1. On top of sputter deposited ruthenium oxide film
When BaTiO 3 with a film thickness of 3500Å or more was deposited, the entire surface was peeled between the ruthenium oxide and the silicon electrode.

また、本実施例のルテニウムシリサイド膜の代わりにル
テニウム膜を用いても同様に密着性向上の効果があっ
た。
Further, even if a ruthenium film was used instead of the ruthenium silicide film of this example, the effect of improving the adhesion was similarly obtained.

以上の実施例はBaTiO3膜について説明したが、この他に
SrTiO3,PbTiO3,PbZrO3,LiNbO3,Bi3Ti4O12及び固溶
体(Ba,Sr)TiO3,(Ba,Pb)TiO3,Pb(Zr,Ti)O3につい
ても同様の作製、評価を行った結果、膜厚によらず誘電
体膜本来の誘電率が得られた。
In the above examples, the BaTiO 3 film was explained.
SrTiO 3, PbTiO 3, PbZrO 3 , LiNbO 3, Bi 3 Ti 4 O 12 and solid solutions (Ba, Sr) TiO 3, (Ba, Pb) TiO 3, Pb (Zr, Ti) same manufacturing also O 3, As a result of the evaluation, the original dielectric constant of the dielectric film was obtained regardless of the film thickness.

(発明の効果) 本発明は以上説明したように、シリコン電極上に形成さ
れた薄膜コンデンサにおいてシリコン電極と誘電体膜の
間に酸化ルテニウム、ルテニウムシリサイド、もしくは
ルテニウムからなる膜と高融点貴金属膜からなる導電層
を形成することにより、低誘電率層の形成を防ぎ、高誘
電率の薄膜コンデンサを提供することができる。
(Effect of the invention) As described above, according to the present invention, in a thin film capacitor formed on a silicon electrode, a film made of ruthenium oxide, ruthenium silicide, or ruthenium and a high melting point noble metal film are provided between the silicon electrode and the dielectric film. By forming such a conductive layer, it is possible to prevent the formation of the low dielectric constant layer and provide a high dielectric constant thin film capacitor.

【図面の簡単な説明】 第1図は本発明における実施例1の薄膜コンデンサの断
側面図、第2図はBaTiO3膜の膜厚と誘電率の関係を示す
図。 図において、1…単結晶シリコン基板、2…単結晶シリ
コンの低抵抗層、3…酸化シリコン、4…多結晶シリコ
ン膜、5,9…Al,6…導電層第1層、7…導電層第2層、
8…BaTiO3膜。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional side view of a thin film capacitor of Example 1 of the present invention, and FIG. 2 is a diagram showing a relationship between a film thickness of a BaTiO 3 film and a dielectric constant. In the figure, 1 ... Single crystal silicon substrate, 2 ... Low resistance layer of single crystal silicon, 3 ... Silicon oxide, 4 ... Polycrystalline silicon film, 5, 9 ... Al, 6 ... Conductive layer first layer, 7 ... Conductive layer The second layer,
8 ... BaTiO 3 film.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】シリコン電極上に導電層、誘電体、上部電
極が順次形成された構造の薄膜コンデンサにおいて、導
電層がシリコン電極上に形成される第1層とその上に形
成される第2層とから構成され、第1層がルテニウム、
ルテニウムシリサイド、酸化ルテニウムから選ばれる少
なくとも1種以上の材料であり、第2層が白金、パラヂ
ウム、ロヂウムの高融点貴金属から選ばれる少なくとも
1種以上の材料であることを特徴とする薄膜コンデン
サ。
1. In a thin film capacitor having a structure in which a conductive layer, a dielectric and an upper electrode are sequentially formed on a silicon electrode, the conductive layer is a first layer formed on the silicon electrode and a second layer formed thereon. And a first layer of ruthenium,
A thin film capacitor comprising at least one material selected from ruthenium silicide and ruthenium oxide, and the second layer comprising at least one material selected from high melting point noble metals such as platinum, palladium and rhodium.
【請求項2】シリコン電極上に導電層の第1層にルテニ
ウムあるいはルテニウムシリサイドを形成した後400℃
以上700℃以下の酸素雰囲気で熱処理して導電層第1層
の一部または全体を酸化し、しかる後に導電層第2層に
白金、パラヂウム、ロヂウムの高融点貴金属から選ばれ
る少なくとも1種以上の材料を形成し、その上に誘電
体、上部電極を順次形成することを特徴とする薄膜コン
デンサの製造方法。
2. After forming ruthenium or ruthenium silicide on the first layer of the conductive layer on the silicon electrode, 400 ° C.
The conductive layer first layer is partially or wholly oxidized by heat treatment in an oxygen atmosphere of 700 ° C. or lower, and then the conductive layer second layer is made of at least one or more refractory precious metals such as platinum, palladium, and rhodium. A method of manufacturing a thin film capacitor, which comprises forming a material, and then sequentially forming a dielectric and an upper electrode thereon.
JP2057058A 1990-03-07 1990-03-07 Thin film capacitor and manufacturing method thereof Expired - Fee Related JPH0687492B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2057058A JPH0687492B2 (en) 1990-03-07 1990-03-07 Thin film capacitor and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2057058A JPH0687492B2 (en) 1990-03-07 1990-03-07 Thin film capacitor and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH03257857A JPH03257857A (en) 1991-11-18
JPH0687492B2 true JPH0687492B2 (en) 1994-11-02

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Country Link
JP (1) JPH0687492B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685193A (en) * 1992-09-07 1994-03-25 Nec Corp Semiconductor device
US6358810B1 (en) * 1998-07-28 2002-03-19 Applied Materials, Inc. Method for superior step coverage and interface control for high K dielectric capacitors and related electrodes
US6197628B1 (en) * 1998-08-27 2001-03-06 Micron Technology, Inc. Ruthenium silicide diffusion barrier layers and methods of forming same
US6727140B2 (en) * 2001-07-11 2004-04-27 Micron Technology, Inc. Capacitor with high dielectric constant materials and method of making
JP7056290B2 (en) * 2018-03-23 2022-04-19 Tdk株式会社 Thin film capacitors and methods for manufacturing thin film capacitors
CN111968857B (en) * 2020-08-28 2022-02-08 电子科技大学 Method for realizing dielectric film double-layer compounding by improving film adhesive force through chemical method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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