JPH0686147A - Imaging device - Google Patents

Abstract

PURPOSE:To provide the image pickup device capable of high-precision automatic adjustment such as automatic exposure. CONSTITUTION:A frame signal of a detection frame generated by frame data set to registers 3 to 6 is obtained from a NAND circuit 15, and this frame signal is used to extract a video signal in the detection frame from a mask circuit 16, and this video signal is integrated by an adder 17 and a register 18, and the automatic adjustment is performed by this integrated output. In this device, plural detection frames are set in the V period based on an interrupt signal IRQ obtained by applying frame end signals WEV and WEH from flip flops 13 and 14 to an AND circuit 20. Thus, the control time is shortened, and the follow-up capacity is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus such as a video camera which automatically makes various adjustments based on a signal obtained in a detection frame set on an image pickup screen.

[0002]

2. Description of the Related Art Recent video cameras can automatically adjust various values such as aperture value, white balance, focal length, etc., which have been manually adjusted until now, so that anyone can use them easily. I am trying. In order to perform these various automatic adjustments, several detection frames having sizes according to the adjustment items are set at predetermined positions on the imaging screen, and the signals in each detection frame from the captured video signal are set. Is detected, and each adjustment is performed using a signal obtained by integrating each detection signal.

FIG. 4 shows a conventional circuit configuration for setting the detection frame and integrating the signals in the detection frame. In this example, the case where AE (automatic exposure) control or AWB (automatic white balance) control is performed is shown.

In FIG. 4, reference numeral 1 is a V counter for counting in the vertical direction by counting the horizontal synchronizing signal HD for each vertical synchronizing signal VD, and 2 is a horizontal counter for counting the system clock CLK for each signal HD. It is an H counter that performs a directional counting operation.

Reference numeral 3 is a vertical position register for writing the vertical start position of the detection frame, 4 is a vertical width register for writing the vertical width of the detection frame, and 5 is a horizontal position register for writing the horizontal start position of the detection frame. Reference numeral 6 is a horizontal width register for writing the horizontal width of the detection frame.

Reference numeral 7 is an adder for adding the vertical start position of the register 3 and the vertical width of the register 4 to obtain the vertical end position of the detection frame, and 8 is the horizontal start position of the register 5 and the horizontal width of the register 6. Is an adder for obtaining the horizontal end position of the detection frame.

Reference numeral 9 is a comparator for detecting a match between the signal VBUS indicating the count value of the V counter 1 and the vertical start position of the register 3, and 10 is a comparator for detecting a match between the signal VBUS and the added value of the adder 7. 11 is a comparator for detecting a match between the signal HBUS indicating the count value of the H counter 2 and the horizontal start position of the register 5, and 12 is a comparator for detecting a match between the signal HBUS and the added value of the adder 8. Is.

13 is set by the coincidence output of the comparator 9,
Flip-flop reset by coincidence output of comparator 10, 14 is set by coincidence output of comparator 11, flip-flop reset by coincidence output of comparator 12, 1
A NAND circuit 5 obtains a frame signal for forming a detection frame by the outputs of the flip-flops 13 and 14.

Reference numeral 16 is a mask circuit for extracting a signal within the detection frame from the picked-up video signal Data by using the frame signal of the NAND circuit 15. Reference numeral 17 is an integrating adder for adding the output of the mask circuit 16 and the integrated output. Is a register for integrating the output of the adder 17, 19 is a microcomputer for setting frame data to the registers 3, 4, 5 and 6, and register 1 for each vertical scanning period based on the signal VD.
Take the integrated output from 8.

Next, the operation of the above configuration will be described.

In FIG. 4, the system clock CLK,
When the horizontal synchronizing signal HD and the vertical synchronizing signal VD are input to the V counter 1 and the H counter 2, respectively, the V counter 1 outputs the signal VBUS of the upper 6 bits of 9 bits. Further, the H counter 2 outputs the signal HBUS of the upper 6 bits of the 10 bits. The microcomputer 19 previously sets the registers 3 to 6 to the start position and the vertical position of the detection frame.
Frame data such as horizontal width is written in advance. The adders 7 and 8 obtain the end position of the detection frame by adding the value of each vertical / horizontal width to the value of each vertical / horizontal start position.

Next, the start position and end position of the detection frame and the signals HBUS and VBUS are compared by the comparators 9 to 12, and if they match, the coincidence output is flip-flops 13 and 1.
Enter in 4. The output signals of the flip-flops 13 and 14 rise when the start positions match, and the output signals fall when the end positions match. The NAND circuit 15 combines vertical and horizontal to create a frame signal. In addition, the video signal Data
Is input to the mask circuit 16, the video signal is output as it is in the detection frame by the frame signal, and a zero value is output outside the detection frame. The signal output from the mask circuit 16 is integrated by an integrating circuit composed of an adder 17 and a register 18, and then applied to a microcomputer 19 to be used as information for AE or AWB control.

FIG. 5 is a flow chart showing the operation of the microcomputer 19. In FIG. 5, step S
At 51, frame data is set in the registers 3, 4, 5, and 6. In step S52, the arrival of the signal VD is waited for. When the signal VD is detected, the register 18
Capture the integrated output of.

FIG. 6 shows an example of the data indicating the positions of the detection frames in one screen, which are written in the registers 3, 4, 5 and 6, and are written in a regular pattern such as a vertical column as shown in the figure.

[0015]

However, in the conventional circuit configured as described above, a large amount of information is taken out, and it is necessary to collect the data for one screen once in one vertical scanning period. However, it takes a long time, so that there is a problem that it takes too much time for the control to follow, or it cannot follow a fast moving object. In addition, the information to be extracted may be shifted in time depending on the shape or pattern of the subject, which may make it impossible to perform accurate control.

The present invention solves the above problems, and an object of the present invention is to obtain an image pickup apparatus capable of performing automatic adjustment accurately and stably.

[0017]

In the first invention,
A plurality of detection frames for one automatic adjustment item are set in one vertical scanning period.

In the second invention, a plurality of detection frames are set in one vertical scanning period, and the positions of the detection frames are arranged irregularly at that time.

[0019]

According to the first aspect of the present invention, by setting a plurality of detection frames in one vertical scanning period, the time for collecting data for one screen is significantly shortened, and the control time is shortened.
It becomes possible to perform control with good followability.

According to the second invention, by setting a plurality of detection frames in one vertical scanning period and arranging the positions of the detection frames irregularly, the information to be taken in is averaged, and the regularity of It is less likely to be affected by a subject with a certain pattern.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, the same parts as those in FIG.

In FIG. 1, 20 is an AND circuit, which is a frame end signal WEV, WE from the flip-flops 13, 14.
H is input and the interrupt signal IRQ is output to the microcomputer 19.

Next, the operation of the first invention having the above-mentioned structure will be described.

As described with reference to FIG. 4, in the flip-flops 13 and 14, the output signal rises when the frame positions match and the output signal falls when the frame end positions match. Also,
At the same time, the frame end signals WEV and WEH are output at the frame end position. The AND circuit 20 includes flip-flops 13 and 14
AND of the above signals WEV and WEH obtained from
The interrupt signal IRQ is output to the microcomputer 19. As shown in FIG.
After the interrupt signal IRQ is input in step S22, the integrated output is read from the register 18 in step S23. Next, in step S21, the operation of writing the next frame data into the registers 3 to 6 is performed.

According to the above, a plurality of detection frames are created in one vertical scanning period according to the contents of the frame data.

Next, the operation of the second invention will be described.

In this embodiment, when setting the position of the frame based on the frame data in step S21 of FIG. 2, the data is set so that a plurality of detection frames are irregularly arranged as shown in FIG. I try to write it. Therefore, the plurality of detection frames obtained in one vertical scanning period are irregularly arranged on the image pickup screen.

[0028]

As described above, according to the present invention, a plurality of detection frames are set in one vertical scanning period by setting the next detection frame after the end of one detection frame. Since this is done, the time for collecting data for one screen is significantly shortened, the control time is short, and control with good followability can be performed. Further, since the positions of the respective detection frames are arranged irregularly, it is possible to obtain an effect such as automatic adjustment of the camera which is less likely to be affected by the subject having a regular pattern.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the microcomputer shown in FIG.

FIG. 3 is a configuration diagram showing a state of a position of a detection frame according to the present invention.

FIG. 4 is a block diagram showing a conventional imaging device.

5 is a flowchart showing the operation of the microcomputer shown in FIG.

FIG. 6 is a configuration diagram showing a state of a position of a conventional detection frame.

[Explanation of symbols]

 1 V counter 2 H counter 3 Vertical position register 4 Vertical width register 5 Horizontal position register 6 Horizontal width register 13, 14 Flip-flop 16 NAND circuit 17 Adder 18 register 19 Microcomputer 20 AND circuit

Claims (2)

[Claims] 1. A detection frame having a size corresponding to an item of automatic adjustment is set at a predetermined position on an image pickup screen, and a signal within the detection frame among the picked-up video signals is integrated, and an integrated output thereof is provided. An image pickup apparatus, wherein a signal is used as information for automatic adjustment, wherein a plurality of detection frames for the same automatic adjustment item are set within one vertical scanning period. 2. The image pickup apparatus according to claim 1, wherein the plurality of detection frames are irregularly arranged on the image pickup screen.