JPH0683185B2 - Successive decoding device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a sequential decoding device, and more particularly to a sequential decoding device that performs error correction decoding on a convolutional code transmitted on a transmission path of an orthogonal modulation method.

[Conventional technology]

In order to detect and correct a transmission error of data, the data is divided into several information symbols, convolutionally coded by an error correction encoder to form a code symbol, and the transmitted code symbol is decoded by an error correction decoder (hereinafter Sequential decoding is performed using the Fano algorithm.

Such an error correction encoder comprises a state holding circuit and a function generating circuit. The state holding circuit is composed of, for example, a shift register, holds an internal state, and changes the internal state by inputting an information symbol. The function generator inputs internal states and generates code symbols.

The received signal (hard decision thereof) received by the decoder corresponding to one code symbol does not necessarily match the sent code symbol due to a transmission error.

If the decoder proceeds decoding in code symbol units,
It has a circuit (hereinafter referred to as encoder duplication) having the same function as the corresponding error correction encoder, and inputs all possible information symbols to the encoder duplication each time a received signal corresponding to one code symbol is received. Each of the code symbols output by the encoder replica at that time is compared with the received signal received, and the information symbol giving the code symbol closest to the received signal is estimated to be the transmitted information symbol. A likelihood called Fano likelihood is used as a measure of closeness. In the Fano algorithm, basically, the information symbol sequence having the largest cumulative likelihood of Fano likelihood is determined to be the transmitted information symbol sequence.

However, if transmission errors occur frequently, it is possible that the wrong information symbol is determined to be the sent information symbol. Once an incorrect decision is made, the internal state of the encoder copy after that is inconsistent with the internal state of the error-correcting encoder, and even if you try to find an information symbol with a large Fano likelihood, you will not be able to find it. It is possible to detect that the judgment is made. When an incorrect decision is detected, the internal state of the encoder copy is returned to the past state, and then the information symbol with the next largest Fano likelihood is sent after the information symbol selected in the past. And try again. Even if an information symbol having the next largest Fano likelihood is to be found, if it cannot be found because it has already been searched, it returns to another past state and performs the same operation. As described above, since decoding may be performed by repeating execution errors and the decoding result once output may be changed later, the decoder needs a buffer for the input received signal and a buffer for the decoding result.

The Fano algorithm described above is based on the American Fano (R.
Invented by M. Fano), IEEE Transactions on inf
ormation Theory, IT-9 (1963) (US) P. 64-74. Further, the error correction encoder and the encoder as described above are disclosed in, for example, US Pat.
It can be realized by the circuit described in 3,665,396.

By the way, in a transmission system such as a digital microwave communication system in which the spectrum width in the carrier band is severely limited, a quadrature modulation method such as four-phase phase modulation or 16-value quadrature amplitude modulation is often used.

When transmitting a code symbol in a transmission system using a quadrature modulation method, each bit constituting the code symbol is divided into two and each bit group T _p , T _q is made to correspond to each quadrature component of the quadrature modulation signal. There is a well-known 4-phase phase uncertainty in demodulating a quadrature modulation signal, and even if there is no transmission error, the phase of the demodulator reference carrier wave (demodulation reference phase) differs from the phase of the modulator carrier wave every 90 degrees. The (hard decision) R _p and R _{q of the} two bit groups output from the demodulator may not match the bit groups T _p and T _q . (R _p , R _q ) is (T _p , T _q ) or Will be either. Therefore, when (R _p , R _q ) does not match (T _p , T _q ), it is detected and a phase shift circuit that performs a logical operation equivalent to rotating the demodulation reference phase every 90 degrees is used. It is necessary to match R _p , R _q with T _p , T _q . R _p , R _q
If does not match T _p and T _q , the received signal (hard decision)
(R _p , R _q ) is erroneous with a very large probability,
Since the decoding does not proceed in the decoder and the buffer of the received signal overflows, the mismatch can be detected.

A conventional sequential decoding device that includes a phase shift circuit and decodes a convolutional code transmitted through a quadrature modulation type transmission path performs a logical operation by trial and error in the phase shift circuit each time the buffer of a received signal overflows. If such trial and error is repeated up to three times, the discrepancy in the demodulation reference phase can be eliminated without fail. It should be noted that it is necessary to discard all received signals stored in the buffer when overflow occurs due to a discrepancy in demodulation reference phase.

[Problems to be Solved by the Invention]

As described above, the conventional iterative decoding apparatus needs to repeat the overflow of the buffer of the received signal at most three times before removing the discrepancy in the demodulation reference phase, which takes a long time and causes an error during this time. There are drawbacks.

An object of the present invention is to provide a sequential decoding device capable of removing a discrepancy in demodulation reference phase in a short time.

[Means for Solving the Problems]

The sequential decoding device of the present invention is controlled by the control signal to control the first received signal obtained by transmitting and demodulating the modulated signal which is orthogonally modulated with the code symbol of the convolutional code, and is based on the four-phase phase uncertainty. Demodulation reference phase conversion means for performing a logical operation by trial and error to eliminate the discrepancy of the demodulation reference phase and outputting the result of the logical operation as a second reception signal, and a predetermined first number of the second reception signals. A reception signal storage unit capable of storing a signal, a decoding result storage unit capable of storing the decoding result of the second reception signal by the predetermined first number, and the second reception signal storing the second reception signal. At the same time as sequentially writing to the means, the decoding result already written from the decoding result storage means is sequentially read and output to the outside, and the decoding of one second received signal read from the received signal storage means is completed. Then the decryption At the same time that the result is written in the decoding result storage means, the second received signal written next to the second received signal which has just been decoded is read out from the received signal storage means, and decoding is tried, When the decoding is to be delayed due to the possibility of an error in the previous decoding, the second received signal written before the second received signal read immediately before is read from the received signal storage means. At the same time, when the decoding of the second received signal to be read now has been completed, the decoding result written in the decoding result storage means is read and the decoding is redone, and the oldest written in the received signal storage means. Decoding is delayed until the second received signal cannot be decoded, and if it is determined that the demodulation reference phase shifting means has a logical operation error, the control signal controls the demodulation reference phase shifting means to perform the logical operation. Redo the second to be subsequently newly written in the received signal storage unit
After performing the reset operation for reading out the received signal and attempting the decoding, the decoding does not proceed until the number of the second received signals for which the decoding is completed reaches the predetermined second number after the reset operation. The first predetermined by the latest second received signal written in the storage means
The decoding is delayed until the second received signal written earlier by a third number less than the number is read out and an attempt is made to make the decoding, each time it is determined that there is an error in the logical operation of the demodulation reference phase shifting means. And a sequential decoding processing means for repeating the reset operation.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings illustrating an embodiment.

FIG. 1 is a block diagram showing an embodiment of the successive decoding apparatus of the present invention.

In the embodiment shown in FIG. 1, a convolutional code symbol having a code rate of 3/4 and one code symbol consisting of 4 bits is transmitted by a transmission system of a 16-value quadrature amplitude modulation system, and a demodulator (receiver end) ( It is a sequential decoding device that decodes received signals D _p1 and D _q1 of 2 bits in parallel, which are hard decisions output by (not shown). A parallel 4-bit reception signal composed of a pair of reception signals D _p1 and D _q1 corresponds to one code symbol.

Reference _numeral 1 is a phase shift circuit, which is controlled by the control signal B1 to output the received signals D _p1 and D _{q1 as} they are as the received signals D _p2 and D _q2 , or the demodulation reference phase of the demodulator is 90 degrees, 180 °. The received signals D _p1 and D _q1 are logically operated and output as the received signals D _p2 and D _{q2 in the same} manner as when they are rotated by 1 degree or 270 degrees. Reference numeral 2 denotes a RAM for buffering a received signal, which has a storage capacity of 4 bits × n words. 3 is a RAM for a decoding result buffer, and 3
It has a storage capacity of bits × n words. Reference numeral 4 denotes a decoding processing unit, which reads the reception signal written in the RAM 2 and sequentially decodes it, and writes the decoding result in the ROM 3. The decoding processing unit 4 is a counter
41 and 42, selector 43, control circuit 44, and decoding circuit 4
It is composed of 5. The counter 41 is a counter whose count output returns from the maximum value (n-1) to 0, and outputs the count signal address signal A1 and control signal B5. The counter 42 is also a similar counter and outputs the address signal A2 and the control signal B7. The selector 43 selects either the address signal A1 or A2 under the control of the control signal B6, and outputs it to the RAMs 2 and 3. The control circuit 44 controls the logical operation of the phase shift circuit 1 by the control signal B1, and controls the writing and reading of the RAMs 2, 3 by the output of the selector 43 and the control signals B2, B3. The decoding circuit 45 performs decoding processing of the received signal according to the control signal B4. The clock signal CL input to the counter 41 is the received signals D _p1 , D _q1 (and D
_p2 , D _q2 ).

When the phase-converted received signal is input, the counter 41
The address signal A1 is incremented by one by counting the clock signal CL. At this time, the control circuit 44 outputs the control signals B2, B3 and B6 in response to the control signal B5 from the counter 41. The selector 43 outputs the address signal A1 in response to the control signal B6. The RAM2 responds to the control signal B2, writes the received signals D _p2 and D _q2 at the address A1, and the RAM3 responds to the control signal B3 to read the decoding result E written at the address A1 and output it to the outside.

On the other hand, the address signal A2 indicates the address of the RAM2 in which the received signal currently being decoded by the decoding circuit 45 is written. The decoding circuit 45 receives the received signal read from the RAM1 immediately before.
When the decoding of D1 is completed, the control signal B4 which notifies the completion of decoding is output. The control circuit 44 outputs control signals B2, B3, B6 and B7 in response to the control signal B4. Selector 43 is a control signal
Address signal A2 is output in response to B6. Decryption result D2
Is written in the address A2 of the RAM3 under the control of the control signal B3. The counter 42 responds to the control signal B7 from the control circuit 44 and increments the address signal A2 by one. And counter
43 responds to the control signal B6 and outputs the address A2 which is increased by one immediately before. Further, the decoding circuit 45 newly reads the next reception signal from the address A2 which is increased by one in the RAM2 under the control of the control signal B2, and decodes this reception signal. Since the decoding processing cycle is sufficiently shorter than the cycle of the clock signal CL,
If the decoding goes smoothly, address A2 catches up with address A1,
Since the latest received signal written in RAM2 is decoded and there is no more received signal to be read, when the value of address signal A2 becomes equal to the value of address signal A1, control circuit 44 causes control signal B4 Is output. And the decoding circuit 45
Responds to the control signal B4 and suspends the decoding process. When the decoding is moved backward, the control circuit 44 controls the control signals B2, B3, B6.
And B7 are output. The counter 42 decrements the address signal A2 by one in response to the control signal B7. Selector 43
In response to the control signal B6, the address A2 which has been decreased immediately before is output. The decoding circuit 45 responds to the control signals B2 and B3, and RAM2,3
Read the received signal (which has been decoded before) and the decoding result from address A2 of and decode again. In this way, the decoding circuit 45 successively decodes the received signal.

The received signal (address A2-1) written immediately before the received signal (address A2 in RAM2) read immediately before from RAM2 is rewritten by the newly received signal (this written address is A1). By the time
In other words, if the decoding is delayed by the time A2-1 = A1, the received signal that has not been decoded will be rewritten by the newly input received signal. Therefore, the control circuit 44 determines that the RAM 2 overflows when A2-1 = A1. When the control circuit 44 determines that the demodulation reference positions of the demodulator are different due to the occurrence of overflow, the control circuit 44 outputs the control signals B1 and B7. The phase conversion circuit 1 responds to the control signal B1 by setting the relative phase relationship between the received signals D _p1 , D _q1 and the received signals D _p2 , D _q2 up to now.
Reset the logical operation to move forward. For example, if the received signals D _p2 and D _q2 were equal to the received signals D _p1 and D _q1 so far, in the future, a logical operation equivalent to advancing the demodulation reference phase by 90 degrees will be performed, and the demodulation reference phase is still 270 degrees. Assuming that the logical operation equivalent to proceeding is performed, the received signal D _p1 ,
D _q1 is output as it is as received signals D _p2 and D _q2 . After redoing this logical operation, the counter 42 responds to the control signal B7 and resets the value of the address signal A2 to the value of the address signal A1. The decoding circuit 45 reads the received signal newly written in the RAM 2 and restarts the decoding.

After the logical operation of the phase shift circuit 1 and the above-mentioned reset of the address signal A2, the address signal A2 becomes the address signal.
If the decoding is delayed until it becomes smaller than A1 by the value n1, the control circuit 44 determines that the demodulation reference phase is still inconsistent and performs the above reset again. In this way, if the reset is repeated up to three times, it is possible to remove the discrepancy in the demodulation reference phase without fail. Decoding should proceed if the demodulation reference phase difference is removed, so the number of received signals that have been decoded after reset is counted, and when this count reaches the value n ₂ , the control circuit
44 determines that the difference in demodulation reference phase has been removed, and thereafter reset is not performed until RAM2 overflows.

If the demodulation reference phase is not correct, the decoding will be delayed rapidly, so by setting the value n ₂ appropriately, even if the value n ₁ is set to be considerably smaller than the number n of addresses of RAM 2, A discrepancy in the demodulation reference phase can be accurately detected.

For the second and subsequent resets, the number of RAM2 addresses is reduced to (n ₁ +1) after the first reset, and this reduced RA
It is equivalent to resetting when M2 overflows.

The operation of the embodiment shown in FIG. 1 has been described above.

If the embodiment shown in FIG. 1 is changed to, for example, 2-bit soft decision, the decoding processing unit 4 is changed to 2-bit soft decision and the input received signals D _p1 and D _q1 are also 4-bit. Since they are arranged in parallel, the number of processing bits of the phase shift circuit 1 and the number of bits per address of the RAM 2 may be changed accordingly.

If a 4-bit code symbol is transmitted by a 4-phase phase modulation type transmission system, since 4 bits of 1 code symbol are transmitted over 2 time slots of the modulation signal, the number of bits of the phase shift circuit 1 is increased. , And a serial converter for parallelizing the received signals of two time slots must be added between the phase shift circuit 1 and the RAM2. This serial-parallel converter needs to perform serial-parallel conversion of the reception signals of two time lots corresponding to one code symbol in code synchronization with the sequence of reception signals, and this code synchronization also eliminates the discrepancy in the demodulation reference phase. Similarly, the decoding process is performed by trial and error. This trial and error is often detected by the RAM2 overflow. In this case, the RAM2 overflow is reset to remove the discrepancy in the demodulation reference phase or to recover the code synchronization. It is necessary to decide separately whether to operate.

In the embodiment shown in FIG. 1, writing and reading are performed in units of one code symbol for the RAM2 and in units of one information symbol for the RAM3, but this is changed to, for example, two symbol units or three symbol units. You can also do it. In this case, the decoding processing unit 4 converts 2 symbols or 3 symbols of a 4-bit code symbol into 8 bits or 12 symbols.
Decoding may be performed by considering it as one symbol of a bit code symbol, or the decoding processing unit 4 may be provided with a reception signal intermediate buffer and a decoding result intermediate buffer each having a storage capacity of 2 symbols or 3 symbols. Add
Received signals from RAM2 and RAM3 via these intermediate buffers,
The exchange of the decoding result can be decoded in units of one code symbol. If a plurality of symbols are accommodated in one address of RAM2 and RAM3 in this way, the degree of freedom in selecting the RAM batchware increases.

There is also known a decoding processing unit that performs decoding not in code symbol units but in each bit unit. The present invention can be applied to the case of performing such a code.

〔The invention's effect〕

As described in detail above, the sequential decoding device of the present invention causes the received signal buffer to overflow due to the discrepancy of the demodulation reference phases and perform the initial reset to remove this discrepancy, and thereafter the received signal buffers. Since the number of addresses is reduced equivalently and the reset is repeated due to the overflow of the reduced buffer, the discrepancy of the demodulation reference phase can be removed in a short time, and the number of received signals to be discarded at the time of reset is also reduced. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the successive decoding apparatus of the present invention. 1 ... Phase conversion circuit, 2, 3 ... RAM, 4 ... Decoding processing unit,
41, 42 ... Counter, 43 ... Selector, 44 ... Control circuit, 45 ... Decoding circuit.

Claims (1)

[Claims] 1. A first received signal obtained by transmitting and demodulating a modulated signal orthogonally modulated with a code symbol of a convolutional code is controlled by a control signal to obtain a demodulation reference phase of four-phase phase uncertainty. A demodulation reference phase shifting means for performing a logical operation by trial and error to remove the discrepancy and outputting the result of the logical operation as a second received signal, and a predetermined first number of the second received signals are stored. An obtained received signal storage means, a decoding result storage means capable of storing the decoding result of the second received signal by the predetermined first number, and sequentially writing the second received signal in the received signal storage means. At the same time as the decoding, the decoding result already written from the decoding result storage means is sequentially read and output to the outside, and when the decoding of one of the second reception signals read from the reception signal storage means is completed, the decoding result is obtained. The above The result when the writing in the storage means now decoded from the received signal storage unit simultaneously is written next to the writing of the completed second received signal the second
Of the received signal is read out from the received signal storing means, and when the decoding is performed backward because there is a possibility of an error in the previous decoding, it is written before the second received signal read immediately before from the received signal storage means. When the second received signal that is being read is read at the same time that the second received signal that is being read is previously decoded, the decoding result written in the decoding result storage means is read and decoding is performed again. Decoding is delayed until the oldest second received signal written in the storage means cannot be decoded, and when it is determined that the logical operation of the demodulation reference phase conversion means is incorrect, the control signal causes the demodulation reference phase. Controlling the conversion means to redo the logical operation,
After that, a reset operation for reading out the second received signal newly written in the received signal storage means and attempting decoding is performed, and after this reset operation, the number of the second received signals for which decoding is completed is predetermined. Decoding does not proceed until the number of 2 is reached, and a third number less than the first number predetermined by the latest second received signal written in the received signal storage means is written before. Decoding is delayed until the second received signal is read out and decoding is attempted, and the successive decoding processing means repeats the reset operation every time it is determined that the logical operation of the demodulation reference phase shifting means is incorrect. Characteristic sequential decoding device.