JPH0683014B2 - Integrator circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a capacitor inside an IC circuit applied to form a control voltage of a VCO (voltage controlled oscillator) of an AFC circuit or an APC circuit of a VTR. The present invention relates to an integrating circuit configured by using the integrating circuit.

[Outline of Invention]

According to the present invention, a capacitor is connected between two output terminals of a differential amplifier, and two output terminals of the differential amplifier are connected to an input terminal of an adder via a first buffer circuit and a second buffer circuit, respectively. The output terminal is derived from the capacitor, the first to fourth transistors are connected to both ends of the capacitor, and the currents corresponding to the input voltage from the other input terminals are added by the first to fourth transistors. Yes, it is an integration circuit capable of performing both integration operation and addition operation.

[Conventional technology]

The VTR recording circuit is provided with an AFC circuit in order to synchronize the conversion carrier signal for low-frequency conversion of the carrier color signal with the horizontal synchronizing signal in the recording video signal. Also, V
In the TR reproducing circuit, an APC circuit is provided in order to synchronize the conversion carrier signal for returning the reproduced low-frequency converted color signal to the carrier color signal with the burst signal in the reproduced signal. A VCO is provided in these AFC circuit and APC circuit.

FIG. 7 shows a conventional configuration for forming the control voltage of the VCO, and in FIG. 7, 21 is the VCO. VCO21 has
The control current from the adder circuit 22 is supplied. The adder circuit 22 is supplied with the current for setting the center frequency from the current source 24 and the error current from the differential amplifier 23. At the time of recording, the differential amplifier 23 is supplied with the AFC error voltage from the AFC filter 27 through the r-side terminal of the recording / reproducing changeover switch 25,
During reproduction, the APC voltage from the APC filter 29 is supplied via the p-side terminal of the recording / reproduction switching switch 25. The AFC filter 27 is supplied with the AFC detection voltage from the input terminal 26, and
The APC detection voltage is supplied to the PC filter 29 from the input terminal 28.

Further, in the APCID circuit 30, the signal obtained by dividing the output signal of the VCO 21 and the signal obtained by dividing the horizontal synchronizing signal from the input terminal 31 are phase-compared, and the oscillation frequency of the VCO 21 is outside the pull-in range of the APC. Is detected. Hold circuit in which the ID error current from the APCID circuit 30 has a capacitor 33
The voltage is supplied to 32, and the hold circuit 32 generates an ID error voltage. This ID error voltage is converted into an ID error current by passing through the diode and the resistance circuit 34, and this ID error current is supplied to the hold circuit 35 having the capacitor 36.

In order to keep the DC potential of the AFC error voltage or APC error voltage through the recording / playback switch 25 constant,
Differential amplifier 37, hold circuit 35 and differential amplifier 38 described above
Is provided for VCO21. Differential amplifier 37 and 38
Is for converting an input voltage into an output current.
The hold circuit 35 has a sufficiently long time constant to form a DC feedback path. The capacitor 36 having a large capacity is connected to the outside of the IC circuit, and the current of the DC feedback path and the ID error current are added in this capacitor 36.

In the circuit that forms the VCO control signal as described above, the holding capacitors 33 and 36 are external parts of the IC circuit. Therefore, by incorporating these capacitors 33 and 36 inside the IC, the configuration shown in FIG. 7 can be realized entirely by the elements inside the IC. In this case, since the hold circuit 35 forming the DC feedback path has a considerably long time constant, it is necessary to devise a device for making it into an IC.

The balance-type integrating circuit according to the proposal of the inventor of the present application can minimize the charging / discharging current of the capacitor, and has an expanded output dynamic range.
It is suitable to be applied to.

[Problems to be solved by the invention]

In the IC-type balanced integration circuit, the addition of the output signal of the DC feedback path and the ID error signal cannot be configured to supply both signal currents to an external large-capacity capacitor, unlike the conventional configuration. .

Therefore, an object of the present invention is to provide an integrator circuit that can add another input signal such as an ID error signal by using an IC type balanced integrator circuit.

[Means for solving problems]

According to the present invention, a differential amplifier in which a capacitor is connected between one output terminal and the other output terminal, and one output terminal and one input terminal of the differential amplifier are connected via a first buffer circuit. In addition to being connected, the other output terminal and the other input terminal of the differential amplifier are connected via the second buffer circuit, and an adder from which an output signal is taken out and both ends of the capacitor and a collector are connected. The first and second transistors, the third and fourth transistors in which the emitters and emitters of the first and second transistors are commonly connected, and the other input terminal is derived from the base, and the first and second transistors
And an electric current source inserted between each of the transistors and the reference potential point.

[Action]

Since the capacitor is connected between the opposite-phase output terminals of the differential amplifier, the dynamic range of the output is double that of the conventional integrating circuit. Also, another input signal such as an ID error signal can be current-added to both ends of the capacitor.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In this example, all elements including capacitors are
It is built into the IC. This one embodiment will be described in the following order of items.

Overall configuration of one embodiment b. Balanced integration circuit c. Concrete connection of balanced integration circuit d. Interface with integration circuit a. Overall configuration of one embodiment FIG. The structure of one embodiment applied to a filter is shown. The AFC circuit is provided in the recording circuit of the rotary head type VTR and is used to generate a conversion carrier signal for converting a carrier color signal into a low frequency conversion color signal. The AFC circuit, the center frequency is 378f _H (f _H:
A horizontal scanning frequency) VCO is provided, and the conversion carrier signal of 743 [kHz] is formed by dividing the output signal of this VCO into (1/8). In addition, the signal obtained by dividing the VCO output signal and the horizontal synchronization signal are phase-compared by the AFC detection circuit, and the phase comparison output is VC through the low-pass filter.
Supplied as a control voltage to O. In this case, if the phase of the VCO output signal and the horizontal sync signal are significantly deviated, the first
In the figure, the control voltage of the VCO is forcibly increased or decreased by the AFCID circuit indicated by 20.

In FIG. 1, an AFC error signal from the AFC detection circuit is supplied to an input terminal indicated by 18, and this AFC error signal is supplied to the addition circuit 9 via the low pass filter 19. The output signal of the low-pass filter 19 is supplied to the adding circuit 12.
The output signal of the adder circuit 12 is supplied to one input terminal of the differential amplifier 11. The differential amplifier 11, the constant current source 14, the switching circuit 15, the capacitor 16, and the buffer circuit 17 constitute an integrating circuit similar to the conventional one. A negative feedback path including an attenuator 13 is provided between the output terminal of the buffer circuit 17 and the adder circuit 12.

The output signal of the buffer circuit 17 is supplied to the adding circuit 9 and also to one input terminal of the differential amplifier 1. The differential amplifier 1, the reference voltage source 3, the constant current source 4 and the switching circuit 5 constitute a balanced type integrating circuit described later. The output signal of this integrating circuit is supplied to the adding circuit 9. The ID error signal formed in the AFCID circuit 20 is AFC
It is added to the error signal. This ID error signal is
The voltage is added to both ends of the capacitor 6 by current addition, and is also added to the other input terminal of the differential amplifier 11 of the integrating circuit of the preceding stage by voltage addition in order to accelerate the pull-in.

The above-described filter shown in FIG. 1 is a low-pass characteristic of the first stage low-pass filter 19 and a low-pass characteristic indicated by a in FIG. It has a frequency characteristic obtained by combining the low-pass characteristic indicated by c. The low-pass characteristic b has an attenuation gradient of -6 [dB / oct], and the low-pass characteristic c has an attenuation gradient of -12 [dB / oct]. The low-pass characteristics a and b realize characteristics similar to those of the lag lead filter. Further, the integration circuit including the differential amplifier 1 has a long time constant,
It has a characteristic that the attenuation gradient is large, and a DC feedback loop is formed by this integrating circuit. The APC circuit provided in the reproduction circuit of the VTR has the same configuration as the above AFC circuit.

b. Balance-type integrator circuit FIG. 3 shows the configuration of the balance-type integrator circuit. In FIG. 3, one input terminal of the differential amplifier indicated by 1 is derived as the input terminal 2 and the other of the differential amplifier 1 is shown. The reference voltage source 3 is connected to the input terminal. The constant current supplied to the differential amplifier 1 is the constant current generated by the constant current source 4 switched by the switching circuit 5.

A capacitor 6 is inserted between one output terminal of the differential amplifier 1 and the other output terminal. One output terminal of the differential amplifier 1 is connected to one input terminal of the adder 9 via the buffer circuit 7, and the other output terminal of the differential amplifier 1 is connected to the other input terminal of the adder 9 via the buffer circuit 8. Connected to the input terminal. The output terminal of the adder 9 is derived as the output terminal 10. The adder 9 produces a current output.

In the above-mentioned integrating circuit, since the output signals of the opposite phase of the differential amplifier 1 are supplied to both ends of the capacitor 6, the middle point of the capacitor 6 becomes an AC ground point. Therefore, the third
The circuit connections shown in the figure can be represented by the equivalent circuit shown in FIG. When the value of the capacitor 6 is C, the value of the divided capacitors 6A and 6B in FIG. 4 is 2C.
When an output voltage of +1 V is generated at one output terminal of the differential amplifier 1, an output voltage of -1 V is generated at the other output terminal. Conversely, when an output voltage of + 1V is generated at one output terminal, an output voltage of -1V is generated at the other output terminal. Therefore, the output dynamic range is ± 2V,
It can be expanded to twice the size of a conventional integrating circuit.

c. Concrete Connection of Balance-type Integrator Circuit FIG. 5 shows a concrete connection of the integrator circuit shown in FIG. The input terminal 2 to which an input signal such as an AFC error signal is supplied is supplied to a differential amplifier 55 using a pair of Darlington connections and converted into a differential signal current.

A series connection of a constant current source 58 and diode-connected transistors 56 and 57 is inserted between the power supply line 51 and the ground line 53, and one of the differential signal currents is supplied to the connection point of the transistors 56 and 57. . The connection point of the constant current source 58 and the transistor 56 is connected to the base of the transistor 59. The collector of the transistor 59 is connected to the power supply line 51, the emitter of the transistor 59 is grounded via the constant current source 60, and is connected to the base of the transistor 64 via the resistor 61. The base of the transistor 64 is grounded via the collector and emitter of the transistor 62.
A switching pulse is supplied to the base of the transistor 62 from the terminal 63. When the switching pulse is at high level, the transistor 62 turns on and the transistor 64 turns off.

The other signal current taken out to the other output terminal of the differential amplifier 55 is supplied to the base of the transistor 74 through the circuit configuration similar to the above-mentioned one signal current configuration. That is, transistors 66, 67, 69, 72 corresponding to the transistors 56, 57, 59, 62 are provided, constant current sources 68 and 70 corresponding to the constant current sources 58 and 60 are provided, and a resistor 61 and a corresponding resistor are provided. 71 are provided.

The emitters of the transistors 64 and 74 are grounded, and the capacitor 6 is inserted between the collectors of the transistors. In addition, the collectors of the transistors 64 and 74 are connected to the transistor 75, respectively.
And 76 to the respective collectors. A predetermined DC voltage source 77 is connected to the bases of the transistors 75 and 76, respectively. The emitters of the transistors 75 and 76 are connected to the power supply line 52 via the collector-emitter of the transistors 78 and 79.

One output voltage of the differential output voltage extracted across the capacitor 6 is supplied to the emitter follower connection composed of the Darlington connection 81 and the constant current source 82, and the output signal of this emitter follower connection serves as the transistor 83 and the level shift diode. It is supplied to the base of a transistor 86 via an emitter follower connection consisting of a transistor 84 and a constant current source 85. The emitter of the transistor 86 is grounded via the resistor 87, and its collector is connected to the power supply line 51.

Regarding the other output voltage of the differential output voltage taken across the capacitor 6, the same connection as the above-mentioned one output voltage is provided. That is, the Darlington connection 91 and the constant current source 92 constitute an emitter follower connection, and the transistor 93, the diode-connected transistor 94 and the constant current source 95 constitute another emitter follower connection, and the output voltage via the other emitter follower connection is Connected to the base of transistor 96. The emitter of the transistor 96 is grounded via the resistor 97, and its collector is connected to the power supply line 51.

The transistors 86 and 96 are emitter follower transistors, and differential output voltages are taken out from the respective emitters of these transistors 86 and 96. Further, for the midpoint control, the emitters of the transistors 86 and 96 are connected to each other via resistors 88 and 98 having the same value,
The midpoint potential is taken out from the connection point of the resistors 88 and 98. The resistors 88 and 98 form a resistance adding circuit.

This midpoint potential is one of the transistors 101 of the differential amplifier 100.
Supplied to the base of. To the base of the other transistor 102 of the differential amplifier 100, the reference voltage source 103 corresponding to the potential to be controlled of the midpoint potential is connected. 104 is
It is a constant current source of the differential amplifier 100. The collector of the transistor 101 is connected to the power supply line 52, and the collector of the transistor 102 is connected to the collector of the transistor 105.
The emitter of the transistor 105 is connected to the power supply line 52. The base of the transistor 105 is commonly connected to the bases of the transistors 78 and 79 described above to form a current mirror circuit. The transistor 106 is connected for hfe (grounded emitter current amplification factor) cancellation.

Further, the output voltages taken out from the respective emitters of the transistors 86 and 96 are supplied to the bases of the transistors 111 and 112 forming the Gilbert-type adder circuit. Transistors 111 and 112 form a differential amplifier, and their respective collectors are connected to the emitters of transistors 113 and 114. A common DC voltage source 115 is connected to the bases of the transistors 113 and 114, and the collectors of the transistors 113 and 114 are connected to the power supply line 52.

The collectors of transistors 111 and 112 are transistor 116.
And 117, and a constant current source is connected to the common emitter connection point of the transistors 116 and 117. The collector of the transistor 116 is connected to the power supply line 52, and the collector of the transistor 117 is connected to the power supply line 52 via the diode-connected transistor 118. The added output current taken out to the collector of the transistor 117 is taken out to the output terminal 10 via the transistor 118 and the transistor 119.

Both ends of the capacitor 6 are connected to the collectors of the transistors 121 and 122, respectively. The emitters of the transistors 121 and 122 are connected to the ground line 54 via resistors, and the transistors 126 and 127 are connected via resistors 124 and 125.
Connected to the emitter of. A DC voltage source 123 is commonly connected to the bases of the transistors 121 and 122. Each of the transistors 126 and 127 is connected to the power supply line 52, the input terminal 128 is derived from the base of the transistor 126, and the input terminal 129 is derived from the base of the transistor 127.
Is derived.

An ID error signal is supplied to the input terminals 128 and 129, respectively. The ID error signal becomes a high level during the normal operation in which the phase of the output signal of the VCO is not greatly deviated from the phase of the horizontal synchronizing signal, the transistor 126 or the transistor 127 is turned on, and these transistor and the resistor 124 or 125 and the emitter resistor are turned on. Current flows through. Therefore, in this normal operation, the transistors 121 and 122 are cut off, and the ID error signal is not added to the AFC error signal.

When the phase of the output signal of the VCO deviates significantly from the phase of the horizontal synchronizing signal, one of the input terminals corresponding to the direction of the deviation becomes low level. When one of the input terminals 128 becomes low level, the transistor 126 is cut off, and a predetermined direct current, for example, a direct current of 80 [nA] flows through the transistor 121.
When the other input terminal 129 goes low, the transistor 1
27 is cut off, and a predetermined direct current flows through the transistor 122. As a result, the potential at one end of the capacitor 6 is forcibly increased or decreased.

In this configuration described above, the differential signal current extracted by the differential amplifier 55 corresponds to the difference between the input voltage applied to the input terminal 2 and the reference voltage. This differential signal current is converted into a minute current of (1 / x) times and becomes a collector current of the transistors 64 and 74.

The base-emitter voltage of the transistor 56 is V _BE1 ,
The base-emitter voltage of the transistor 57 is V _BE2 ,
The constant current of the constant current source 58 is I ₁ , and the constant current of the constant current source 60 is xI
_1, and the base-emitter voltage of transistor 59 is V
_BE3 , the base-emitter voltage of the transistor 64 is V
_BE4 and the constant current flowing when the transistor 64 is turned on is I ₀
Then, the base potential Va of the transistor 59 and the emitter potential Vb of the transistor 59 have the following relationship.

(K: Boltzmann's constant, T: absolute temperature, q: electron charge, Is: saturation current) From the above formula, (I ₀ = I ₁ / x). Therefore, by setting (x> 1), the current I ₀ reduced to (1 / x) of I ₁ can be passed through the transistor 64. When turning off the current I ₀ , the transistor 62 is turned on.

The other signal currents of the differential signal currents are similarly reduced to (1 / x) and flow through the transistor 74. In addition, since the capacitor 6 is directly connected to the collectors of the transistors 64 and 74, the switching speed is increased, and the collector currents of the transistors 64 and 74 can be made minute currents, for example, 40 [nA]. . Therefore, the time constant can be made longer than in the conventional case.

Further, control is performed so that the midpoint potential of the capacitor 6 is always located at the central potential of the dynamic range, and the dynamic range of the output can be effectively used. As shown in FIG. 5, the DC potentials at both ends of the capacitor 6 are V _A and V _B , the emitter potentials (DC potential) of the transistors 86 and 96 are V _C and V _D , and the reference voltage source 103 The midpoint control will be described below with the reference voltage by Vr as Vr.

The potentials V _A and V _B are DC-equal, and the potentials V _A and V _B
Is transmitted to the emitters of the transistors 86 and 96 through the base-emitters of the emitter-follower-connected transistors, but the cancellation of the base-emitter voltage results in (V _A = V _B = V _C = V _D ). Resistance 88
And the value of the resistor 98 are made equal, and the potential of the connection point of both is set to V _E
And Let Vt be the potential to be controlled of the midpoint potential of the capacitor 6, and (Vt = Vr).

In normal operation, the signal current, the voltage change V.alpha occurs, the _{(V A = Vt + Vα,} V B = Vt-Vα). Therefore, V _E = 1/2 (V _A + V _B ) = 1/2 (V _C ± V _D ) = Vt (Vt = Vr)
01 and 102 are in balance. Set the constant current of the constant current source 104 to 2I ₂
Then, by the transistors 105, 78, 79, a constant current I ₀ flows through the transistors 75 and 76, respectively, and is controlled so as to be balanced with the currents of the transistors 64 and 74, respectively.

When both V _A and V _B increase in potential by V β, that is, when V _A = Vt + Vα + Vβ V _B = Vt−Vα + Vβ, V _E = Vt + Vβ. As the base potential of the transistor 101 rises by Vβ, the currents flowing through the transistors 75 and 76 are both reduced from I ₂ . Therefore, the potentials V _A and V _B are lowered, and negative feedback is applied to suppress the potential rise Vβ.

Further, even when the potentials of both V _A and V _B are reduced by Vβ, the negative feedback in which the reduction in potential Vβ is suppressed by the fact that the currents flowing through the transistors 75 and 76 both increase above I ₂ contrary to the above. Takes.

As described above, the midpoint potential Vt of the capacitor 6 is always controlled to (Vt = Vr) and is maintained at the center of the dynamic range.

d. Interface with integrating circuit In the configuration shown in FIG. 1, the ID error signal from the AFCID circuit 20 is added to the integrating circuit composed of the differential amplifier 11 via the interface shown in FIG.

In FIG. 6, the broken line portion shows the configuration of the portion of the integrating circuit including the differential amplifier 11, the resistors 131 and 132 configure an adding circuit, and the terminal 133 is supplied with the reference voltage.

A series circuit of a constant current source 136, a diode-connected transistor 137, and a resistor is inserted between the power supply line 134 and the ground line 135. A series circuit of a resistor-diode-connected transistor 139, a transistor 138, and a resistor is connected between a power supply line 134 and a ground line 135. Resistors and transistors 141
A series circuit of a diode-connected transistor 140 and a resistor is connected between the power supply line 134 and the ground line 135. A series circuit of a resistor, a transistor 143, a transistor 142 and a resistor is connected between the power supply line 134 and the ground line 135.

The bases of the transistors 137, 138, 140 and the base of the transistor 142 are connected via the resistor 144, and the transistor 144
Is connected to the ground line 135 via the collector and the emitter of the transistor 145, and the base of the transistor 145 is led out to be the input terminal 147. Further, the bases of the transistors 139, 141, 143 are commonly connected. The emitter of the transistor 143 is connected to the ground line 135 through the resistor and the collector and emitter of the transistor 146, and the base of the transistor 146 is led out to the input terminal 148.
It is said that An ID error signal is supplied to these input terminals 147 and 148. Further, the connection point between the collector of the transistor 143 and the collector of the transistor 144 is connected to the base of one transistor of the differential amplifier 11.

Assuming that the constant current of the constant current source 136 is I ₃ , the constant current I ₃ flows through the transistor 137, so that the transistors 139 and 13
A constant current I ₃ flows through the series circuit of 8 and the transistors 141 and 14
A constant current I ₃ flows in a series circuit of 0s. During normal operation, the ID error signals supplied to the input terminals 147 and 148 are both at the high level, and the transistors 145 and 146 are both on. At this time, the constant current I ₃ stops flowing through the transistor 142, and the constant current I ₃ flowing through the transistor 143 is bypassed. Therefore, no output current is generated for the differential amplifier 11 of the integrating circuit.

Here, when the low-level ID signal is supplied to only one input terminal 148, the transistor 146 is turned off, the constant current I ₃ flows through the transistor 143, and the transistor 143 is turned on.
An output current is generated that flows from the collector to the terminal 133 of the integrating circuit via the resistor 132. When the low-level ID signal is supplied only to the other input terminal 147, the transistor 145 is turned off and the constant current I ₃ flows through the transistor 142. Therefore, an output current in the direction of flowing out from the terminal 133 of the integrating circuit via the resistor 132 is generated. The voltage drop generated by the resistor 132 is added to the AFC error voltage.

〔The invention's effect〕

According to the present invention, it is possible to realize an integrator circuit that can be incorporated in an IC, can increase the output dynamic range as compared with the conventional one, and can add another input signal such as an ID error signal.

[Brief description of drawings]

1 and 2 are a connection diagram and a schematic diagram of frequency characteristics showing a configuration of an embodiment in which the present invention is applied to an AFC circuit, and FIG.
FIG. 4 is a connection diagram of a balanced type integrating circuit used in one embodiment of the present invention, FIG. 4 is a connection diagram showing an equivalent circuit of this integrating circuit, and FIG. 5 is a partial connection diagram of one embodiment of the present invention. 6 is a partial connection diagram of an embodiment of the present invention, and FIG. 7 is a conventional AF.
It is a connection diagram used for the description of the C circuit. Description of main symbols in the drawing 1: Differential amplifier, 2: Input terminal, 4: Constant current source, 6: Capacitor, 7,8: Buffer circuit, 9: Adder circuit, 10: Output terminal, 12
1,122: first and second transistors, 126,127: third and fourth transistors, 128,129,147,148: input terminals for ID error signal.

Claims (1)

[Claims] 1. A differential amplifier in which a capacitor is connected between one output terminal and the other output terminal, and one output terminal and one input terminal of the differential amplifier form a first buffer circuit. And the other output terminal and the other input terminal of the differential amplifier are connected via the second buffer circuit, and the adder from which the output signal is taken out and the both ends and the collector of the capacitor are connected. The connected first and second transistors, the third and fourth transistors in which the emitters and emitters of the first and second transistors are commonly connected, and the other input terminal is derived from the base; An integrator circuit including first and second transistors and a current source inserted between the reference potential points.