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JPH0678549A - Circuit system of inverter - Google Patents

Circuit system of inverter

Info

Publication number
JPH0678549A
JPH0678549A JP4229006A JP22900692A JPH0678549A JP H0678549 A JPH0678549 A JP H0678549A JP 4229006 A JP4229006 A JP 4229006A JP 22900692 A JP22900692 A JP 22900692A JP H0678549 A JPH0678549 A JP H0678549A
Authority
JP
Japan
Prior art keywords
inverter
elements
semiconductor element
circuit
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4229006A
Other languages
Japanese (ja)
Inventor
Katsuyuki Watanabe
勝之 渡辺
Masato Mori
真人 森
Tadashi Shibuya
忠士 渋谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Priority to JP4229006A priority Critical patent/JPH0678549A/en
Publication of JPH0678549A publication Critical patent/JPH0678549A/en
Pending legal-status Critical Current

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  • Inverter Devices (AREA)

Abstract

PURPOSE:To balance currents without uniformizing the characteristics of the connected-in-parallel elements of an inverter or converter strictly. CONSTITUTION:The parallel elements U1 and U2 of the upper arm of an inverter and those X1 and X2 of the lower arm are connected in series respectively. To their connected points (a1) an (a2) AC wires W1 and W2 of large impedance, with the other ends (a) connected to each other, are connected, and the current burden between the parallel elements is made even. The parallel elements X1 and X2 of the lower arm are controlled by a common gate circuit Gx. While, the gates of the parallel elements U1 and U2 of the upper arm are controlled by gate circuits GU1 and GU2 insulated respectively, and shortcircuiting of the connected points (a1) and (a2) by the gate circuits is prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、IGBTトランジスタ
等の半導体素子を並列に使用したインバータの回路方式
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter circuit system in which semiconductor elements such as IGBT transistors are used in parallel.

【0002】[0002]

【従来の技術】従来、半導体素子を並列に使用した単相
インバータの回路例を図3に示す。この場合並列に接続
した半導体素子T1,T2に流れる電流バランスは、素子
の順方向のオン時の電圧降下VFF特性を揃えると共に電
気回路の配線インピーダンスを等しくすることによって
揃えている。
2. Description of the Related Art Conventionally, a circuit example of a single-phase inverter using semiconductor elements in parallel is shown in FIG. In this case, the currents flowing through the semiconductor elements T 1 and T 2 connected in parallel are made uniform by aligning the voltage drop V FF characteristics when the elements are turned on in the forward direction and equalizing the wiring impedance of the electric circuit.

【0003】[0003]

【発明が解決しようとする課題】上記半導体素子電流の
バランスを揃えたインバータは、単に直流,交流の変換
装置として商用周波数程度の比較的力率のよい負荷に適
用する場合には実用上問題が発生しない。
The above-mentioned inverter having a well-balanced semiconductor element current has a practical problem when it is applied as a DC / AC converter to a load having a relatively high power factor such as a commercial frequency. Does not occur.

【0004】しかし、モータ制御のように低い周波数か
ら使用したり、又系統との連系のように回生領域で使用
したりすると下記の理由で電流がバランスしなくなる。
However, when it is used from a low frequency such as motor control, or when it is used in a regenerative region such as interconnection with a system, the current is unbalanced for the following reasons.

【0005】(1)低周波数の場合 モータ制御に使用する場合インバータの周波数範囲は数
Hzから数百Hzまで使用される。数Hzのような低い
周波数で使用すると、配線インピーダンスが殆どなくな
って素子のVFF特性のみで電流分担が決まり、高精度の
素子特性が必要となるため製作上の支障が発生する。
(1) Case of low frequency When used for motor control The frequency range of the inverter is from several Hz to several hundred Hz. When it is used at a low frequency such as several Hz, the wiring impedance is almost eliminated, the current sharing is determined only by the V FF characteristic of the element, and high-precision element characteristic is required, which causes a trouble in manufacturing.

【0006】(2)回生領域の場合 系統と連系するインバータは駆動と回生の領域で使用す
る。駆動の場合素子に流れる電流は順方向に流れ、回生
の場合逆方向に流れる。このため素子の選別はVFF特性
と逆方向に電流が流れた場合の電圧特性VFR特性を揃え
ることが必要となる。
(2) In case of regeneration area The inverter connected to the grid is used in the drive and regeneration areas. In the case of driving, the current flowing through the element flows in the forward direction, and in the case of regeneration, it flows in the reverse direction. Therefore, it is necessary to select the elements so that the voltage characteristic V FR characteristic when the current flows in the opposite direction to the V FF characteristic is made uniform.

【0007】モータ制御でも回生領域で電流が大きい場
合は素子のVFFとVFRの両特性を揃える必要がある。こ
のため素子の選別条件が難しくなり実用的に支障が発生
する。特に、U相,X相2アームで構成された素子を並
列で使用する場合、P相,N相それぞれのVFF,VFR
性を合わせる必要があるため、更に選別条件が厳しくな
る。
Even in motor control, when the current is large in the regenerative region, it is necessary to make both the characteristics of V FF and V FR of the element uniform. For this reason, it becomes difficult to select conditions for the elements, which causes a practical problem. In particular, when using elements composed of two arms of U-phase and X-phase in parallel, it is necessary to match the V FF and V FR characteristics of the P-phase and the N-phase, respectively, and the selection conditions become more severe.

【0008】本発明は、従来のこのような問題点に鑑み
てなされたものであり、その目的とするところは、並列
接続素子の特性を厳しく揃えることなく電流のバランス
をとりうるインバータの回路方式を提供することにあ
る。
The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a circuit system of an inverter capable of balancing currents without strictly aligning characteristics of parallel-connected elements. To provide.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に、本発明における変換器の回路方式は、主回路の上,
下のアームにそれぞれ複数の半導体を並列に使用するイ
ンバータにおいて、上,下アームの各半導体素子をそれ
ぞれ直列に接続すると共に、上アームの各半導体素子を
プラス極に共通に接続し、下アームの各半導体素子をマ
イナス極に共通に接続する。
In order to achieve the above object, the circuit system of the converter according to the present invention is based on the main circuit:
In an inverter that uses a plurality of semiconductors in parallel in the lower arm, each semiconductor element of the upper and lower arms is connected in series, and each semiconductor element of the upper arm is commonly connected to the positive pole, Each semiconductor element is commonly connected to the negative pole.

【0010】前記直列に接続した各半導体素子の接続点
に他端が接続された複数の交流線をそれぞれ接続する。
下アーム側の各半導体素子は共通のゲート回路で制御
し、上アームの各半導体素子は絶縁された各ゲート回路
で制御する。
A plurality of alternating current lines, the other ends of which are connected, are connected to the connection points of the respective semiconductor elements connected in series.
Each semiconductor element on the lower arm side is controlled by a common gate circuit, and each semiconductor element on the upper arm is controlled by each insulated gate circuit.

【0011】[0011]

【作用】上アームと下アームの並列素子である複数の半
導体素子はそれぞれ直列に接続され、その各接続点に他
端が接続された複数の交流線がそれぞれ接続されている
ので、各半導体回路の交流側インピーダンスは交流線に
よる配線インピーダンス分大きくなる。
A plurality of semiconductor elements, which are parallel elements of the upper arm and the lower arm, are connected in series, and a plurality of alternating current lines whose other ends are connected are connected to the respective connection points. The AC side impedance of is increased by the wiring impedance of the AC line.

【0012】この配線インピーダンスは半導体素子のイ
ンピーダンスより大きいので、各半導体の特性に多小相
違があっても並列された各半導体素子の電流分担は平衡
する。
Since this wiring impedance is larger than the impedance of the semiconductor element, the current sharing of the paralleled semiconductor elements is balanced even if there are many differences in the characteristics of each semiconductor.

【0013】下アームの各半導体はマイナス極に共通に
接続されているので、共通のゲート回路で制御すること
ができる。
Since the semiconductors of the lower arm are commonly connected to the negative pole, they can be controlled by a common gate circuit.

【0014】上アームの各半導体の交流側(エミッタ)
は交流線を介して接続されているが、絶縁した各ゲート
回路で各半導体を制御するので、支障なく制御できる。
AC side (emitter) of each semiconductor of the upper arm
Is connected via an AC line, but since each semiconductor is controlled by each insulated gate circuit, control can be performed without any trouble.

【0015】[0015]

【実施例】本発明の実施例を図面を参照して説明する。Embodiments of the present invention will be described with reference to the drawings.

【0016】図1はインバータ主回路を示し、図2はゲ
ート回路を示す。
FIG. 1 shows an inverter main circuit, and FIG. 2 shows a gate circuit.

【0017】図1,図2において、U1,U2は上側U相
アームの並列半導体素子、X1,X2は下側X相アームの
並列半導体素子で、素子U1,U2のコレクタをプラス母
線Pに接続し、素子X1とX2のエミッタをマイナス母線
Nに接続する。
1 and 2, U 1 and U 2 are parallel semiconductor elements of the upper U-phase arm, X 1 and X 2 are parallel semiconductor elements of the lower X-phase arm, and collectors of the elements U 1 and U 2 . Is connected to the positive bus P, and the emitters of the elements X 1 and X 2 are connected to the negative bus N.

【0018】上アーム素子U1,U2のエミッタを下アー
ム素子X1,X2のコレクタに夫々接続し、その接続点a
1及びa2を直接接続して交流端子とせずに、夫々2本の
交流線W1,W2により負荷L側まで引出し接続aする。
The emitters of the upper arm elements U 1 and U 2 are connected to the collectors of the lower arm elements X 1 and X 2 , respectively, and their connection points a
1 and a 2 are not directly connected to each other to form an AC terminal, but two AC lines W 1 and W 2 are respectively drawn out and connected a to the load L side.

【0019】素子X1とX2のエミッタはマイナス母線N
に接続され共通となっているので、電位差が殆どないた
め、素子X1とX2のゲートは共通ゲート回路GXで駆動
する。
The emitters of the elements X 1 and X 2 are the negative bus N
The gates of the elements X 1 and X 2 are driven by the common gate circuit G X because they are connected to each other and have a common potential.

【0020】素子U1とU2のエミッタ間には線W1,W2
により電位差があるので、絶縁されたゲート回路GU1
U2を用いて素子U1,U2のゲートを別々に駆動する。
The element U 1 and line W 1 is between the emitters of U 2, W 2
Since there is a potential difference due to, the insulated gate circuit G U1 ,
G U2 is used to drive the gates of devices U 1 and U 2 separately.

【0021】V相,Y相のアーム回路及びゲート回路は
上記U相,X相のアーム回路及びゲート回路と同様に構
成する。
The V-phase and Y-phase arm circuits and gate circuits are constructed similarly to the U-phase and X-phase arm circuits and gate circuits.

【0022】なお、図中TRは絶縁トランス、Rf1〜R
f3はトランスTRの2次巻線n1〜n3電圧を整流しゲー
ト回路GU1,GU2,GXの電源を出力する整流回路を示
す。
In the figure, TR is an insulating transformer, R f1 to R
f3 denotes a rectifier circuit that outputs the power of the secondary winding n 1 ~n 3 rectifies the voltage gate circuit G U1, G U2, G X of the transformer TR.

【0023】以上のように構成されているので、各素子
の交流側配線インピーダンスが交流線W1,W2により大
きくなり各相における並列素子の電流分担のバランスが
しやすくなる。また、U相,V相アームの各素子は絶縁
したゲート回路により駆動されるので、エミッタ電位が
異なっていても影響されることはない。
With the above-mentioned structure, the AC side wiring impedance of each element is increased by the AC lines W 1 and W 2 , and the current sharing of the parallel elements in each phase can be easily balanced. Further, since each element of the U-phase and V-phase arms is driven by the insulated gate circuit, there is no influence even if the emitter potential is different.

【0024】上記実施例は、並列素子数2であるが、こ
れに限定されるものではなく3以上いくらあっても同様
に実施できる。また、単相インバータについて示した
が、多相インバータについても同様に実施することがで
きる。また、本発明はコンバータにも応用できる。
In the above embodiment, the number of parallel elements is 2. However, the number of parallel elements is not limited to this, and any number of parallel elements of 3 or more can be similarly applied. Further, the single-phase inverter is shown, but the same can be applied to a multi-phase inverter. The present invention can also be applied to converters.

【0025】[0025]

【発明の効果】本発明は、上述のように構成されている
ので、次に記載する効果を奏する。
Since the present invention is configured as described above, it has the following effects.

【0026】(1)インバータ主回路の並列素子の電流
バランスが取り易くなる。
(1) It becomes easy to balance the currents of the parallel elements of the inverter main circuit.

【0027】(2)このため並列接続する素子の選別が
容易になる。
(2) Therefore, it becomes easy to select the elements to be connected in parallel.

【0028】(3)電流バランスがよくなるので素子の
並列数を低減することが可能となる。
(3) Since the current balance is improved, the number of parallel elements can be reduced.

【0029】(4)これらのことからインバータ装置の
小形化,経済化ができる。
(4) From the above, the inverter device can be made compact and economical.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例にかかるインバータの主回路を示す回路
図。
FIG. 1 is a circuit diagram showing a main circuit of an inverter according to an embodiment.

【図2】同インバータのゲート回路を示す回路図。FIG. 2 is a circuit diagram showing a gate circuit of the inverter.

【図3】従来インバータの主回路を示す回路図。FIG. 3 is a circuit diagram showing a main circuit of a conventional inverter.

【符号の説明】[Explanation of symbols]

1,T2,U1,U2,X1,X2…半導体素子 GU,GU1,GU2,GX…ゲート回路 W1,W2…交流線 T 1, T 2, U 1 , U 2, X 1, X 2 ... semiconductor element G U, G U1, G U2 , G X ... gate circuit W 1, W 2 ... AC line

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 主回路の上,下のアームにそれぞれ複数
の半導体を並列に使用したインバータにおいて、 上,下アームの各半導体素子をそれぞれ直列に接続する
と共に、上アームの各半導体素子をプラス極に共通に接
続し、下アームの各半導体素子をマイナス極に共通に接
続し、前記直列に接続した各半導体素子の接続点に他端
が互いに接続された複数の交流線を接続し、下アーム側
の各半導体素子を共通のゲート回路で制御し、上アーム
の各半導体素子を絶縁された各ゲート回路で制御するこ
とを特徴としたインバータの回路方式。
1. An inverter using a plurality of semiconductors in parallel in upper and lower arms of a main circuit, wherein each semiconductor element of the upper and lower arms is connected in series and each semiconductor element of the upper arm is positively connected. Commonly connected to the pole, each semiconductor element of the lower arm is commonly connected to the negative pole, the plurality of alternating current lines whose other ends are connected to each other are connected to the connection point of the semiconductor elements connected in series, An inverter circuit system characterized in that each semiconductor element on the arm side is controlled by a common gate circuit, and each semiconductor element on the upper arm is controlled by each insulated gate circuit.
【請求項2】 交流電流を検出する変流器を他端が互い
に接続された複数の交流線が共通するように設けたこと
を特徴とした請求項1記載のインバータの回路方式。
2. A circuit system of an inverter according to claim 1, wherein a current transformer for detecting an alternating current is provided so that a plurality of alternating current lines whose other ends are connected to each other are common.
【請求項3】 半導体素子がIGBTトランジスタ等の
自己消弧素子であることを特徴とした請求項1又は2記
載のインバータの回路方式。
3. The circuit system of an inverter according to claim 1, wherein the semiconductor element is a self-turn-off element such as an IGBT transistor.
JP4229006A 1992-08-28 1992-08-28 Circuit system of inverter Pending JPH0678549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4229006A JPH0678549A (en) 1992-08-28 1992-08-28 Circuit system of inverter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4229006A JPH0678549A (en) 1992-08-28 1992-08-28 Circuit system of inverter

Publications (1)

Publication Number Publication Date
JPH0678549A true JPH0678549A (en) 1994-03-18

Family

ID=16885286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4229006A Pending JPH0678549A (en) 1992-08-28 1992-08-28 Circuit system of inverter

Country Status (1)

Country Link
JP (1) JPH0678549A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6208041B1 (en) 1998-09-11 2001-03-27 Mitsubishi Denki Kabushiki Kaisha Drive control device, module and combined module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6208041B1 (en) 1998-09-11 2001-03-27 Mitsubishi Denki Kabushiki Kaisha Drive control device, module and combined module

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