JPH0669470A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] A master substrate of a master slice type LSI is subjected to a slicing process to improve the degree of integration when a circuit requiring a resistance element is realized. [Structure] In a master substrate, a P-type diffusion region 1 and an N-type diffusion region 2 are provided on the substrate. Gate electrodes 3 made of polysilicon or the like are formed in an array on these. The resistance layer 4 is formed between the P-type diffusion region 1 and the N-type diffusion region 2, and the resistance layer 4 can be formed by the same material and the same process as the gate electrode 3. [Effect] When realizing a circuit that requires a resistive element,
In the slicing process, the resistance element can be formed of a resistance layer. Therefore, since it is not necessary to use the diffusion region as the diffusion resistance, the degree of integration is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a master structure of a master slice type LSI.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional master slice type L
1 shows a master substrate (master structure) of SI. A P-type diffusion region 1 and an N-type diffusion region 2 are arranged and formed in an array on a substrate. Further, gate electrodes 3 made of a polysilicon material or the like are alternately formed with P-type diffusion regions 1 and N-type diffusion regions 2 in an array.

In the slicing process, Al wiring is applied to the master substrate thus constructed to form a circuit.

[0004]

Since the conventional master substrate is constructed as described above, the diffusion resistance in the P-type diffusion region 1 and the N-type diffusion region 2 is used when the resistance element is required. However, if the diffusion resistance is used, there is a problem in that these diffusion regions are additionally required in addition to the diffusion region required for the transistor, and as a result, the degree of integration of the circuit is reduced.

This further allows the cell size to be increased, leading to the problem that the wiring to the cell in the next stage becomes long and the additional capacitance of the clock line increases.

The present invention has been made in order to solve the above problems, and an object thereof is to obtain a semiconductor device in a master slice type LSI which does not reduce the degree of circuit integration even when a resistance element is required. To do.

[0007]

According to another aspect of the present invention, there is provided a semiconductor device, in which a substrate and an array of first and second semiconductor regions formed on the substrate and having first and second conductivity types, respectively, are arranged. An array of first gate electrodes alternately formed with the first semiconductor regions in the same column as the array of the first semiconductor regions, and a second semiconductor region in the same column as the array of the second semiconductor regions. The arrangement of the second gate electrodes and the arrangement of the first and second semiconductor regions which are alternately formed are the first and the second.
And a resistance layer formed on the substrate separately from the arrangement of the gate electrodes.

Preferably, the resistance layer is formed in a region between the first semiconductor region array and the second semiconductor region array.

Also, preferably, a plurality of resistance layers are provided.

[0010]

The resistance layer in the present invention is used as a resistance element by wiring in the slicing process.

By forming the resistive layer in a region between the first semiconductor region array and the second semiconductor region array,
There is no reduction in the degree of integration.

By providing a plurality of resistance layers, these can be connected in series or in parallel to obtain a resistance element having a desired resistance value.

[0013]

EXAMPLES Example 1. A master substrate, which is an embodiment of the present invention, will be described below with reference to FIG. Figure 4
Similar to the conventional case shown in (1), the P-type diffusion regions 1 and the N-type diffusion regions 2 are formed in an array on the substrate. Further, gate electrodes 3 made of a polysilicon material or the like are alternately formed with P-type diffusion regions 1 and N-type diffusion regions 2 in an array.

A plurality of resistance layers 4 are formed in a region between the arrangement of the P type diffusion regions 1 and the arrangement of the N type diffusion regions 2.
Here, one gate electrode is provided for every four gate electrodes. Although the resistance layer 4 is formed in the master process, it may be formed separately from the gate electrode 3 or may be formed by the same material and the same process as the gate electrode 3.

FIG. 2 shows a ratio latch circuit as a circuit requiring a resistance element. This circuit requires the resistance element 5 as a feedback resistance. This ratio latch circuit is realized by subjecting the master substrate shown in FIG. 1 to a slicing process.

FIG. 3 shows how the ratio latch circuit shown in FIG. 2 is realized by providing wiring between the P-type diffusion region 1, the N-type diffusion region 2, the gate electrode 3 and the resistance layer 4 by the slicing process. . In the figure, black squares indicate connections in via holes and the like. Wiring 6 and 7 are VDD potential and G, respectively
Supply ND potential. Specifically, first, after arranging macro cells such as inverters, slice wiring for the resistance layer 4 is performed so that the overall circuit scale becomes as small as possible.

The present invention is not limited to the above ratio latch circuit, but can be applied to a circuit requiring a resistance element such as a flip-flop and a scan register.

Example 2. In addition, in the above embodiment, the resistance layer 4
Is provided for every four gate electrodes, but other ratios may be used. Further, it is also possible to form resistance elements having different values by forming resistance layers having different lengths on the master substrate. Furthermore, a plurality of resistance layers can be connected in series or in parallel to obtain a resistance element having a desired resistance value.

[0019]

As described above, according to the present invention, since the resistance layer is provided on the master substrate of the master slice type LSI, a circuit that requires a resistance element such as a latch, a flip-flop, or a scan register is provided. Even in the case of the configuration, it is not necessary to use the diffusion resistance of the diffusion region, and a semiconductor device with high integration can be obtained.

Further, since it is possible to avoid the increase of cells, the wiring between cells can be shortened and the wiring capacity can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view showing a structure of a master substrate according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a ratio latch circuit.

FIG. 3 is a plan view showing a configuration of a ratio latch circuit realized by subjecting a master substrate to a slicing process.

FIG. 4 is a plan view showing a structure of a conventional master substrate.

[Explanation of symbols]

 1 P-type diffusion region 2 N-type diffusion region 3 Gate electrode 4 Resistance layer

Claims (3)

[Claims] 1. A substrate, a respective array of first and second semiconductor regions formed on the substrate, each having first and second conductivity types, and an array of the first semiconductor regions. Arrangement of first gate electrodes formed alternately with the first semiconductor regions in the same row, and second gates formed alternately with the second semiconductor areas in the same row as the arrangement of the second semiconductor regions A semiconductor device comprising: an array of electrodes; and a resistance layer formed on the substrate so as to be isolated from the arrays of the first and second semiconductor regions and the arrays of the first and second gate electrodes. 2. The semiconductor device according to claim 1, wherein the resistance layer is formed in a region between the arrangement of the first semiconductor regions and the arrangement of the second semiconductor regions. 3. The resistance layer is provided in plurality.
The semiconductor device described.