JPH0666887B2 - Image reader - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading apparatus suitable for reading a document or the like in office equipment such as a facsimile and a copying machine.

“Conventional technology” In recent years, CCD (Ch
A large coupled device) image sensor has been developed.

FIG. 3 is a diagram showing the configuration of this type of image reading apparatus.
In this figure, 1 _-1 to 1- _n is a one-dimensional CCD image.
It is a sensor (line sensor) and these CCD images
The sensors _1-1 to 1- _n are arranged in a straight line, and the document reading unit R is configured thereby. Each CCD image sensor 1
_-1 to 1- _n are a photoelectric conversion unit composed of a row of photodiodes, a charge storage unit composed of a photo gate group provided corresponding to the photodiode group, and a charge storage unit. A photo transfer gate that collectively transfers the accumulated charges to the CCD analog shift register,
The CCD analog shift register for transferring the transferred accumulated charges to the output terminal. Then, the photo transfer gate is opened by a charge transfer pulse supplied from a drive circuit (not shown), and the accumulated voltage of each pixel is collectively transferred to the CCD analog shift register. Further, the charge in the CCD analog shift register is sent to the output end by the clock pulse supplied from the drive circuit, and the pixel signal (analog signal) transferred from the photodiode group is sequentially serialized as the output signal S1. Is output to.

Here, the output signal S1 of each CCD image sensor 1 _-1 to 1 _-n
, The upper limit is kept constant (4.5 to 6.5V) as shown in Fig. 4, and pixel signals (minimum 0.8V) are set downward based on this upper limit.
L ₁ , L ₂ , L ₃ ... have occurred. At the beginning of the one-line period, a dummy signal unrelated to reading is sent, and in this dummy signal, the light shielded pixel signal A output from the portion where the light receiving surface is shielded and light does not completely enter. Is included for 24 pixels. Then, after the dummy signal, the effective pixel signal B based on the reading of the original document is transmitted. In this case, the upper limit voltage level of the waveform of FIG. 4 varies for each CCD image sensor _1-1 to 1- _n , and each level L ₁ , L ₂ , ... Of the effective pixel signal B is directly converted to a digital signal. When converted, each CCD image sensor 1 _-1 to 1
There will be variations for each _−n .

Therefore, as shown in FIG. 3, each CCD image sensor 1 _-1
~ 1- _n , sample-hold circuit 3 _-1 ~ 3
_-N , differential amplifiers 4 _-1 to 4- _n , and A / D conversion circuit 5 _-1
.About.5- _n are provided. Each sample and hold circuit 3 _{-1 to} 3- _n is a CCD image sensor 1 _-1 to 1
The level Lr of the optical shield signal A in the output of _-n is used as a reference voltage to sample and hold, and the differential amplifiers 4 _-1 to 4 _-n are used to sample and hold circuits 3 _{-1 to} 3 respectively.
Reference voltage Lr output from _-n and each CCD image sensor 1
The levels L ₁ and L of the effective pixel signal B output from _-1 to 1 _-n
It is the difference between ₂ and ... And each differential amplifier 4
The outputs of the _-1 to 4- _n are converted into digital signals by the A / D conversion circuits _{5-1 to} 5- _n , respectively, and the bus buffer 6
_-1 to 1- _n is output to the bus line and image-processed by the computer. In this case, the switching circuit 7 for sequentially supplying selection signals to each bus buffer 6 _-1 to 6 _-n is provided, the selection signal supplied from the bus buffer 6 _-1 to 6 _-n is switching circuit 7 If it is, the image signal output from the a / D converter circuit 5 _-1 to 5 _-n is adapted to respectively output to the bus line.

[Problems to be Solved by the Invention] By the way, in the above-described conventional image reading apparatus, the sample and hold circuits 3 _{−1 to} 3 _−n and the differential amplifier _4-1 to
4- _n , A / D conversion circuits 5 _{-1 to} 5 _-n , and bus buffers 6 _{-1 to} 6 _-n are CCD image sensors 1 _-1 to 1 _-n.
It was configured to be provided in the same number as. However, the differential amplifiers _4-1 to 4- _n and the A / D conversion circuits _{5-1 to} 5 are used.
_-N is generally an expensive IC, so CC
As the number of D image sensors _1-1 to 1- _n increases, the cost of the image reading apparatus increases.

This invention was made in view of the above-mentioned circumstances, and CCD
An object of the present invention is to provide an image reading device that can be configured at low cost even when the number of image sensors is large.

[Means for Solving Problems] A reading unit constituted by a plurality of CCD image sensors and a predetermined number of CCDs provided for each of the plurality of CCD image sensors. Of the signals output from the image sensor, a predetermined number of delay circuits for delaying each of the signals by a half cycle, and a plurality of CCD image sensors are provided corresponding to each of the delay circuits. A plurality of sample and hold circuits for extracting and holding reference signals from the signals output from the CCD image sensor and each of the predetermined number of delay circuits, and a CCD image sensor other than the predetermined number Also, among the signals output from each of the predetermined number of delay circuits, each signal indicating a pixel signal and the sample / hold circuit holds the signal. Selecting means for sequentially selecting the reference signal in time division,
A differential amplifier that takes each difference between the output of the CCD image sensor selected by the selection means and the outputs of the plurality of sample and hold circuits, and an A / D that converts the output of the differential amplifier into a digital signal. And a conversion circuit.

"Operation" The output of each CCD image sensor and the output of the sample and hold circuit are supplied to one differential amplifier by the selection means, and the output of this differential amplifier is converted into a digital signal by one A / D converter. It

Therefore, even if the number of CCD image sensors is large, it is possible to configure with a single differential amplifier and A / D converter, and obtain a digital signal with uniform conversion characteristics. Further, at this time, since only the pixel signal is supplied to the differential amplifier and the A / D converter, a digital signal with less noise can be obtained.

Further, rather than sequentially switching the output signals of a plurality of CCD image sensors within the period corresponding to the pixel signal, that is, sequentially switching without delay, the switching time of the selection means and the conversion time of the A / D conversion circuit Can be doubled.

Therefore, it is possible to use the one having the lowest maximum frequency, which can reduce the cost and simplify the peripheral circuit.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and the portions corresponding to the respective portions in FIG. 3 are designated by the same reference numerals.

In the figure, reference numeral 12 is an analog multiplexer, which sequentially selects the signals of the following groups (1) to (4) described below based on the selection signal supplied from the switching circuit 11 and supplies the signals to the differential amplifier 4. That is, the analog multiplexer 12 includes a pair of attenuator 8 _-1 CCD image sensor 1 is supplied through a _-1 output signal S1 and the sample and hold circuit 3 _-1 of the output signal S2, the attenuator 8 _- the output signal S1 of the CCD image sensor 1 _-2 supplied via the ₂ and sample
The set of output signals S2 of the hold circuit 3 _-2 and the CCD supplied via the attenuator 8 _-3 and the analog delay circuit 10 _-3.
A set of image sensor 1 _-3 of the output signal S1 and the sample and hold circuit 3 _-3 of the output signal S2, CCD image sensor 1 is supplied through an attenuator _8-4 and analog delay circuit _{10-4 -4} output signal S1 and sample and hold circuit 3
One of the four sets of the output signal S2 of _-4 is sequentially selected and supplied to the differential amplifier 4. In this case, the analog delay circuits 10 _-3 and 10 _-4 are the CCD image sensor 1 supplied via attenuators 8 _-3 and 8 _-4 , respectively.
_-3 and 1 _-4 respective output signals S1 is to time delays 333 _nsec. This 333 _nsec period is a time period corresponding to a half cycle of each output signal S1. Further, each CCD image sensor 1 _-1 to _1-4 outputs an output signal S1 in synchronization with a clock pulse supplied from a drive circuit (not shown), and the clock pulse is supplied to the switching circuit 11 Is also being supplied to.

CCD image sensor 1 _-1 and 1
Each output signal S1 _-2 attenuators _28-1 and _8-2 via respectively supplied to the analog multiplexer 12, and each output signal S1 of the CCD image sensor 1 _-3 and 1 _-4, attenuated Bowl 8
_-1 and 8 _-2 respectively, and further delayed by 333 _nsec by the analog delay circuits 10 _-3 and 10 _-4 and supplied to the analog multiplexer 12. The time relationship between the output signals S1 supplied to the analog multiplexer 12 is shown in FIGS. 2 (A) to 2 (D). That is, the pixel signal L _n, L _{n + 1} of the CCD image sensor 1 _-3 and 1 _-4 respective output signals _S1, ... (n is an integer)
Is the output signal S1 of each of the CCD image sensors 1 _-1 and 1 _-2.
Of the pixel signals L _n , L _{n + 1} , ... Of 333 _nsec ,
In other words, it is supplied to the analog multiplexer 12 after being delayed by the reset noise period Tr. Then, the analog multiplexer 12 operates as follows based on the selection signal supplied from the switching circuit 11.

Period T ₁ shown in Fig. 2 (a), that is, CCD image
In the period corresponding to the beginning 83 _nsec of the pixel signal L _n of the output signal S1 of the sensor 1 _-1 , this CCD image sensor 1 _-1
Output signal S1 and the sample and hold circuit 3 _-1 output signal S
2 is supplied to the differential amplifier 4.

Period T ₂ shown in Figure 2 (b), that is, CCD image
The end of the pixel signal L _n of the output signal S1 of the sensor 1 _-2 83 _nsec
The CCD image sensor 1
The output signal S1 of _{-2 and} the output signal S2 of the sample and hold circuit 3 _-2 are supplied to the differential amplifier 4.

Period T ₃ shown in Figure 2 (c), that is, CCD image
In the period corresponding to the beginning 83 _nsec pixel signal L _n of the output signal S1 of the sensor 1 _-3, the CCD image sensor 1 _-3
Output signal S1 and the sample and hold circuit 3 _-3 output signal S
2 is supplied to the differential amplifier 4.

Period T ₄ shown in Figure 2 (d), that is, CCD image
End of pixel signal L _n of output signal S1 of sensor 1 _-4 83 _nsec
The CCD image sensor 1
The output signal S1 and the output signal S2 of the sample and hold circuit 3 _{-4 -4} supplied to a differential amplifier 4.

In this manner, one cycle of the output signal S1, 666 within a period of _nsec, the output signal S1 of the four CCD image sensors 1 _-1 to 1 _-4 and sample and hold circuit 3 _-1 -3 _{- 4} , each output signal
The set of S2 is sequentially supplied to the differential amplifier 4.

[Advantages of the Invention] As described above, according to the present invention, a plurality of CCDs are provided.
A reading unit constituted by an image sensor, and a signal among signals output from each of the predetermined CCD image sensors provided for each of the predetermined CCD image sensors. A predetermined number of delay circuits for delaying each half cycle, and a CCD image sensor other than the predetermined number and a predetermined number of delay circuits provided corresponding to each of the plurality of CCD image sensors. Of the output signals,
A plurality of sample and hold circuits for respectively extracting and holding reference signals, CCD image sensors excluding the predetermined number, and each of the predetermined number of delay circuits indicating a pixel signal among the signals output from each of the delay circuits. Selecting means for sequentially selecting the signal and the reference signal held by the sample-hold circuit by time division, the output of the CCD image sensor selected by the selecting means, and the plurality of sample-hold circuits Since a differential amplifier that takes each difference from the output of the differential amplifier and an A / D conversion circuit that converts the output of the differential amplifier into a digital signal are provided, the CCD image
Even when the number of sensors is large, it is possible to configure with a single differential amplifier and A / D converter, and it is possible to obtain a digital signal with uniform characteristics during conversion. Further, at this time, since only the pixel signal is supplied to the differential amplifier and the A / D converter, a digital signal with less noise can be obtained.

Further, rather than sequentially switching the output signals of a plurality of CCD image sensors within a period corresponding to the pixel signal, that is, rather than sequentially switching without delay, the switching time of the selection means and the conversion time of the A / D conversion circuit. Can be doubled. Therefore, it is possible to use those having the lowest maximum frequency, and it is possible to obtain the effects of cost reduction and simplification of peripheral circuits.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention,
2 (a) to (d) are timing charts for explaining the operation of the embodiment, FIG. 3 is a block diagram showing the configuration of a conventional image reading apparatus, and FIG. 4 is a CCD in the image reading apparatus. It is a figure which shows the output signal of an image sensor. R: original reading unit, 1 _-1 to 1 _-4 ... CCD image sensor, 3 _{-1 to} 3 _-4 ... sample and hold circuit, 4 ... differential amplifier, 5 ... A / D conversion circuit , 10 _-3 to 10 _-4 ... analog delay circuit, 11 ... switching circuit, 12 ... analog
Multiplexer (selection means).

Claims (2)

[Claims] 1. A reading unit composed of a plurality of CCD image sensors, and a reading unit provided for each of a predetermined number of the plurality of CCD image sensors. Of the output signals, a predetermined number of delay circuits for delaying each of the signals by a half cycle, and a plurality of CCD image sensors provided corresponding to the plurality of CCD image sensors, respectively, and Of the signals output from each of the predetermined number of delay circuits, a plurality of sample and hold circuits that respectively extract and hold a reference signal, a CCD image sensor other than the predetermined number, and the predetermined number of sample and hold circuits. Of the signals output from each of the delay circuits, each signal indicating a pixel signal, and the reference signal held by the sample and hold circuit Selecting means for sequentially selecting in time division; a differential amplifier for taking each difference between the outputs of the CCD image sensor selected by the selecting means and the outputs of the plurality of sample and hold circuits; A / D that converts output to digital signal
An image reading apparatus comprising: a conversion circuit. 2. The number of the CCD image sensor and the number of the sample and hold circuits are "4", respectively, and the first to fourth CCD image sensors and the first to fourth CCD image sensors are respectively provided.
A fourth sample-and-hold circuit, the number of the delay circuits is “2”, and the first and second delay circuits are respectively provided, and the selecting means includes the first and second CCD image
The signals output from the sensor and each of the first and second delay circuits and the outputs of the first to fourth sample and hold circuits are converted into a pixel signal of the output signals of the first CCD image sensor. Of the output signal of the second CCD image sensor from the beginning to the predetermined time before the end of the pixel signal of the second CCD image sensor through the first delay circuit. From the beginning of the pixel signal of the output signal to the lapse of a predetermined time, and from the end of the pixel signal of the output signal of the fourth CCD image sensor output via the second delay circuit to the time before the predetermined time. The image reading device according to claim 1, wherein the image reading device is selected sequentially in each period.