JPH066535A - Image forming device - Google Patents

Abstract

PURPOSE:To implement horizontal synchronization control and screen corner control without use of a high frequency clock and a high speed device. CONSTITUTION:An F/I converter 31 of a triangle wave VCO 23 converts a frequency of an input clock CLK into a current I, a current from current sources 32, 33 is converted into a value relating to the frequency of the input clock CLK by the F/I converter 31 and a selector 34 is switched for each half period of the input clock CLK and then, a triangle wave synchronously with a picture clock is generated. Then one of eight phi clocks whose phases differ is selected based on the triangle wave and the selected clock is used for the picture clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus.

[0002]

2. Description of the Related Art In recent years, laser beam printers have attracted attention because of their quietness, high-speed printing, and high-quality printing. In the case of color printing, a series of steps of scanning a light beam on the photoconductor to perform the first development and then transferring to the recording paper is performed for each toner color (yellow, magenta,
Recording is performed by repeating each time for cyan and black. The image signal is expressed in gradation by changing the light emitting area of the light beam by performing pulse width modulation to realize full color printing. By the way, in the conventional printer, when the cycle on the paper is slightly shifted between the colors due to various scanning unevenness, paper feeding speed unevenness, paper expansion, etc., moire with a coarse pitch occurs and density unevenness and color unevenness occur. Conspicuous,
Since the image quality is greatly reduced, as shown in FIG. 12, the printing position is shifted for each line to form a screen angle,
As shown in FIG. 11A, the printing positions of the black color toner and the other color toners are shifted. Alternatively, FIG. 11 (b)
As described above, by shifting the printing position for each toner color and averaging the toner overlap, the above-mentioned problems are reduced.

Many monochrome printers that print halftones also have a screen angle in order to reduce uneven density. FIG. 13 is a circuit for controlling the screen angle and horizontal synchronization in a conventional printer. In the printer shown in the figure, in order to realize a small screen angle (tan (1/8)) and fine screen angle control, or to set the horizontal synchronization accuracy to 1/8 or more of the pixel clock (VCLK), the pixel 8 times the clock (8V
CLK).

In FIG. 13, a D flip-flop 53 is provided.
Reference numerals 1 to 539 configure a shift register that shifts the horizontal synchronizing signal BD by 8VCLK. Further, the AND circuits 540 to 547 are edge detection circuits of the horizontal synchronizing signal BD, and each have a time difference of 8 VCLK. Then, in the 1of8 selector 548, the AND circuits 540 to 540 are generated according to the screen angle selection signal SCREEN.
One of the outputs of 547 is selected, which resets the divide-by-8 circuit 550 by the signal inverted by the inverter circuit 549. This divide-by-8 circuit divides 8VCLK by 8 to generate a pixel clock VCLK. In the printer having the above configuration, horizontal synchronization accuracy is 1/8 or more (human visual detection limit or less), and fine screen angle control in tan (1/8) increments is performed.

[0005]

However, as described above, in the conventional printer, the clock that is eight times the image clock is used to obtain the required horizontal synchronization accuracy and screen angle. For example, in a color printer with 600 DPI and two sheets, the image clock is about 20 MHz, and a frequency that is eight times as high as that, that is, a high frequency clock of 160 MHz is required. Therefore, expensive crystal oscillators and EC
There is a problem that fine screen angle control cannot be realized unless the L device is used. In addition, handling a high frequency clock causes a large amount of unnecessary radiation noise from the device.

[0006]

The present invention has been made for the purpose of solving the above-mentioned problems, and has the following structure as one means for solving the above-mentioned problems. That is, in an image forming apparatus that forms an electrostatic latent image on a recording medium and performs scanning for visualizing the electrostatic latent image based on a horizontal synchronizing signal, a clock that generates a plurality of clocks with different phases. Generating means, clock holding means for holding the clock in synchronization with the horizontal synchronizing signal, means for instructing a screen angle, the clock held by the clock holding means and the screen angle based on the Means for selecting one of the plurality of clocks.
Preferably, the clock generating means further includes a triangular wave generating means, a means for generating a plurality of different reference levels in synchronization with the level of the triangular wave from the triangular wave generating means, and the reference level and the triangular wave. Means for comparing, and clocks having different phases are generated based on the comparison.

[0007]

In the above structure, the horizontal synchronization control and the screen angle control are performed without using a high frequency clock or a high speed device.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. [First Embodiment] A first embodiment according to the present invention will be described. FIG. 1 is a configuration diagram of a color laser beam printer as an image processing apparatus according to this embodiment. Here, the operation of multicolor printing in the color laser beam printer will be described with reference to FIG. In FIG. 1, a photosensitive drum 501 rotating in a direction indicated by an arrow at a predetermined speed is
The charger 504 charges the battery to a predetermined polarity and voltage value. Next, the recording paper P is fed one by one from the paper feed cassette 515 by the paper feed roller 514 at a predetermined timing. When the detector 190 detects the leading edge of the paper, the laser light L modulated by the image signal VDO is emitted from the semiconductor laser 120 toward the polygon mirror 507, and the laser light L is scanned by the polygon mirror 507. Then, the light is guided onto the photoconductor drum 501 via the lens 508 and the mirror 509.

A signal TOP from a detector 190 arranged at one end of the optical scanning is a vertical synchronizing signal T indicating the leading edge of the recording paper.
It is output to the image forming apparatus (not shown) as OP. Similarly, when the laser light L is incident on the detector 200, a beam detect signal (hereinafter, referred to as a BD signal) which is a horizontal synchronizing signal is output. Further, the image signal VDO is sequentially sent to the semiconductor laser 120 in synchronization with the TOP signal and the BD signal, and the photosensitive drum 501 is scanned and exposed. Then, the first electrostatic latent image is developed by the developing device 503Y,
A yellow first toner image is formed on the photosensitive drum 501. A transfer bias voltage having a polarity opposite to that of the toner is applied to the transfer drum 516 immediately before the front end of the recording paper P fed at a predetermined timing reaches the transfer start position.
At the same time that the first toner image is transferred onto the recording paper P, the recording paper P is electrostatically attracted to the surface of the transfer drum 516. next,
When the second electrostatic latent image is formed on the photosensitive drum 501 by scanning with the laser light L and the second electrostatic latent image is developed by the developing device 503M, the magenta second toner is formed on the photosensitive drum 501. An image is formed. Then, by the TOP signal, the second toner image is transferred onto the recording paper P in alignment with the position of the first toner image previously transferred onto the recording paper P.

Similarly, when the third electrostatic latent image is formed and developed by the developing device 503C, the cyan toner image is transferred onto the recording paper P in alignment with it. Next, when the fourth electrostatic latent image is formed and developed by the developing device 503K, the black toner image is transferred in alignment with the recording paper P. In this way, the VDO signal for one page is sequentially output for each process.
The toner image which is output to the semiconductor laser 120 and which has not been transferred in each transfer process is wiped off by the cleaner 510. When the front end of the transferred recording paper P approaches the position of the separation claw 512, the separation claw 512 contacts the surface of the transfer drum 516, and the recording paper P is separated from the transfer drum 516. The separation claw 512 returns to the original position when the rear end of the recording paper P separates from the transfer drum 516. At that time, the charger 5
The accumulated charge on the recording paper P is eliminated by 11 and the separation claw 5
The separation of the recording paper P by 12 is facilitated and the air discharge at the time of separation is reduced.

FIG. 2 is a block diagram showing the arrangement of the image processing apparatus according to this embodiment. In the figure, 1 is a host computer that sends an image code, 2 is an image forming unit that forms image data based on the image code sent from the host computer 1, and 3 is based on image data sent from the image forming unit 2. An image printing unit that prints an image, and 4 is a color printer including an image forming unit 2 and an image printing unit 3. Further, an RGB → YMCK converter 5 is a YMCK that uses RGB colors as toner colors. Converting to color, 6 is a selector for selecting a color to be printed from the converted YMCK colors, 7 is a buffer memory for adjusting time timing, 8 is a γ conversion table, and 9 is based on the output of the γ conversion table. A PWM modulation circuit 10 for performing pulse width modulation, a PWM modulation circuit 9 and a selector 1 for selecting an output of a parallel-to-serial conversion circuit 18 which will be described later. Reference numeral 1 is a laser driver, 12 is a semiconductor laser, 13 is a black detection circuit, 14 is a white detection circuit, and 15 and 16 are AND circuits. Reference numeral 17 is a smoothing circuit for improving the image quality of a text image, 18 is a parallel-to-serial conversion circuit for converting parallel data output of the smoothing circuit into serial data, 19 is a vertical sync detector for detecting vertical sync timing, and 20 is horizontal sync. A horizontal sync detector for detecting timing, 21 is a 2BI for counting the vertical sync signal TOP
A color selection circuit configured by a T counter to select a print toner color, 22 is an oscillator that outputs the same frequency as the image clock, 23 is a triangular wave VCO that generates a triangular wave in synchronization with the clock of the oscillator 22, 24 Is a screen angle selection circuit for selecting a screen angle, and 25 is an image clock generation circuit for generating an image clock VCLK with a phase shift corresponding to the screen angle designated by the timing control circuit 21 with a predetermined horizontal synchronization accuracy.

The host computer 1 sends the image code to the color printer 4. And the color printer 4
Then, the image forming section 2 forms an image code of multi-valued RGB color image data and sends it to the image printing section 3. The image printing unit 3 converts the RGB color image data sent from the image forming unit 2 into a YMCK color which is a toner color by an RGB → YMCK converter 5 and performs printing. Here, since the RGB → YMCK conversion is performed every time YMCK is printed, the image forming unit 2 converts the image data of RGB colors into YMCK.
It is sent every time K is printed. The YMCK color data output from the RGB → YMCK converter 5 is selected by the selector 6 as the color data of the current printing process and becomes the address input of the γ conversion table 8 which is the SRAM via the buffer memory 7. . The buffer memory 7 corrects a time delay of several lines generated in a smoothing circuit 17 described later, and the other address input terminals of the γ conversion table 8 are connected to the TEXT signal from the image forming unit 2 and the color selection circuit 21. COLOR signal is input.

The TEXT signal is a control signal indicating whether the RGB image data is a character or a graphic or a natural image. In the PWM circuit described later, when image data is a character, low-gradation but high-resolution PWM processing is performed. On the other hand, in the case of a natural image, low-resolution but high-gradation PWM processing is performed. The γ characteristics are different. Further, due to the difference in color toner and the difference in human visual characteristics with respect to color, the γ characteristic also differs depending on the toner color. Therefore, the γ conversion table 8 is switched to perform optimum γ conversion for each. The PWM modulation circuit 9 performs pulse width modulation based on the γ-converted 8BIT color data, and sends it to the selector 10. In addition, the parallel-to-serial conversion circuit 1 is connected to the other input terminal of the selector 10.
8 outputs are connected. This signal is a signal obtained by improving the image quality of binary characters, and the generation process thereof will be described. Further, the black detection circuit 13 is a 24-input NAND circuit, and detects R, G, and B color data of all 00 _H , that is, zero brightness. And the AND circuit 15
Is to detect the binary black (BK) by taking the logical product of the output of the black detection circuit 13 and the TEXT signal. The white detection circuit 14 is a 24-input AND circuit,
R, G, and B color data are all FF _H , that is, the maximum luminance is detected.

The AND circuit 16 calculates the logical product of the output of the white detection circuit 14 and the TEXT signal and outputs the binary character white (W
H) is detected. Further, the smoothing circuit 17 finely divides the pixels in the main scanning direction into eight, based on the black (BK) and white (WH) patterns of the target pixel and its surrounding pixels, and smoothes the edge portion of the character or figure. The pattern of 8 divisions is output corresponding to each bit of 8 bits. The 8-bit parallel data PDT is serial-converted by the parallel-to-serial conversion circuit 18 and input to the selector 10. The P / T signal from the smoothing circuit 17 is the PW output from the PWM modulation circuit 9.
The VDO signal selected by the selector 10 is a control signal for selecting the M modulation signal and the smoothing processing signal, and is amplified by the laser driver 11 and printed by the semiconductor laser 12. Next, the generation of the image clock in the image processing apparatus according to the present embodiment will be described. FIG. 3 is a detailed block diagram of the image clock generation unit in the image processing apparatus according to the present embodiment. In the figure, 31 is an F / I converter that converts the input clock frequency into a current value, and 32 and 33 are
A current source for generating a current based on an F / I converter, 34 a selector, 35 a capacitor, 36 a triangular wave VCO2
S / H circuit that samples / holds the maximum voltage value of 3
37 is an inverter that inverts the input clock, and 38
Is an S / H circuit for sampling / holding the lowest voltage value of the triangular wave VCO 23; 39-42 are voltage adders for mixing the voltage divided by the resistor R and the output of the S / H circuit 38;
3 to 46 are the output of the triangular wave VCO 23 and the voltage adder 39.
Comparing the outputs of .about.42 with 47, and 47 is an 8 .phi. Clock generator for generating 8 clocks with different phases from the outputs of the comparators 43-46.

Reference numeral 48 is a 1of8 selector for selecting one of the signals from the 8φ clock generator 47, 49 is an 8 bit D flip-flop for latching the 8φ clock with the horizontal synchronizing signal BD, and 50 is a D flip-flop 49. 8
A code converter for converting a bit output to 3 bits, 51
Is the output of the code converter 50 and the screen angle selection signal S
Digital adder for adding with CREEN, 52 is 8φ
Code converter that converts clock to 3-bit code, 5
3 is an 8-bit D flip-flop that latches the output data from the smoothing circuit (reference numeral 17 in FIG. 2) with the image clock VCLK selected by the 1of8 selector 48, and 54 corresponds to the output of the code converter 52. It is a 1of8 selector that selects the output of the D flip-flop 53. The F / I converter 31 performs conversion into a current value I corresponding to the frequency of the input clock CLK, and the current source 3
The F / I converter 31 sets the current values of 2 and 33 to values relative to the frequency of the input clock CLK.
These current sources 32 and 33 are connected to the input terminals of the selector 34, and the selector 34 is switched every half cycle of the input CLK. Further, since the capacitor 35 is connected to the output terminal of the selector 34, CLK is a logic Hi.
In the half cycle of gh, the current of the current value I flows from the current source 32 into the capacitor 35, and in the half cycle of the logic low of CLK, the current of the current value 33 from the current source 33 is the capacitor 35.
Drained from. Here, by this operation, a triangular wave synchronized with the oscillation clock CLK of the crystal oscillator 22 (see FIG. 2) that oscillates at the frequency of the image clock is generated.

The reason why the current values of the current sources 32 and 33 are set to the current value I relative to the frequency of the input clock CLK is to obtain the maximum dynamic range even in the system in which the input clock is changed. Triangular wave VC
The triangular wave generated at O23 is input to the positive terminals of the comparators 43 to 46 as described above, and is sampled / held by the S / H circuits 36 and 38. Since the sampling pulse of the S / H circuit 36 is the rising edge of the CLK signal, the maximum voltage value of the triangular wave is sampled when the current is completely injected into the capacitor 35.
On the other hand, the sampling pulse of the S / H circuit 38 is CLK
Since it is the falling edge of, the minimum voltage value of the triangular wave is sampled when the discharge of the current from the capacitor 35 is finished. An adder 39 that divides the voltage between the minimum voltage value and the maximum voltage value of the triangular wave by five resistors having the same resistance value R and adds the voltage to the minimum voltage value of the triangular wave, respectively.
~ 42. This makes it possible to construct a voltage divider that always follows the level of the triangular wave. FIG. 4 is an operation timing chart of the image clock generation unit.
b, c, and d are outputs obtained by comparing the outputs of the adders 39 to 42 and the triangular wave with the comparators 43 to 46. Further, FIG. 5 shows the output signals a, / of the comparators 43 to 46.
It is a block diagram of an 8φ clock generator 47 that generates eight clock pulses φ0-φ7 having different phases from a, b, / b, c / c, d, / d.

In FIG. 5, reference numerals 64-71 are edge input type SR latches. For example, the SR latch 64 is
It is composed of D flip-flops 61 and 62 and an inverter 63. In FIG. 5, the signal / a which is the inverted signal of the signal a
Rising (falling of the signal a in FIG. 4), the Q output of the D flip-flop 61 becomes "1". After that, since the Q output of the D flip-flop 62 becomes "1" at the rising edge of the signal d, the signal resets the D flip-flops 61 and 62 via the inverter 63. By this operation, the φ0 clock is generated (see FIG. 4). Similarly, φ1-φ7 are generated in the SR latches 65 to 71, and as a result, clocks having different phases shown in FIG. 4 are generated. In the D flip-flop 49 (see FIG. 3), the above φ0 is generated at the rising timing of the horizontal synchronizing signal BD.
-Φ7 is latched (see φLatch shown in FIG. 4),
Code conversion is performed according to the selection logic table shown in FIG. 6 (see φCode in FIG. 4). Further, in the adder 51, the output signals SCREEN and φCode from the screen angle selection circuit 24 are added (Screen, φS in FIG. 4).
(See el). The 1of8 selector 48 selects a clock with the logic shown in FIG.

Next, the operation of the parallel / serial converter 18 using φ0-φ7 will be described. Parallel data PDT for smoothing generated by the smoothing circuit 17
Is latched by the D flip-flop 53 with the image clock VCLK, and each bit is selected by the 1of8 selector 54 in the next stage. The control clock of the 1of8 selector 54 is connected to the output clocks φ0-φ7 of the 8φ clock generator 47.
The output of the code converter 52 for converting into a code as shown in FIG. In addition, in FIG.
This shows the selection logic of the of8 selector 54, and φ
Since 0-φ7 takes all the states shown in FIG. 6 within one pixel clock as shown in FIG. 4, a shift register operation for shifting 8-bit data within one pixel can be performed. As described above, according to this embodiment, one clock is selected from a plurality of clocks having different phases,
By using it as an image clock, horizontal synchronization control and screen angle control can be performed without using a high-frequency clock or high-speed device, and stable and high-quality images can be obtained without character deviation, density unevenness, color unevenness, or color bleeding. There is an effect that can be. In addition, parallel / serial conversion can be performed without using a high-frequency clock or a high-speed device by sequentially selecting parallel data representing divided dot patterns in one pixel based on a plurality of clock outputs having different phases, which is inexpensive. A high-quality image with smooth edges of characters can be obtained by the device. Note that it is possible to minimize the influence of changes in the surrounding environment, changes over time, etc. by performing self-calibration processing on the different phase clock generators.

[Second Embodiment] In the above first embodiment,
A triangular wave synchronized with a clock having the same frequency as the image clock is generated, and eight clocks having different phases are generated based on the triangular wave to perform horizontal synchronization, screen angle control, and parallel / serial conversion. In this embodiment, eight clocks having different phases are created by using delay elements, and horizontal synchronization, screen angle control, and parallel / serial conversion are performed. FIG. 9 is a block diagram of an image clock generator according to the second embodiment. The image processing apparatus according to this embodiment is the same as the image processing apparatus according to the first embodiment shown in FIG. 2, except that the triangular wave VCO 23 and the image clock generation unit 25 are replaced with the image clock generation unit shown in FIG. It is a thing.

In FIG. 9, reference numeral 147 denotes 8 having different phases.
8φ clock generator that generates two clocks, 148 is a selector, 150 is a code converter that converts the state of the 8 output clocks of the 8φ clock generator into a 3-bit code, 151 is a bit adder, and 180 to 186 are , A delay element that delays the input clock by 1/8 of that time,
187 is a 3-bit D flip-flop. The CLK signal of FIG. 9 is a clock generated by the crystal oscillator 21 (see FIG. 2) as in the first embodiment, and is input to the selector 148 as φ0 and is also supplied to the delay element circuit 180. It This delay element circuit 1
The output φ1 of 80 is CLK (φ0) delayed by time τ (see signal φ1 in FIG. 10), and time τ is
This corresponds to 1/8 of the time of the input clock CLK. Similarly, the time τ is integrated to obtain φ2-φ7 (see FIG. 10).

The code converter 150 uses the same logic as that shown in FIG. 6 to convert into a 3-bit φ code based on φ0-φ7 (see the output of the code conversion 150 in FIG. 10). This φ code is latched by the D flip-flop 187 at the timing of the horizontal synchronizing signal BD. For example, at the timing shown in FIG. 10, (φ0 to φ7) =
(0,1,1,1,1,0,0,0,), that is,
(Φ code) = (100) is latched. On the other hand, similarly to the first embodiment, the screen angle control signal SCREEN and the bit addition from the D flip-flop 187 are performed by the adder 151, and the result is used as the control signal of the selector 148. The selector 148 selects a clock with the logic shown in FIG. 7 (see the adder 151 output and the selector 148 output in FIG. 10). The parallel / serial converter according to the present embodiment also has the same configuration as that of the first embodiment, and performs parallel / serial conversion using φ0-φ7 clocks. In this way, by using the delay circuit to generate the 8φ clocks having different phases, the configuration of the image clock generating unit can be simplified. The present invention may be applied to a system including a plurality of devices or an apparatus including one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0022]

As described above, according to the present invention,
By selecting one of a plurality of clocks with different phases and using that clock as an image clock, horizontal synchronization control and screen angle control can be performed without using a high frequency clock or a high speed device, and as a result, a stable high There is an effect that a high quality image can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a color laser beam printer as an image processing apparatus according to a first embodiment.

FIG. 2 is a block diagram showing a configuration of an image processing apparatus according to an embodiment.

FIG. 3 is a detailed block diagram of an image clock generation unit in the image processing apparatus according to the embodiment.

FIG. 4 is an operation timing chart of the image clock generation unit.

FIG. 5 is an 8φ clock generator 47 that generates clock pulses φ0-φ7 from output signals of comparators 43 to 46.
It is a block diagram of.

FIG. 6 is a selection logic table relating to a D flip-flop 49.

FIG. 7 is a selection logic table relating to a 1of8 selector 48.

8 is a diagram showing selection logic of a 1of8 selector 54. FIG.

FIG. 9 is a block diagram of an image clock generation unit according to a second embodiment.

FIG. 10 is a timing chart of the image clock generator according to the second embodiment.

FIG. 11 is a diagram showing a state where the print positions of black color toner and other color toners are shifted in a normal printer.

FIG. 12 is a diagram showing a state in which a printing position is shifted and a screen angle is added to each line in the printer.

FIG. 13 is a circuit for controlling a screen angle and horizontal synchronization in a conventional printer.

[Explanation of symbols]

 1 Host Computer 2 Image Forming Section 3 Image Printing Section 4 Color Printer 5 RGB → YMCK Converter 6, 10 Selector 7 Buffer Memory 8 γ Conversion Table 9 PWM Modulation Circuit 11 Laser Driver 12 Semiconductor Laser 13 Black Detection Circuit 14 White Detection Circuit 15 , 16 AND circuit 17 Smoothing circuit 18 Parallel-to-serial conversion circuit 19 Vertical sync detector 20 Horizontal sync detector 21 Color selection circuit 22 Oscillator 23 Triangular wave VCO 24 Screen angle selection circuit 25 Image clock generation circuit

Claims (4)

[Claims] 1. An image forming apparatus for forming an electrostatic latent image on a recording medium and performing scanning for visualizing the electrostatic latent image based on a horizontal synchronizing signal, wherein a plurality of clocks having different phases are used. Based on the clock generating means for generating, the clock holding means for holding the clock in synchronization with the horizontal synchronizing signal, the means for instructing the screen angle, the clock held by the clock holding means and the screen angle And a means for selecting one of the plurality of clocks. 2. The clock generating means further comprises: triangular wave generating means; means for generating a plurality of different reference levels in synchronization with the level of the triangular wave from the triangular wave generating means; and the reference level and the triangular wave. 2. The image forming apparatus according to claim 1, further comprising: a unit configured to compare with each other, and generating clocks having different phases based on the comparison. 3. The image forming apparatus according to claim 1, wherein the clock generating unit generates a plurality of clocks having different phases by delaying the input clock with a plurality of delay circuits. 4. A means for dividing one pixel into a plurality of dots and outputting data representing a blinking pattern of a light beam corresponding to the divided dots in the one pixel, and a means for outputting the data based on the plurality of clocks. The image forming apparatus according to claim 1, further comprising: a unit that sequentially selects data, wherein the selected data is a signal of the light beam.