JPH06511099A - How to perform disk array operations using a non-uniform stripe size mapping scheme - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Performing disk array operations using a non-uniform disk drive size mapping scheme Technological field The present invention provides performance improvements for multiple disk drives in computer systems. In particular, using parity data redundancy and recovery protection features , relates to a method for performing write operations on a disk array.

Background technology In recent years, microprocessors and computers that utilize disks have increasingly become It's becoming even more powerful. The computers currently available are from 10 years ago. It has performance that exceeds that of frame and minicomputers. 32-bit width Microprocessor data buses have become widely available, whereas in the past 16 bits became the norm.

Personal computer systems have evolved over the years and new uses are discovered every day. . Usage changes and this results in different services forming a complete computer system. There are different requirements for different systems. Due to the increased performance of computer systems A mass storage subsystem, such as a fixed disk drive, is a computer system's It has become clear that they will play an increasingly important role in the transfer of data. past few years smell A new feature in the storage subsystem, referred to as the disk array subsystem. New trends have emerged to improve data transfer performance, capacity and reliability. Di One reason for establishing a disk array subsystem is to have a logic with very high data transfer rates. The goal is to create a logical device. This allows multiple standard disk drives to be interconnected. By "grouping" these drives and transferring the data sent and received from these drives in parallel, can be achieved. Therefore, the data is stored in the data file where each disk has a data file. is stored across each disk in the disk array to have a portion of .

If n drives are grouped together, the effective data transfer rate can be increased by a factor of n. It can increase. This technique is known as striping, and is used to remove large amounts of traffic to and from secondary storage. It was first adopted in hyper-computing environments where data transfer is frequently required.

In this stripe, consecutive data blocks have a unit length such as sector size. partitions, where consecutive partitions are not a single disk drive ordinal position, but multiple written sequentially to the disk drive. Data stored across each disk The unit length or capacity of is referred to as the stripe size. This stripe size generally affects the data transfer characteristics and access times of disk arrays. chosen to optimize the transfer of traffic data. If the data block is n units long If longer, the process runs every next stripe position on each disk drive. repeated. This method turns a physical drive into a single logical device. and may be implemented through either software or hardware.

Used to configure for data protection and recovery in disk array subsystems. One technique is referred to as a parity scheme. In this parity scheme , data blocks written to different drives in the array are used, and the known exclusion An alternative or (XOR) technique is written to a reserved or parity drive within the array. It is used to create parity information. The advantage of the parity scheme is that the Used to minimize the amount of data storage dedicated to data redundancy and recovery purposes It's also a good thing. For example, FIG. 1 shows three disks: disk O, disk 1 and disk 2 are used for data storage, one disk namely disk 3 describes the traditional 3+1 mapping scheme used to store parity information. It's clear. In Figure 1, each rectangle surrounding a number or a letter P combined with a number is It corresponds to a sector which is preferably 512 bytes. As shown in Figure 1, each complete A stripe separates each disk O for a total of 12 sectors of data storage per disk. 11 and 2 to 4 sectors are used. Assuming a standard sector size of 512 bytes , the stripe size of each of these disk stripes is A 2-kilometer storage area defined as the amount of storage allocated to a stripe on one of the number of disks. It's Robite. In this way, the portion of each disk allocated to the stripe is Each complete stripe can store 6 kilobytes of data, including a total of Ru. Disk 3 of each stripe is used to store parity information. death However, the use of parity defect tolerance techniques in disk array systems is There may be disadvantages. One for the 3+1 mapping scheme illustrated in Figure 1 The disadvantage of this is that every time the data drive is updated or written to, the parity Loss of performance within the disk array as the live must be updated It is. Data is not only written to the data drive, but also to the parity drive. must go through an XOR process to write updated parity information to Must be. This process, by having distributed parity data, May be partially alleviated by relieving the load on a dedicated parity disk . However, this does not reduce the number of total data write operations.

Another disadvantage to parity defect tolerant techniques is that traditional operating systems A disk arrangement where the stem or ornis is referred to as a partial stripe write operation. Many small writes on a disk subsystem that are often smaller than the stripe size of It is to carry out the For example, many traditional file systems use files such as A small display to show the structure of files, directories and free space in the system. Use data structures. In a typical UNIX file system, this information is a structure called lN0DE or inode, which is generally 2 kilobytes in size. Retained. lN0DE or INDEX MODE is the position where the data is placed , the owner and user, the most recent time the file was modified or accessed, the MODE The latest time and number of links that were modified or the file name that collaborated with that IN0DE. Contains information about file type and size. O5/2 high performance file system In systems, this structure is called an FNODE. These structures are file access It is updated frequently as it contains modification date and file size information.

These structures are compared to typical data stripe sizes used in disk arrays. is fairly small and therefore causes many partial stripe write operations.

When partial stripe write operations occur fairly frequently on a disk array, The existing data or parity information on disk will be replaced with the new parity information so that The disk subsystem must be read from disk in order to generate system performance is severely reduced. This creates extra spins on the disk drive. This will cause a delay in the time it takes to implement the request. In addition to the time required to perform the actual operation. In addition, a READ operation followed by a WRITE operation to the same sector of the disk is A type of fixed disk drive that rotates one disk revolution or approximately 16.5 millimeters. It is recognized that this will result in a loss of 2 seconds.

As long as a complete stripe of data is written to the array, parity information is may be generated directly from data written to disk arrays, and therefore No extra reading of the write is required. However, the problem is The disk array controller calculates parity for a complete stripe so that Because the computer cannot get enough information from the data written to the Occurs when writing only a partial stripe to a disk array. Partially like this A striped write operation is typically read first and is written by an active process on the host system. disk that is modified by the disk and written back to the same address on the data disk. requires data stored on the computer. This operation performs data disk READ, data disk consists of modifying the data and writing the data to the same address. generally Two techniques used to calculate parity information for each fractional stripe write operation There is.

In the first technique, data disks are Partial stripe writes tolerate parity defects first when the computer system is updated parity information and data from the parity disk for each data disk sector Read old data values to be replaced from disk. After that, the XOR parity information is , the related parity sectors are recomputed by the host or local processor or dedicated logic that replaces the data. It will be done. This recovers parity values without their data values. The new data value is XORed with this recovered value to generate new parity data . The WRITE command then writes the updated data to the data disk and It is executed by writing new parity information to the parity disk. This process Two additional partial sector READ operations or parity operations are performed before generating the standard XOR parity information. It is recognized that reading from the security disk and reading old data is required. Ru. Additionally, a WRITE operation is at the position just read. Therefore data transferability This brings disadvantage to Noh.

The second method uses the strut despite the fact that it is not replaced in the WRITE operation. Eve needs to read the rest of the data which cannot be denied. new parity All information is updated using recovered old (old) data and new data. May be determined for stripes. This process identifies data that should not be replaced. Data READ operation and full stripe WRIT to save parity information E operation is required.

According to the prior art, parity defect tolerance methods that utilize disk arrays are partially To manage striped WRITE operations, one of the techniques listed above must be performed. did not become. Therefore, a partial stripe write is a stripe write that was not written. must be fetched, or the existing parity for the stripe must be fetched. The system efficiency is reduced because the system information must be read before the information is actually corrupted. caused harm to the rate. Therefore, to reduce the number of partial stripe write operations, , a modification that performs a disk WRITE operation in a parity defect-tolerant disk array. There is a need for improved methods.

It seems appropriate to format the disk drive in the background. It will be done. Manufacturers also require that the disk drive be is formatted to a low level. Low-level formatting operations are performed on sectors It is used to identify sectors after formatting is complete, along with the formation of with marking of their addresses. The data part of the sector is established and the dummy data data is filled. Disk drive unit collaborates with computer system When each ornis that manages the disk controller and computer system Forms the high-level or logical format of a disk drive and stores it on a disk. Position the “File System” and fit the disk drive into a standard ornis. We have to make sure that we let them do it. This high-level formatting is Each file system is associated with an ornis service referred to as a "file system" program. Executed by the disk controller. On UNIX ornis, the make file system The system program uses the disk array to create a file system on the disk array. It works in conjunction with the controller. In traditional systems, ornis is a block or sector. The makefile system program considers the disk as a contiguous list of They are not aware of the topology of these blocks.

Disclosure of invention The present invention provides disk storage in a computer system having a disk array subsystem. The present invention is directed to methods and apparatus for improving disk performance. In the method according to the invention, A non-uniform disk array containing some designated area with variable size of data stripes A mapping scheme is used. This disk array is frequently used in file systems. has a stripe size that is almost the same as the size of the internal data structures used in A region consisting of multiple data stripes and a region used for general data storage. A region containing multiple data stripes with a larger stripe size.

When a write operation occurs involving one of the small data structures, preferably The data structure is a disk whose complete stripe size matches the size of the data structure. Maps to a small stripe region in the array. File system like this Whenever a data structure is updated, the operation is a full stripe write. child This reduces the number of partial stripe write operations and thus reduces the number of The associated performance penalty is also reduced.

A better understanding of the invention may be obtained from the following detailed description of the preferred embodiments, taken together with the accompanying drawings. It can be obtained when you think about it.

Brief description of the drawing Figure 1 shows a traditional 3+1 disk array mapping with uniform stripe size. It is a prior art diagram of Keim.

2 and 3 illustrate a descriptive computer system in which the method of the invention may be implemented. It is a block diagram.

FIG. 4 is a block diagram of the disk subsystem of the preferred embodiment.

FIG. 5 is a functional block diagram of the transfer controller of FIG. 4 in accordance with a preferred embodiment.

FIG. 6 shows a 3+1 disk array with variable size stripes according to the first embodiment. FIG. 2 is a diagram of a mapping scheme.

FIG. 7 shows RAID5 with variable stripe size according to the second embodiment of the present invention. FIG. 3 is a diagram of a 3+1 disk array mapping scheme.

FIG. 8 is a diagram of a 4+1 disk array mapping scheme according to a preferred embodiment of the invention. It is.

FIG. 9 is a flowchart diagram of a WRITE operation according to the method of the present invention.

FIG. 10 is a flowchart diagram of a READ operation according to the method of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION The computer system and disk array subsystem described below are of the invention. represents a preferred embodiment. Of course, if you have the capabilities of the system described below, It is anticipated that other computer systems may be used to implement the invention. It will be done.

With reference to signals 2 and 3, the letter C generally refers to a computer on which the invention may be implemented. The data system is clearly specified. For clarity, System C is designated by circled numbers 1 through 8. It is shown in two parts in FIGS. 2 and 3 with referenced interconnects. System C contains a number of block elements interconnected via four buses.

Central processing unit 1 - CPU is a system processor connected to system processor bus 26. a system processor 20, a numerical coprocessor 22, and a cache memory controller 24. , and associated logic circuits. The cache controller 24 includes a high-speed cache. Data random access memory (RAM) 28, non-cached memory address (NCA) map programming logic circuit 30, non-cached address Or NCA memory map 32, address exchange latch circuit 34, data exchange transformer Seaver 36 and page hit detection logic 43 cooperate. Also, the CPU has System processor preparation logic circuit 38, next address (NA) enable logic The bus request logic circuit 40 and the bus request logic circuit 42 cooperate.

The system processor is preferably an Intel 80386 microprocessor. be. System processor 2o interfaces to system processor bus 26. It has controlled control, address and data lines. The coprocessor 22 is Preferably, the local processor bus 26 and the system processor 2 are connected in a known manner. Intel 80387 or Waychik WTL31 interfaced with 67 numerical processor. Cache RAM 28 is preferably required bus under the control of cache controller 24 to perform cache memory operations. Preferably fast static random interface with 26 address and data elements It is access memory. Cache controller 24 preferably has a two-way set An instance configured to operate in associative master mode. Intel 82385 cache controller. In a preferred embodiment, each component This is the 33MHz version of the unit. Intel 80486 my 80386, numerical coprocessor and external cache memory system The processor, 82385 and cache RAM may be replaced. address latch times A cache controller 34 and a data transceiver 36 together with the processor 2o 24, a processor bus 26 and a host or memory bus 44. form a local bus that interfaces between Circuit 38 connects bus 26 to Controls access and provides bus ready signals to indicate when to start the next cycle It is a logic circuit. Enable circuit 40 is in pipeline address mode. the next address of data or code to be used by the subsystem element is used to indicate that the local bus 26 may be placed on the local bus 26.

A non-cached memory address (NCA) map programmer 30 is a processor 20 and non-cached address memory 32, the non-cached memory Map your location. Uncached address memory 32 includes various types of caches. areas of system memory that are uncached to avoid cache coherence problems. Used to specify the area. The bus request logic circuit 42 receives the requested data. is not located in cache memory 28 and requires access to system memory. To request access to host bus 44 in situations such as when 20 and related elements.

A main memory array or system memory 58 is coupled to host bus 44 . main memory Array 58 is preferably a dynamic random access memory. memory 58 is an EISA pass buffer (EBB) data buffer circuit 60 and a memory control circuit. 62 and memory mapper 68 to host bus 44 . this Buffer 60 performs the functions of transferring data and generating and checking parity.

The memory controller 62 and memory mapper 68 include an address multiplexer and a column addressr. Address strobe (ADDR/CAS) buffer 66 and 7 rear address strobe Interfaces to memory 58 via RAS enable logic circuit 64. To do so.

In the drawings, system C includes processor bus 26 or host bus 44, an extended Industrial Standard Architecture (EISA) bus 46 (Figure 3) and X bus 90 (Figure 3) ). Parts of the system shown in Figure 3 and not detailed below The details describe an example of a fully configured computer system. less important to the invention. The part of system C shown in FIG. ISA bus 46, EISA bus controller 48 EBB data buffer 50 and address EISA bus 46 and host bus 44 referred to as slatch and buffer 52 The data latches and transceivers that interface between It is an EISA system. Figure 2 also shows the EISA standard computer system. An integrated system peripheral (ISP) that works with a number of elements used in the system5 4 is shown.

The integrated I5P54 provides access to the main system without requiring access to the processor 20. Memory and input/output inserted into memory 58 (Figure 1) or EISA slot (Ilo) direct memory access controller 56 to control access between locations; include. Also, l5P54 is the interrupt controller 70, unmasked interrupt logic. 72 and interrupt signals and comply with EISA specifications and conventional practices. The system includes a system timer 74 that generates the timing signals and wait states required by the method. nothing. In the preferred embodiment, the processor that generated the interrupt request is a traditional Intel It emulates the 8259 interrupt controller and goes through two extended interrupt control circuits. controlled by The l5P54 also cooperates with the bus controller 48 to The cache controller 24, DMA controller 56 and bus mask device located in the bus 46 A bus mediation logic that controls and mediates between the various requests for the EISA bus 46 by devices. 75.

78 and ISA and EISA data buses 80 and 82; 46 on the ISA control bus and interfaced via the X bus 90. . Control and data/address transfers for the XBus 90 are provided by the XBus control logic 9. 2, facilitated by data buffer 94 and address buffer 96.

A suitable keyboard and mouse are connected to the X-bus via connectors 100 and 102. Species, such as keyboard/mouse controllers 98, each interface to an X bus 90. Various peripheral devices are attached. The X bus also includes system C and system Read-only memory or ROM circuit containing basic operating software for video operation 106 is attached. Further, the serial communication boat 108 connects to the system via the X bus 90. connected to system C. The block circuit 110 includes a floppy disk support, There is a parallel port, a second serial port and video support circuitry.

Computer system C includes a disk array controller 112 and a fixed disk connector. 114 and a fixed disk array 116 .

Disk array controller 112 is connected to EISA bus 46, preferably by a slot. are connected to communicate data and address information through the EISA bus 46. fixed Disk connector 114 connects to disk array controller 112, which in turn connects to fixed disks. is connected to the network array 116.

Referring now to FIG. 4, the disk subsystem used to provide a detailed description of the present invention. 111 is shown. Disk array controller 112 is preferably an Intel 801 It has 86 local processors 130. This local processor 130 has a multiplexed address/data bus UAD and control outputs UC. Many The duplicated address/data bus UAD provides outputs for local processor data and It is connected to transceiver 132, which is bus UD. Also, multiplexed addresses address/data bus UAD whose Q output forms the local processor address bus UA. It is also connected to the D input of the latch 134. The local processor 130 is Via multiplexed address/data bus UAD and address data bus UA It cooperates with an associated random access memory (RAM) 136. RAM13 6 connects to the processor control bus UC to develop the appropriate timing signals. ing. Similarly, read-only memory (ROM) 138 stores multiplexed addresses/ Data bus UAD, processor address bus UA and processor control bus UC is connected to. In this way, local processor 130 has a and has its own local memory to control operations. Programmable arrangement A column logic (PAL) device 140 is utilized in the disk array controller 112. connected to the local processor control bus UC to deploy additional control signals. ing.

Also, local processor address bus UA, local processor data bus bus UD and local processor control bus UC are bus mask interface based. It is connected to the controller (BMIC) 142. 8MIC142 is EISA or MCA The ability to interface the disk array controller 112 to a standard bus such as and act as a bus master. In the preferred embodiment, 8 MIC142 An Intel 82355 interfaced to ISA bus 46. in this way 8MIC142 is connected to local processor buses UA, UD and UC. interfaces to the local processor 130 so that data and control information can be can be passed between host system C and local processor 130.

Additionally, a local processor data bus UD and a local processor control bus U C is preferably connected to transfer controller 144. Generally, the transfer controller 144 , various other devices in disk array controller 112 and transfer buffer RAM. A specialized multi-channel direct link used to transfer data between It is a direct memory access (DMA) controller. For example, the transfer controller 144 is a BMIC Connected to 8MIC142 by data line BD and BMIC control line C It will be done. Thus, if a READ operation is requested on this interface , the transfer controller 144 transfers data from the transfer buffer RAM 146 to the 8MIC 142. can be transferred. If a WRITE operation is requested, the data is 8M It can be transferred from the IC 142 to the transfer buffer RAM 146. then transfer Controller 144 transfers this information from transfer buffer RAM 146 to disk array 116. can be passed. Transfer controller 144 is described in U.S. Application No. 431,735 and European patent application publication number 0427119 published on April 4, 1991 corresponding to the state These are described in more detail in , and are referred to here.

The transfer controller 144 includes a disk data bus DD and a disk address bus. and control bus DAC. The disk address and control bus DAC is a fixed disk Connector 114 is connected to two buffers 165 and 166 for transfer. It is used to exchange control signals between the transmission controller 144 and the disk array 116.

Disk data bus DD includes two Connected to data transceivers 148 and 150. Transceiver 148 and The output of the transfer port 146 is connected to the two disk drive port connectors 1. 52 and 154. Two connectors 1 in similar fashion 60 and 162 are connected to the outputs of transceiver 150 and 166. There is. Two hard disks are connected to each connector 152.154.160 and 162 can be connected to. In this way, up to eight disk drives can be transferred The controller 144 can be connected and coupled to the controller 144 . As discussed below, preferred embodiments In this case, five disk drives are coupled to transfer controller 144 to form a 4+1 disk drive. A tuping scheme is used.

In descriptive disk array system 112, compatibility port controller CPC16 4 is also connected to the EISA bus 46.

The CPC 164 transfers across the compatibility data line CD and the compatibility control line CC. It is connected to the transmission controller 144. Therefore, CPC164 is a disk array controller 11 that is addressed to allow very high throughput. 2 and its 8 written for legacy computer systems that do not have MIC142. formatted software so that it can operate without requiring software rewrites. will be accomplished. In this way, the CPC 164 interfaces with the hard disk. Emulate the various control ports you have already used.

Referring now to FIG. 5, transfer controller 144 itself includes a series of separate circuit blocks. nothing. The transfer controller 144 functions as a RAM controller 170 and a disk controller 172. Contains two main units referenced. The RAM controller 170 has a transfer buffer. control various interface devices that have access to the RAM 146 and an arbiter for data transfer to and from the transfer buffer RAM 146. It has a multiplexer.

Similarly, disk controller 172 determines which of the various devices are integrated disk interfaces. - Contains an arbiter to determine who has access to the face 174, and where the data is collected. multiplexing capabilities for proper forward and backward transfer through the product disk interface 174. including becoming

Transfer controller 144 preferably includes seven DMA channels. 1 DMA Channel 176 is assigned to cooperate with BMIC 142. second DMA channel 178 is designed to work with CPC 164. these The two devices, BMIC 142 and bus compatibility port controller 164, through their appropriate MA channels 176 and 178 and RAM controller 170. and is coupled only to the transfer buffer RAM 146. BMIC142 and compatible port The controller 164 has integrated disk interface 174 and disk array 116. do not have direct access to. Local processor 130 (FIG. 3) is connected to the RAM controller 170 through a processor DMA channel 180. , the disk controller 172 through the local processor disk channel 182. It is connected to the. Thus, as desired, the local processor 130 is connected to transfer buffer RAM 146 and disk array 116.

Further, the transfer controller 144 may individually and simultaneously transfer information to the disk array A and the RAM 14. 6 DMA/disk channels that can pass between 184.186.188 and 190. Additionally, the fourth DMA/disk channel 190 has a parity transfer controller 14 without requiring calculations on local processor 130. It is noted that it includes an exclusive-or capability so that it can be easily implemented in It will be done. The computer system C and the disk array subsystem 111 are 2 represents a preferred computer system for implementing the method of the invention.

Computer system C is preferably U, although other ornis may be used. Use NIX ornis. As mentioned in the background, UNIX ornis Includes services referred to as file system programs. favorable fruit In the example, the makefile system program determines the number and number of lN0DEs created. Information regarding the size of the IN0DE is provided to the disk controller 112. selectively The makefile system supports small stripe and large stripe areas. information about the desired stripe size and the boundaries dividing these areas. Contains sufficient intelligence to inform disk controller 112. As already mentioned, lN0 The number of DEs is approximately equal to the number of files that should be allowed in the system. Disk arrangement system Controller 112 stores this information in a file system on each disk with array 116. Used to expand.

Disk array controller 112 divides disk array 116 into small stripes and large stripes. We use a multiple mapping scheme according to the invention that partitions into striped regions. small The small stripe area preferably occupies the first N sectors of each disk and Reserved for the N0DE data structure, the remaining stripes in the array Creates a large stripe area with free space used for data storage. that Therefore, in the preferred embodiment, the disk controller 112 is configured for small stripe areas. , allocate the first N sectors of each disk in the array. the rest of each disk Sectors are formatted into large striped areas. disk array controller 112 represents the small stripe and large stripe areas in RAM 136. Remember the dividing boundary. The lN0DE data structure is then written to each disk. disk array controller 112 uses this boundary to limit the size of array 116. Write lN0DE to the small stripe portion.

In this way, whenever lN0DE updates, the resulting operation is a full stripe. This is writing. This is because, as already mentioned, partial stripe write operations are generally This increases system performance because it requires additional read operations and reduces performance.

In an alternative embodiment of the invention, a small stripe area is located in the first N sections of each disk. Rather, small stripe regions occupy space between large stripe regions. Contains multiple areas scattered throughout.

In this example, there are multiple stripes dividing the small stripe and large stripe area. The boundary is that the disk controller 112 places the lN0DE data structure in the small stripe area. is stored in the RAM 136 so that it can be written.

In an alternative embodiment of the invention, an O5/2 ornis is used. In this example, the above The O5/2 service, which is similar to the makefile system program created by FN Information regarding the number of ODEs created and the size of the FNODE is sent to the disk controller 11. Supply to 2. The disk controller then uses multiple map pins similar to those described above. The disk array 116 is divided into small stripes and large strips using a Split into live regions, with a small stripe region reserved for the FNODE data structure. It is about. What kind of ornis or file system can the invention operate with? What you can do will get noticed.

Referring again to Figure 1, the lN0DE data structure with a size of 2 kilobytes is the prior art. Example of a disk array with a uniform disk stripe size of 2 KB using the technique For example, when writing to stripe 0, all lN0DEs are written to sector 0 of disk 0. ．． 1.2 and 3, leaving disks 1 and 2 unused. effectively this The operation is called a disk array system because only one disk is accessed. deny the advantages of Also, the amount of unused space can become significant and the disk drive This results in inefficient use of space. If the data is sequential stripe remaining i.e. disk If it is possible to write to the part of the stripe in 1 and 2, then in this stripe The resulting operation is a partial stripe write operation with a performance penalty as described above. Consists of.

Referring to Figure 6, utilizing multiple stripe sizes according to an embodiment of the present invention. A diagram illustrating a 3+1 mapping scheme is shown. Figure 6 is only an example. , and the disk array 1l6 uses a very large number of stripes of each size. is attracting attention. The disk drives used in the preferred embodiment each have 51 Contains many sectors with 2 bytes of storage. In the embodiment shown in FIG. The disk array has two stripe sizes: 1 kilobyte disk stripe size. and a disk stripe size of 2KB. Shown in Figure 6 Stripes O11 and 2 have a total of 6 sectors per complete stripe or per disk on disks 0.1 and 2 for 3 kilobytes of data storage. A disk stripe size of 1 kilobyte with two sectors is used.

Additionally, stripes 0, 1 and 2 are used to store parity information for each stripe. Two sectors of disk 3 are used for this purpose. Stripes 3-6 are 2KB for each disk on disks 0, 1, and 2 using a disk stripe size of Four sectors are allocated for data storage for each stripe, and four sectors are allocated for data storage on disk 3. is reserved as parity information for each stripe.

In this example, the lN0DE data structure has a small stripe size, i.e. 0.1 or 2 of the disk array. As already mentioned, The lN0DE structure is assumed to be 2 kilobytes in size in the preferred embodiment. Ru.

Therefore lN0D written in stripe O11 or 2 as shown in country 6 The E structure fills up space on disks O and 1, leaving disk 2 generally unused and Disk 3 is used to store each parity information. In this example Data is written to disk 2 of each stripe after lN0DE is written there. Writing is not allowed. In this way, partial stripe write operations are prevented from occurring. It will be done. Therefore, using a smaller stripe size for portions of disk array 116 to prevent data from being written to unused space after lN0DE is written. By stopping, write operations on these structures emulate full striped writes. Rate. However, during this full stripe write, disk 2 remains unused. not being used or written, thus resulting in inefficient use of disk area. attracts attention. Furthermore, each small disk 2 has a lN0DE structure written to it. Because each stripe is generally unused, data transfer from disk array systems is The transmission bandwidth is reduced and the array is required as a 2+1 mapping scheme in these examples. It works properly.

One solution to this problem is to use different disks in each stripe, as shown in Figure 7. The goal is to distribute unused space across the In this way, data transfer bandwidth is reduced. The smaller number is not important since each disk is used approximately equally. However, each disk Data transfer bandwidth is sub-optimal since the disk accesses involve unused disks. Ru. Furthermore, this method generates an undesirable amount of unused disk space.

In a preferred embodiment of the present invention, a 4+1 mapping scheme is used, as shown in M8. is used. FIG. 8 is illustrative only; the preferred embodiment disk array 116 is Utilizing a significant number of stripes in small stripes and large stripe areas Once again, the use of Stripes in small stripe areas i.e. The disk stripe size for stripes O to 4 is 512 bytes; stripe size is defined as the amount of each disk allocated to a stripe. child As in, each complete stripe in a small stripe region has an lN0DE structure It holds exactly 2 kilobytes of data, which is roughly equivalent to the size of . Therefore, lN When a 0DE structure is written to a small stripe in disk array 116 If a full stripe write operation is performed and the lN0DE is empty without any unused space, also occupies the entire stripe. In this way, the bandwidth of the disk array 116 is The blocks also share each access and are optimally used since no unused space is created.

Referring again to FIG. 4, in the preferred embodiment, disk requests are preferably The system is connected to the disk array controller 112 through the EISA bus 46 and 8 MICs 142. system processor 20. This request is received through 8MIC142. The local processor 130 that received the information stores the information in the local processor RAM memory 136. Establish data structures. This data structure is known as a command list and is It may be a simple READ or WRITE request to the array 116; or multiple READ/WRITE or diagnostic and configuration requests. It may also be a more elaborate set of requirements. The command list then becomes the locale for processing. file processor 130. Local processor 130 then processes the data. Supervise the execution of command lists, including transfers. Command list execution completed Sometimes local processor 130 operates on system microprocessor 20. ornis device driver. Submission of command list and commands The notification of the completion of the list is sent by a program using the I10 register allocated to the 8MIC142. Achieved by rotocol.

READ and WRITE operations performed by disk array controller 112 are As many application tasks running on local processor 130 executed. Due to the interactive nature of the I10100, an exemplary computer system System C executes disk commands as a single batch task on local processor 130. It is impractical to process. Therefore, the local processor 130 An implementation that allows multiple tasks to be addressed by local processor 130, including methods of Utilize time multitasking system. Preferably local processor 13 Ornis on 0 is an AMX86 multitasking management program by Kodak. be. The AMX Ornis kernel is an application configured using the method of the present invention. in addition to providing many system services.

Referring to signal 9, a computer system including an intelligent disk array controller 112 A flowchart diagram of a WRITE operation performed in C is shown. WRITE operation is an active process or application that has access to a disk device driver. Step 200 of issuing the passed WRITE request to the system processor 20 Start with This disk device driver is installed on computer system C. system memory 58 that performs disk unit and actual interface operations; It is a part of the software contained within. Disk device driver software The system administrator configures the specific task to perform the required I10 operation. Assume that the system processor 20 is under control.

The control assumes that the disk device driver is under control of the system processor 20, The process moves to step 202 where a WRITE command list is generated.

In step 204, the device driver passes through the BMIC 142 or CPC 164. and submits the WRITE command list to the disk controller 112. then device The driver enters a wait state to wait for a completion signal from the disk array controller 112. enter.

The logical flow of operations is that local processor 130 executes a WRITE command list. received and whether the lN0DE data structure has been written to disk array 116. The process proceeds to step 206 in which it is determined whether In implementing this decision, local The processor preferably utilizes the boundaries between the small stripe and large stripe areas. do. In an alternative embodiment of the invention, the device driver This can be added to the WRITE command list, taking advantage of the boundaries between large stripe areas. Intelligence that collaborates with information collaborates with device drivers. If lN0DE data structure has been written to disk array 116, the load is performed in step 208. The processor 130 writes a full stripe WRIT to a small stripe area. Establish a disk-specific WRITE command for the E operation. After that, control is transferred The control chip (TCC) 144 was written to the disk array 116. The process moves to step 210 in which parity data is generated from E. small stripes An operation that writes lN0DE to an area is treated as a full stripe write operation, and Thus, any preceding READ operations associated with the partial stripe write operation are not encountered. This is noteworthy. After that, the operation is controlled by the TCCl 44 from the disk array 116. step 21 of writing data and recently generated parity information to the disk in the Transition to 2. Control then determines that the local processor 130 has access to additional data. The process moves to step 214 in which it is determined whether or not the data will be written to the disk array 116.

If additional data is written to disk array 116, control is transferred to the local Processor 130 increments the memory address and the byte to be transferred. The process moves to step 216 where the number is decremented. Control then passes to step 206. return. If no additional data is written to disk array 116, the Control begins at step 214 where local processor 130 signals WRITE completion. The process moves to step 224. If the local processor 130 If the lN0DE structure has not been written to disk array 116, If the local processor 130 determines that the large Disk specific WRITE command for data to be written to a new stripe area Establish. This operation includes the small and large stripes stored in RAM 136. requests the local processor 130 to utilize boundaries between different stripe areas. different size struc- tures to ensure that the appropriate physical disk addresses are deployed. It is noted that the appropriate bias or offset is developed to modify for the type.

Optionally, this intelligence can be established in the device driver and access and use the boundaries between small stripe and large stripe areas. Then, use this offset information in the WRITE command list. This example In the local processor 130, this intelligence is cooperated with the device driver. , it is required to exploit the boundaries between small stripes and large stripe regions. Not done.

In step 220, the transfer controller chip 144 sends a parity only for written data. Generate tea information. Here, if the write operation is a full striped write For example, the disk controller 112 generates parity information only from written data. It is noteworthy that it is possible to However, if the write operation is partially striped If it is a write operation, the look-ahead operation uses the current data or parity on disk. May need to be executed to read the information. As already mentioned, partial These additional read operations that result from the tripe write operation are performed by disk system 1. 11 performance is reduced. Technology used to improve performance of partial stripe write operations is a U.S. patent application serial number 752,77 filed on August 30, 1991. Name of 3 [METHoDFoRPERFORMING WRITE 0PERA TIONS IN A PARITY FAULT TOLERANT DISK ARRAYJ and US Patent Application Syria filed on December 27, 1991 Name of file number 815,118 “THOD FORIMPROVING PAR Tl, AL 5TRIPE WRITE PERFORMANCE IN DI Reference is made to SK ARRAYSUBSYSTEMSJ, both of which are associated with this invention. Assigned to the same assignee and incorporated herein by reference. In step 222, the The disk controller 112 writes data and parity information to the large stripe area. nothing. Control then determines whether additional data is to be written to disk array 116. The process moves to step 214, where the local processor 130 determines. Step 21 4, if it is decided not to transfer any additional data, control disk array controller 112 signals WRITE completion to disk device driver The process moves to step 224. Control is then given to the device driver by the application. release control of the system processor 20 to continue execution of the program Proceed to step 226. This completes the operation of the WRITE sequence.

Referring to signal 10, the disk array sub using intelligent disk array controller 112 A READ operation performed on system 111 is shown. READ operation is An active process or application program runs on system processor 20. Step 2 Generating the READ command passed to the disk device driver Starting from 50. The disk device driver controls the system processor 20. Assuming control, the system processor 20 is and assigned to Compact Computer Co., Ltd., the assignee of this invention. The process moves to step 252 where a READ command list similar to is generated. child The READ command list is sent to the disk subsystem 111 in step 254. After the operation, the device driver waits until it receives the READ completion signal. do.

In step 256, the disk controller 112 connects the BMIC 142 or CPC 146 to The READ command list is received via the transfer controller 144 and the read operation is small. Accessing stripe area data, i.e. lN0DE or large stripe area data. determine whether access is intended. In performing this decision the disk controller 112 preferably stores the disk address of the requested data in RAM 136. Compared to the boundaries between the stored small stripe and large stripe areas, Determine which area is being accessed. Optionally, further intelligence can be added to the device The driver works with the information which areas are accessed in the READ command list. so that it can be established in the device driver. According to this embodiment, the di The disk controller 112 requires little extra intelligence and simply controls the disk specific REA. It only uses this information in the READ command list by generating a D request. Ru.

If a small stripe area is accessed, the local processor 130 In step 260, the requested lN0DE and small stripe area generate a disk-specific READ request for its associated parity information at; Queuing requests in local RAM 136. Control is when the request is executed and The requested data is transferred from the disk array 112 to the transfer controller 144 and the BMIC 14. 2 or the address indicated by the requested task via CPCl34. The process moves to step 264 where the data is transferred to the system memory 58 of the system. Large read operation Disk controller 1 intends to access data in a striped area. 12, the local processor 130, in step 262, data and its associated parity information in large stripe areas. Generates a disk specific READ request and executes the request in local RAM 136 That is, requests are queued. These requests are executed and the data is retrieved in step 264. be transferred. Upon completion of the data transfer in step 264, the disk array control device 112 signals READ completion to the disk device driver in step 266. , releases control of the system processor 20.

Therefore, forming a variable stripe size of the disk array, in particular Full stripe size equal to the size of frequently written small data structures The number of partial stripe write operations is reduced by forming regions with be done.

A small stripe area where the data stripe exactly matches the size of the data structure By placing these smaller data structures in This is a live write. This eliminates the performance penalty associated with partial stripe write operations. Since it is removed, it increases disk performance.

The foregoing disclosure and description of the invention is descriptive and illustrative, and does not include the descriptive logic and flow. - Various changes in components, methods and operations, as well as details of the charts, are subject to invention. may be made without departing from the spirit of

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Claims (1)

[Claims] 1. A first area consisting of a plurality of data stripes having a first stripe size and multiple data with a stripe size larger than this first stripe size. a second area consisting of data stripes, the first stripe size being diagonal; How to improve the performance of disk arrays depending on the size of the data structures used in disk arrays In, Generates a data write operation to a disk array, and the data comprises one of the data structures. If the data comprises one of the data structures, The data is placed in a data stripe in a first area with a stripe size of 1. write, If the data does not include one of the data structures, the data in the second area A computer system comprising the step of writing said data to a data stripe. How to improve disk array performance in disk arrays. 2. Writing the data structure to the first area is a full stripe write operation. The method according to claim 1. 3. A disk controller in which the data writing determining step is coupled to a disk array. 2. The method of claim 1, carried out by. 4. The step of determining data writing is performed in a computer system. 2. The method of claim 1, executed by a processor. 5. Generate a read operation that requests data from the disk array, and the read operation When accessing the first stripe size area or the second stripe size area decide whether or not you intend to the first or second stripe size area depending on the determining step of the read operation; 2. The method of claim 1, further comprising the step of providing the requested data from an area. Method. 6. The disk array utilizes parity defect tolerance technology to improve parity for the data. and if said data comprises one of the data structures, write the parity information in the area, If the data does not include one of the data structures, the parity is stored in a second area. 2. The method of claim 1, further comprising the step of: writing personal information. 7. System bus and A plurality of data streams coupled to this system bus have a first stripe size. A first region consisting of tripes and a strut larger than this first stripe size. a second area consisting of a plurality of data stripes having a size of A stripe size of 1 corresponds to the size of the data structures used in the disk array. disk array, A means coupled to the system bus for generating data write operations to the disk array. step by step, coupled to the generating means and the system bus so that the data is one of the data structures. means for determining whether or not a system bus is included; and if the data comprises one of the data structures, the first stripe sensor means for writing the data to a data stripe in the size area; coupled to said determining means and said system bus, said data being one of the data structures; If the data stripe in the second stripe size area does not have one a computer for performing a disk array write operation, comprising means for writing said data to a disk array; computer system equipment. 8. The data structure write operation to the first stripe size area 8. The apparatus of claim 7, which is a tripe write operation. 9. Having multiple variable-sized data stripes to store data, the first The stripe size corresponds to the size of the data structures used in the disk array. How to improve disk array performance in computer system disk arrays generates a data write operation to a disk array, and the data is one of the data structures. If the data comprises one of the data structures, then The data stripe has a first size corresponding to the size of the data structure. write the data, If said data does not include one of the data structures, it does not have a first size. A method comprising writing said data to a data stripe. 10. The data structure write to the data stripe having a first size 10. The method of claim 9, wherein the method is a regular stripe write operation. 11. The disk array has a first stripe size for storing data structures. and a region with a second stripe size, generating a read operation requesting data from a disk array, said read operation requesting data from said first disk array; when accessing the stripe size area or the second stripe size area. Decide whether to use Mori or not. from the first or second stripe area depending on the read operation decision; 10. The method of claim 9, further comprising the step of providing the requested data. 12. System bus, Multiple variable-sized devices are coupled to this system bus to store data. data stripe, and the first stripe size is the data used for the disk array. a disk array corresponding to the size of the data structure; A means coupled to the system bus for generating data write operations to the disk array. step by step, coupled to the generating means and the system bus so that the data is one of the data structures. means for determining whether or not a system bus is included; and if said data includes one of the data structures, then the size of said data structure writing the data structure to a data stripe having the corresponding first size; a means of entering, coupled to said determining means and said system bus, said data being one of the data structures; If the data stripe does not have the first size, then the data stripe does not have the first size. a computer that performs disk array write operations, having a means for writing data; ta system. 13. Forming a file system on the disk array and partitioning the disk array. a first area consisting of a plurality of data stripes having a first stripe size; and a plurality of data streams having a stripe size larger than the first stripe. a second area consisting of stripes, and the first stripe size is corresponding to the size of the data structure used for the array, Generates a data write operation to a disk array, and the data contains one of the data structures. and if the data includes one of the data structures, the first Write the data to a data stripe in a first area with a write size. fruit, If the data does not include one of the data structures, the data structure in the second area is Utilizes a parity defect tolerant technique with the step of writing said data in a tripe. Improve disk array performance on computer system disk arrays used Method. 14. The data structure write to the first area is a full stripe write operation. 14. The method of claim 13. 15. Generate a read operation that requests data from the disk array, and if the read operation Accessing the first stripe size area or the second stripe size area decide whether you intend to the first or second stripe size area depending on the determining step of the read operation; 14. The method of claim 13, further comprising the step of providing the requested data from an area. the method of.