JPH0648487B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Outline Industrial field of application Conventional technology (Figs. 7 and 8) Problems to be solved by the invention Means for solving problems Problems Working Examples Principle explanation (No. FIG. 1) First embodiment of the present invention (FIGS. 2 to 4) Second embodiment of the present invention (FIGS. 5 and 6) Effect of the invention [Overview] A semiconductor device manufacturing method having a small logic description amount. In order to provide a method for manufacturing a semiconductor device that can be efficiently designed even if the hierarchy is deep and can be easily modified, the internal cells that make up the logic block of the LSI chip are arranged in a hierarchical relationship. In a method of manufacturing a semiconductor device for automatically designing an LSI by automatically specifying layers and connection relationships in all layers of the cell by designating each layer by a predetermined description language that describes the connection relationship, Nanet Name, the logical description of the block is specified, and the hierarchical relationship of the chips is specified to design the lowest level of logic. When an upper level is generated, external terminals are automatically generated using the net name, Configure to perform logical design up to the upper layer.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, more specifically, L
The present invention relates to a method of manufacturing a semiconductor device that improves the logic design when automatically designing an SI.

Generally, in the logic design, the LSI is embodied up to the level of a unit of logic gate (NAND, inverter, etc.) based on the functional design data. In the functional design, the design work is being advanced with a focus on the operation of the LSI, whereas in the logic design, the design is focused on the gate-to-gate connection relationship, that is, the logic circuit structure. The design is advanced using a structure description language represented by SDL and HSL and a logic diagram, and the basic gate used in the logic design is prepared in advance through device design and circuit design. This is done using the logic cell library menu that is available. Usually, the logic cell library includes cells of several to ten or more gates such as a composite gate, a flip-flop, and a three-state driver in addition to a simple basic gate, which facilitates the design.

[Conventional technology]

Languages used in the logic design stage can be roughly classified into a behavioral description language that describes the behavior of input data versus output data and a structural description language that describes the connection state of functional blocks. The behavioral description, for example, describes the flow to the expected output data for the input data series, and uses flowcharts and state diagrams.The structural description describes the modules and submodules that the system is composed of. A block diagram or a logic circuit diagram is used as a method of describing whether or not there is. The functional description is a description model centered on the operation, whereas the structural description uses a model based on the connection relation as a network. Since the actual logic is established by the connection between the transistors, it can be said that the structural description is the description style closest to the real thing. In the structural description, it is basically based on describing each gate terminal and each terminal connection relationship one by one. Therefore, it is possible to completely express the static logical network. Further, since it is equivalent to the logic diagram in which the gates are connected, all the details of the logic circuit can be read from the structure description.

The structural description is classified into a fan-out method, a fan-in method, and the like, which advances the description by focusing on the gate, and a network method, which advances the description by focusing on the network. The former is suitable for an input language of a logic simulator because it always describes the signal flow between gates, and the amount of description is relatively small, but bidirectional paths, wired logic, etc. When you describe, it is necessary to take special measures. The description of the network method can describe the connection between terminals without explicitly indicating the flow of signals, and is excellent in describing bidirectional paths and bidirectional gates in addition to ordinary logical connections. It is convenient for describing various transmission gates such as MOS logics of recent years.

The structure-described design data has the characteristic that it can be used by adjusting details without requiring conceptual conversion when passing data to a placement / wiring program, and is the most basic language system as an LSI design language. Has become.
In the structure description, design methods such as hierarchization and structuring can be easily accepted due to the characteristics of the language. In the case of a functional description, hierarchization is possible only in block units registered as resources, whereas in a structural description, a hierarchy can be constructed independently of a block of logical functions. This is very useful when performing simulations / circuit simulations and designing blocks and cells of different scales side by side at the layout stage.

As a conventional method of manufacturing this type of semiconductor device, there is a design method as shown in FIGS. In FIG. 7, when a chip 1 named ABCDE as shown in FIG. 7 is logically designed (hereinafter referred to as appropriate design), first, a block 2 of a unit ABCDE is described, and then ABCD. Block 3 of unit and block 4 of E are described, and block 3 (ABC
Blocks 5 and 6 of AB and CD are described in D), blocks 7 and 8 of A and B are described in block 5 (AB), and blocks of C and D are described in block 6 (CD). 9 and 10 are described, and a logical description is performed for each of all blocks.

To explain this in more detail, all the pin names shown in the figure (in the figure, only the pin names P1 to P5 relating to the block 2 (ABCDE) are shown), and the internal pins used as external pins are indicated. It is necessary to describe each pin and then to which pin the net name is connected. Here, the pin names are not limited to those appearing outside, but each block 2 to 10 (ABCDE, ABCD, AB, CD, A,
B, C, D, E) means all pins. That is, the pin name and its connection relationship are shown in block 2 (ABCD
E) After properly describing each, next, describe the block 3 (ABCD) in the same manner as above, specify the nets and pin names of all the blocks in the same procedure, and after that, make sure to keep the pin connection relationship. Work to describe is required. That is, such processing is performed by ABCDE, A
They are all described as BCD, AB, CD, E. Table 1 below shows an example in which only the block 2 of the chip 1 shown in FIG. 7 is described.

Table 1 NAME: ABCDE; LEVEL: CHiP; EXTi: i1, i2; EXTO: O1, O2, O3; PiN: P1, P2, P3, P4, P5; NET: N1, N4, N5, N6, N7; SuB CONCECT N1: i1, P1-ABCD; N4: P3-ABCD, O1; N5: P4-ABCD, O2; N6: i2, P2-E; N7: P5-E, O3; END; The table is an example in which only block 2 (ABDCE) is declared, but it goes without saying that the same procedure as in the case shown in Table 1 is used to sequentially declare all the layers. Therefore, a certain pin is repeatedly and repeatedly declared in each block.

FIG. 8 is a flow chart showing a program of the above-mentioned conventional design method. First, in STEP 1, the logical description as shown in Table 1 is made for all layers of the entire chip,
In STEP 3, it is determined whether or not there is a correction due to the cell arrangement change or the like shown in STEP 2, and if there is a correction, STEP
If it does not exist, the process ends. STEP
In step 4, the correction is performed while being aware of the mutual relations of all layers, the logical description of all layers is prepared, and the process returns to STEP 3 again.

[Problems to be solved by the invention]

However, in such a conventional LSI automatic design method, when the scale of the LSI becomes large and the hierarchy in the logic design progresses, the amount of logic description becomes enormous, and the time and effort required for correction are also great. There has been a problem that the design becomes so large that the efficiency of the design cannot be improved.

In other words, as the scale of the LSI increases and the hierarchy deepens, the amount of description becomes enormous, as is apparent from the examples of FIG. 7 and Table 1 described above, and an error or the like inevitably occurs during the description. It will be. In addition, when correcting such an error or correcting the logic, it is necessary to correct the entire hierarchy and the connection relationship, which requires a lot of trouble. For example, when the logic correction is performed after the cell layout inside the LSI is completed, it is necessary to be conscious of the mutual relation of all related layers, and
In the logic design of an LSI, the logic description of all layers is required to design one chip. Therefore, if there is a correction, it is necessary to check all the layers related to the correction, which causes a design error. Also, a single design error affects all related hierarchies. As the scale of LSI becomes larger, the amount of logic description becomes enormous and the hierarchy becomes deeper. Therefore, once the logic is corrected, the burden on the designer becomes heavy. On the other hand. Furthermore, when the description shown in Table 1 is completed, the compiler process is usually performed on the machine. However, if a mistake is made at this point, it is necessary to redo the entire process. Will be very large.

It is therefore an object of the present invention to provide a method of manufacturing a semiconductor device that requires a small amount of logical description, can be efficiently designed even when the hierarchy is deep, and can be easily modified.

[Means for solving problems]

In order to achieve the above object, the method of manufacturing a semiconductor device according to the present invention designates an internal cell that constitutes a logical block of an LSI chip for each hierarchy by a predetermined description language that describes a hierarchical relationship and a connection relationship, and In a method of manufacturing a semiconductor device in which layers and connection relationships in all layers are automatically generated to automatically design an LSI, a logical description of the block is performed using a net name unique to the chip, and the hierarchical relationship of the chip is defined. By designating and designing the lowest hierarchy, when the upper hierarchy occurs, external terminals are automatically generated using the net name, and the logic design up to the highest hierarchy is performed.

[Work]

In the present invention, the logic design of the lowest layer is performed using the net name unique to the LSI, and when the upper layer is generated, external terminals are automatically generated using the net name, and the automatic design up to the highest layer is performed. Be seen.

Therefore, the amount of logical description is reduced, and efficient logical design and modification are performed.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

Description of Principle FIG. 1 is a diagram for explaining the principle of the present invention. Conventionally, a net name when designing the logic of an LSI has been made unique within one hierarchy. On the other hand, according to the present invention, by using a method of performing logical design using a unique net name (global net name) in a chip, the designer does not need the logical description between layers, which is conventionally required. It is possible to reduce the burden of. That is, since the net name is unique within the chip 11, it can be understood that when a net with the same name appears, the nets should be connected without logical description between layers. Therefore, the designer uses the global net name to separately logically design and design each block 12 to 15 as shown in A, B, C, and D of FIG. 1 to design the outermost (chip level) outside. It suffices to indicate the net name connected to the terminal and the parent-child relationship between layers (see Table 2).

Then, necessary blocks are collected based on the net names shown by N1 to N5 in FIG. 1, and external terminals are automatically generated for the net name connected to the outside to a higher hierarchy (blocks 16 in FIG. , 17). Here, the mark in the figure shows the automatically generated external terminal, and the mark in FIG. 7 mentioned above and FIGS. 2 and 6 described later have the same meaning. The hierarchies generated in this way are gathered again based on the net name to generate higher hierarchies. By repeating this process,
Automatic design up to the chip level is possible. That is, it is possible to eliminate the need to describe the relationship between the upper hierarchy and the lower hierarchy by logically describing the lowest level hierarchy and generating the upper hierarchy one by one in a stacking manner. Also, even if the logic is modified, you only need to modify the lowest level hierarchy involved,
It is possible to eliminate the need to consider the hierarchical relationship of layers.

First Embodiment Next, a designing method based on the above principle will be described as an embodiment. 2 to 4 are views showing a first embodiment of the present invention,
In this embodiment, the automatic design method of the present invention is applied to the same chip design method as the LSI chip described in the conventional example of FIG. The same components as those shown in FIG. 7 are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 2, let us consider a case where the same chip 1 as that of the conventional example shown in FIG. 7, which is named ABCDE, is logically designed as shown in FIG. First, as shown in FIG. 3, five blocks 21 to 25, A, B, C, D, and E, are logically described and designed, and then the hierarchical relationships shown in Table 3 are designated.

Table 3 NAME: ABCDE; LEVEL: 1; IN: N1, N6; OUT; N4, N5, N7; SUB: ACBD, E; NAME: ABCD; LEVEL: 2; SUB: AB, CD; NAME: AB; LEVEL : 3; SUB: A, B; NAME: CD; LEVEL: 3; SUB: C, D; In this example, from the lowest level (ie, the highest number after LEVEL in Table 3). , To perform processing. Then, the blocks A and B are gathered together and treated as a black box, and the net names (N1, N2, 3) used other than A and B must be connected to the outside of AB. Occurrence occurs, and the upper level AB is automatically generated. Similarly, a CD is automatically generated, and AB and CD are collected together to generate block 3 (ABCD) in the same manner. Finally, block 3 (ABCD) and block 4 (E) are gathered together,
Chip 1 (ABCDE) is generated. By thus designing the block level hierarchy, the hierarchical structure up to the chip level as shown in FIG. 2 can be automatically designed.

Next, the operation will be described.

FIG. 4 is a flowchart showing a program of the automatic design method. First, in STEP 11, the logical name of each block is written using the net name unique to the chip, and in STEP 12, the hierarchical relationship within the chip is specified. Therefore, as shown in FIG. 3, blocks 21 to 25 called A, B, C, D, and E.
Are designed separately, and a unique net name is used for each block 21 to 25. For example, as shown in the figure, both A and B (net name) N1
To turn on. Next, in STEP 13, the logical design up to the chip level is automatically performed as specified by using the net name as a key, and in STEP 14, it is determined whether or not there is a correction. When there is a correction, the process proceeds to STEP 15, and when there is no correction. Ends the process as it is. In STEP15, the logical description is corrected only in the block involved in the correction, and in STEP16, when the hierarchical relationship is also corrected, it is specified and corrected, and the STE is again specified.
Return to P13.

As described above, in the present embodiment, the logical design of the lowest layer is performed by using the net name unique to the LSI, and the external terminal is automatically generated by using the net name when the upper layer is generated. However, it can be designed efficiently even when considering a deep hierarchy, leading to a reduction in design mistakes. Further, bottom-up type and top-down type design methods can be used together in one chip, such as stacking blocks in one layer in a chip and solidly designing another layer. In addition, it is an advantage of this method that they can be used properly in a hierarchy with a lot of modifications and a hierarchy with a few modifications.

Second Embodiment FIGS. 5 and 6 show a second embodiment of the present invention. This embodiment shows an example in which the logic design of the chip of the first embodiment is modified. In this embodiment, the same components as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 2, inputs to the block 10 (D) are N1 and N.
It is done by 3. Now, suppose that the output signal of the block 4 (E) is to be input to the block 10 (D) instead of the signal carried by N1. In this case, it is only necessary to redesign only the layer D to be modified as shown in block 31 of FIG. Then, in the same manner as the automatic design in the first embodiment, the upper layers are stacked one by one to finally produce a chip having a structure as shown in FIG.

Therefore, for example, in the conventional example, if you try to modify somewhere after completing the cell arrangement, you have to rewrite it (that is, you must rewrite the entire configuration while being aware of the hierarchical relationship). However, in the present invention, it is necessary to modify only the related blocks, and the workability can be greatly improved. It is needless to say that only the above-mentioned Table 3 needs to be modified to correct the hierarchical relationship.

〔The invention's effect〕

According to the present invention, the lowest hierarchy is logically designed using the net name unique to the LSI, and when the upper hierarchy is generated, the external name is automatically generated using the net name to automatically design the highest hierarchy. Therefore, the amount of logic description of the automatic design method for a large scale integrated circuit is small, and even if the hierarchy is deep, the design can be performed efficiently and the correction can be easily performed.

[Brief description of drawings]

FIG. 1 is a logical configuration diagram showing a principle explanation of a method of manufacturing a semiconductor device according to the present invention, and FIGS. 2 to 4 are first diagrams of a method of manufacturing a semiconductor device according to the present invention.
FIG. 2 is a diagram showing an embodiment, FIG. 2 is its logical configuration diagram, FIG. 3 is a block diagram showing its logical description, FIG. 4 is a flow chart showing a program of its automatic design method, and FIGS. Second Method of Manufacturing Semiconductor Device According to Invention
FIG. 5 is a diagram showing an embodiment, FIG. 5 is a block diagram showing its logical description, FIG. 6 is its logical configuration diagram, and FIGS. 7 and 8 are diagrams showing a conventional method of manufacturing a semiconductor device. FIG. 8 is a logical configuration diagram thereof, and FIG. 8 is a flow chart showing a program of the automatic design method. 1, 11; chip (LSI chip), 2 to 10, 12 to 17: block, N1 to N7: net name.

Claims (1)

[Claims] 1. An internal cell forming a logical block of an LSI chip is designated for each layer by a predetermined description language for describing a layer relation and a connection relation, and the layers and the connection relation in all layers of the cell are automatically specified. In a method of manufacturing a semiconductor device for automatically designing an LSI, a logical description of the block is performed using a net name unique to the chip, and a hierarchical relationship of the chip is specified to perform a logical design of the lowest hierarchy. A method of manufacturing a semiconductor device, characterized in that, when an upper layer is generated, an external terminal is automatically generated by using the net name to perform logic design up to the uppermost layer.