JPH0646727B2 - Clock reproduction circuit - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a digital phase-locked loop (digital P).
LL) type clock recovery circuit.

[Technical Background of the Invention] As a conventional digital PLL type clock recovery circuit, for example, there is one as shown in FIG. This clock recovery circuit comprises a waveform shaping circuit 1, a differentiation circuit 2, a phase comparator 3, a racing counter 4, a high speed clock generator 5, a programmable frequency divider 6, and a fixed frequency divider 7, which are input from an input terminal A. The reproduced clock signal b is output from the output terminal B so as to coincide with the polarity conversion point of the digital signal a.

The digital signal a input to the input terminal A is shaped by the waveform shaping circuit 1 and then guided to the differentiating circuit 2. The differentiating circuit 2 generates a polarity conversion point composed of a differential pulse that matches at least one of the polarity conversion points (rising and falling) of the digital signal, and the signal d, which is input to the phase comparator 3. The output signal e of the fixed frequency divider 7 is also input to the phase comparator 3, and a phase delay signal or a phase advance signal is generated from the phase comparator 3 depending on the phase relationship between the differential pulse d and the output signal e and is guided to the racing counter 4. . The racing counter 4 generates a lead control signal when the phase lag signal is continuously counted N times, and the programmable frequency divider 6
Decrement the frequency division of by one. On the contrary, when the racing counter 4 counts the phase lead signal continuously N times, the delay control signal is generated and the frequency division number of the programmable frequency divider 6 is increased by one. The programmable frequency divider 6 includes a high-speed clock generator 5
The high-speed clock signal c is input from the input terminal, the high-speed clock signal c is divided by a predetermined frequency division number, and then further divided by the fixed frequency divider 7, and the reproduction clock signal b is output from the output terminal B. In this way, the reproduced clock signal b is controlled so that its rising edge coincides with the polarity conversion point of the digital signal a.

In such a clock recovery circuit, the parameters of each element are set as follows, for example.

Then, when the respective parameters are set as described above, the jitter Δθ of the reproduced clock signal becomes as follows.

Δθ = 360 ° / (× m) = 2.8 ° (2) When the phase difference between the input digital signal a and the output reproduced clock signal b is controlled from 180 ° to 0 ° for the pull-in time tp Becomes the maximum value and at this time, tp = (1 / 2f _CKR ) ×× m × N = (32 × 4 × 4) / (2 × 16) = 16 msec (3).

[Problems of the Background Art] By the way, in the case where the receiving device is located under fading like digital mobile communication, the jitter Δθ is small and the error due to the jitter is as small as possible when the receiving condition of the clock recovery circuit is good. It is desired that when the reception state becomes poor and the clock recovery circuit becomes out of synchronization, when the reception state becomes good again next time, it is desirable to pull in in a short time.

However, in the conventional clock recovery circuit (2)
As can be seen from the equations and the equation (3), if the fixed frequency division number is reduced in order to shorten the pull-in time tp, the jitter Δθ becomes large, and the pull-in time tp for reducing the jitter Δθ becomes long. there were.

Further, when the synchronization is lost, the synchronization is suddenly attempted to be accurately performed, which causes a problem that the pull-in time becomes long.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a clock recovery circuit capable of efficiently performing synchronization pull-in even in an environment where the received electric field changes due to fading or the like in order to solve the above problems.

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention is provided with a first programmable frequency divider, a second programmable frequency divider and a fixed frequency divider which are connected in series to a high speed clock generator, and is input from the outside. A differentiating circuit for differentiating a digital signal, a phase comparator for comparing the output signal of the differentiating circuit and the output signal of the fixed frequency divider, and outputting a phase lead / lag signal, and a signal-to-noise ratio of the digital signal When the signal-to-noise ratio is determined to be “good”, the frequency division number of the second programmable frequency divider is fixed, and when the signal-to-noise ratio is determined to be “fail”. Is an S / N determination circuit which fixes the frequency division number of the first programmable frequency divider, and which of the first and second programmable frequency dividers is not fixed when the phase lead / lag signal is counted by a predetermined number. The variable number that can be changed And a sourcing counter.

[Examples of the Invention] Examples of the present invention will be described in detail below. FIG. 1 is a circuit diagram of a clock recovery circuit according to one embodiment of the present invention. In the figure, elements having the same functions as those of the conventional example shown in FIG.

In this embodiment, the first programmable frequency divider 8 and the second programmable frequency divider 9 are connected in series to the high-speed clock generator 5 and the S / N ratio (signal-to-noise ratio) of the input digital signal a is determined. An S / N determination circuit 10 for performing the above is provided.
The S / N determination circuit 10 includes a timing circuit 11, an up / down control circuit (hereinafter referred to as UD control circuit) 12, an up / down counter 13, and an S / N determination circuit 14.

The timing circuit 11 uses the detected polarity conversion point signal d as a reference to generate a prediction signal f having a relatively short pulse width centered after the data cycle.

When the signal d is generated within the time when the signal f exists, the UD control circuit 12 causes the up / down counter 13 of the next stage.
On the other hand, when the down signal g is transmitted and the signal d is generated outside the time when the signal f exists, the up signal h is transmitted to the up / down counter 13. The up / down counter 13 changes the counting state by the down signal g and the up signal h, and supplies the count value for a certain period to the S / N discrimination circuit 14 at the next stage as S / N discrimination data. For example, when the count value # 10 of the 16-stage up / down counter 13 is set as the threshold level, the S / N determination circuit 14 determines the S / N as good when the count value is # 1 to # 10. And the output signal i is set to a high level. If the count value is in # 11 to # 16, S / N
Is determined to be no, and the S / N determination output signal i is set to low level.

Judgment C / N value of S / N judgment circuit 10 (carrier to noise ratio)
Can be arbitrarily designed according to the pulse width of the prediction signal f generated in the timing circuit 11. (For example, C / N =
(10 dB) This determination C / N value is set to be slightly higher than the C / N (for example, C / N = 6 dB) at which the clock recovery circuit causes the loss of synchronization.

The S / N determination output signal i is guided to the first and second programmable frequency dividers 8 and 9, and when the S / N is good (the signal i is "H"), the programmable frequency divider 9 divides the frequency by m. Fixed to
The programmable frequency divider 8 is controlled by the output of the racing counter 4. This mode is hereinafter referred to as a protection mode. On the contrary, when the S / N is negative (the signal i is “L”), the programmable frequency divider 8 fixes the frequency division number n, and the programmable frequency divider 9 is controlled by the output of the racing counter 4. Hereinafter, this mode is called an attack mode.

The parameters of this clock recovery circuit are as follows.

And the output of the racing counter is 1st when S / N is good.
The signal is supplied to the programmable frequency divider 8 and is supplied to the second programmable frequency divider 9 when the S / N ratio is bad.

When the parameters are determined as shown in the equation (4), the jitter Δθ of the reproduced clock signal and the pull-in time tp are as follows.

Jitter Δθ In case of protection mode Δθ ₁ = 360 ° / '× m × n) = 2.8 ° In case of attack mode Δθ ₂ = 360 ° /' × m = 11.25 ° Pull-in time tp In case of protection mode tp ₁ = (1 / 2f _CKR ) × '× m × n × N = (8 × 4 × 4 × 4) / (2 × 16K) = 16msec In case of attack mode tp ₂ = (1 / 2f _CKR ) ×' × m × N 2 = (8 × 4 × 4) / (2 × 16K) = 4 msec Further, when the discrimination bit of the S / N discrimination circuit 14 is 16 bits, the discrimination time tg is tg = 16 bits / (16 kb / s) = 1 msec. (9)

The degree to which the received electric field drops due to fading or the like and the clock recovery circuit loses synchronization, for example, C / N <6 dB
In the case of, the S / N determination circuit 6 determines the S / N to be “NO”, and the first programmable frequency divider 8 is fixed and the second programmable frequency divider 9 is in the attack mode controlled by the output of the racing counter 4. Become.

That is, in this case, jitter Δθ = 11.25 ° pull-in time tp
= 4 msec.

Next, the received electric field gradually recovers, and 6 dB <C / N <10 d
In the case of the state B, the S / N determination circuit 6 is S / N even in this case.
Since N is determined to be "no", clock reproduction is synchronized in the attack mode.

At this time, the maximum pull-in time is tg + tp ₂ = 1 msec +
4 msec = 5 msec, which is short-circuited to about 1/3 in this numerical example compared to the protection mode. This C /
Jitter Δθ ₂ generated in the attack mode in the N section
The deterioration of the bit error rate due to = 11.25 ° can be ignored.

When the received electric field becomes even better and C / N> 10 dB, S
The / N determination circuit determines S / N to be “good” and switches from the attack mode to the protection mode. The pull-in time at this switching is t'p = (1 / 16f _CKR ) × '× m × n × N = (8 × 4 × 4 × 4) / (16 × 16k) = 2 msec, and the S / N judgment circuit Considering the determination time (equation (9)) tg of 14, tg + tp '= 1 msec + 2 msec = 3 msec, which enables quick switching. After this switching is performed, it becomes a complete protection mode.

Therefore, when the S / N is bad, the attack mode is set to speed up the synchronization pull-in time of the clock recovery circuit, and when the S / N is good, the protection mode is switched to reduce the jitter and bit error due to the jitter. The deterioration of the rate can be made as small as possible.
At this time, the pull-in time is relatively fast because the attack mode is synchronized with the protection mode from the already synchronized state in the protection mode more quickly.

[Effects of the Invention] An environment in which the reception electric field changes due to fading or the like by switching the mode of the digital PLL clock recovery circuit according to the reception state by using the S / N determination circuit that determines the reception state as described above. It is possible to provide a clock recovery circuit that efficiently performs synchronization pull-in even under the condition.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a clock recovery circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional clock recovery circuit. DESCRIPTION OF SYMBOLS 1 ... Waveform shaping circuit, 2 ... Differentiation circuit, 3 ... Phase comparator, 4 ... Racing counter, 5 ... High-speed clock generator, 7 ... Fixed frequency divider, 8 ... 1st programmable frequency divider, 9 ... 2nd programmable Frequency divider, 10 ... S / N determination circuit, 11 ... Timing circuit, 12 ... UD control circuit, 13 ... Up-down counter,
14 ... S / N discrimination circuit.

Claims (1)

[Claims] 1. A first serially connected high speed clock generator.
A programmable frequency divider, a second programmable frequency divider, and a fixed frequency divider, a differentiation circuit that differentiates a digital signal input from the outside, and a phase of the output signal of the differentiation circuit and the output signal of the fixed frequency divider. And a phase comparator that outputs a phase lead / lag signal, and determines whether the signal-to-noise ratio of the digital signal is good or bad,
When the signal-to-noise ratio is determined to be “good”, the frequency division number of the second programmable frequency divider is fixed, and when the signal-to-noise ratio is determined to be “not”, the first programmable frequency divider An S / N determination circuit that fixes the frequency division number of the first and second phases
And a racing counter for varying the frequency division number of the second programmable frequency divider which is not fixed.